diff options
| author | Ryan Wanner <Ryan.Wanner@microchip.com> | 2025-09-08 13:07:17 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-11-13 15:34:33 -0500 |
| commit | 0fbbc9973997ba075fa72fe17db094c8a6f4c259 (patch) | |
| tree | c14cd88f214cd3849bff6dbf8dcbf524892c691d /drivers/clk | |
| parent | 7af4f219766d58d21208e63cfafda873eb376cb6 (diff) | |
| download | linux-0fbbc9973997ba075fa72fe17db094c8a6f4c259.tar.gz linux-0fbbc9973997ba075fa72fe17db094c8a6f4c259.tar.bz2 linux-0fbbc9973997ba075fa72fe17db094c8a6f4c259.zip | |
clk: at91: clk-master: Add check for divide by 3
[ Upstream commit e0237f5635727d64635ec6665e1de9f4cacce35c ]
A potential divider for the master clock is div/3. The register
configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
method does not work for this case. Checking for MASTER_PRES_MAX will
ensure the correct decimal value is stored in the system.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/at91/clk-master.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 15c46489ba85..4c87a0f789de 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw, { struct clk_master *master = to_clk_master(hw); + if (master->div == MASTER_PRES_MAX) + return DIV_ROUND_CLOSEST_ULL(parent_rate, 3); + return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div)); } |