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author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-04 12:05:32 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-05-04 12:05:32 -0700 |
commit | 2bd80401743568ced7d303b008ae5298ce77e695 (patch) | |
tree | d70278682fca619f7d842faa7c5a5bdce5016cfa /drivers/gpio/gpio-ws16c48.c | |
parent | 99a7583de5ffd5cd82c407aad32bcbdeea09155b (diff) | |
parent | b86c86aa9805b25ee70071d084e618b2c40641b5 (diff) | |
download | linux-2bd80401743568ced7d303b008ae5298ce77e695.tar.gz linux-2bd80401743568ced7d303b008ae5298ce77e695.tar.bz2 linux-2bd80401743568ced7d303b008ae5298ce77e695.zip |
Merge tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull GPIO updates from Linus Walleij:
"This is the bulk of GPIO changes for the v4.12 kernel cycle.
Core changes:
- Return NULL from gpiod_get_optional() when GPIOLIB is disabled.
This was a much discussed change. It affects use cases where people
write drivers that might or might not be using GPIO resources. I
have decided that this is the lesser evil right now.
- Make gpiod_count() behave consistently across different hardware
descriptions.
- Fix the syntax around open drain/open source to not infer active
high/low semantics.
New drivers:
- A new single-register fixed-direction framework driver for hardware
that have lines controlled by a single register that just work in
one direction (out or in), including IRQ support.
- Support the Fintek F71889A GPIO SuperIO controller.
- Support the National NI 169445 MMIO GPIO.
- Support for the X-Gene derivative of the DWC GPIO controller
- Support for the Rohm BD9571MWV-M PMIC GPIO controller.
- Refactor the Gemini GPIO driver to a generic Faraday FTGPIO driver
and replace both the Gemini and the Moxa ART custom drivers with
this driver.
Driver improvements:
- A whole slew of drivers have their spinlocks chaned to raw
spinlocks as they provide irqchips, and thus we are progressing on
realtime compliance.
- Use devm_irq_alloc_descs() in a slew of drivers, getting managed
resources.
- Support for the embedded PWM controller inside the MVEBU driver.
- Debounce, open source and open drain support for the Aspeed driver.
- Misc smaller fixes like spelling and syntax and whatnot"
* tag 'gpio-v4.12-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (77 commits)
gpio: f7188x: Add a missing break
gpio: omap: return error if requested debounce time is not possible
gpio: Add ROHM BD9571MWV-M PMIC GPIO driver
gpio: gpio-wcove: fix GPIO IRQ status mask
gpio: DT bindings, move tca9554 from pcf857x to pca953x
gpio: move tca9554 from pcf857x to pca953x
gpio: arizona: Correct check whether the pin is an input
gpio: Add XRA1403 DTS binding documentation
dt-bindings: add exar to vendor prefixes list
gpio: gpio-wcove: fix irq pending status bit width
gpio: dwapb: use dwapb_read instead of readl_relaxed
gpio: aspeed: Add open-source and open-drain support
gpio: aspeed: Add debounce support
gpio: aspeed: dt: Add optional clocks property
gpio: aspeed: dt: Fix description alignment in bindings document
gpio: mvebu: Add limited PWM support
gpio: Use unsigned int for interrupt numbers
gpio: f7188x: Add F71889A GPIO support.
gpio: core: Decouple open drain/source flag with active low/high
gpio: arizona: Correct handling for reading input GPIOs
...
Diffstat (limited to 'drivers/gpio/gpio-ws16c48.c')
-rw-r--r-- | drivers/gpio/gpio-ws16c48.c | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/drivers/gpio/gpio-ws16c48.c b/drivers/gpio/gpio-ws16c48.c index 901b5ccb032d..87d63695dfcf 100644 --- a/drivers/gpio/gpio-ws16c48.c +++ b/drivers/gpio/gpio-ws16c48.c @@ -51,7 +51,7 @@ struct ws16c48_gpio { struct gpio_chip chip; unsigned char io_state[6]; unsigned char out_state[6]; - spinlock_t lock; + raw_spinlock_t lock; unsigned long irq_mask; unsigned long flow_mask; unsigned base; @@ -73,13 +73,13 @@ static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset) const unsigned mask = BIT(offset % 8); unsigned long flags; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); ws16c48gpio->io_state[port] |= mask; ws16c48gpio->out_state[port] &= ~mask; outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); return 0; } @@ -92,7 +92,7 @@ static int ws16c48_gpio_direction_output(struct gpio_chip *chip, const unsigned mask = BIT(offset % 8); unsigned long flags; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); ws16c48gpio->io_state[port] &= ~mask; if (value) @@ -101,7 +101,7 @@ static int ws16c48_gpio_direction_output(struct gpio_chip *chip, ws16c48gpio->out_state[port] &= ~mask; outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); return 0; } @@ -114,17 +114,17 @@ static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset) unsigned long flags; unsigned port_state; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); /* ensure that GPIO is set for input */ if (!(ws16c48gpio->io_state[port] & mask)) { - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); return -EINVAL; } port_state = inb(ws16c48gpio->base + port); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); return !!(port_state & mask); } @@ -136,11 +136,11 @@ static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value) const unsigned mask = BIT(offset % 8); unsigned long flags; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); /* ensure that GPIO is set for output */ if (ws16c48gpio->io_state[port] & mask) { - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); return; } @@ -150,7 +150,7 @@ static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value) ws16c48gpio->out_state[port] &= ~mask; outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, @@ -178,14 +178,14 @@ static void ws16c48_gpio_set_multiple(struct gpio_chip *chip, iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port]; bitmask = iomask & bits[BIT_WORD(i)]; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); /* update output state data and set device gpio register */ ws16c48gpio->out_state[port] &= ~iomask; ws16c48gpio->out_state[port] |= bitmask; outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); /* prepare for next gpio register set */ mask[BIT_WORD(i)] >>= gpio_reg_size; @@ -207,7 +207,7 @@ static void ws16c48_irq_ack(struct irq_data *data) if (port > 2) return; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); port_state = ws16c48gpio->irq_mask >> (8*port); @@ -216,7 +216,7 @@ static void ws16c48_irq_ack(struct irq_data *data) outb(port_state | mask, ws16c48gpio->base + 8 + port); outb(0xC0, ws16c48gpio->base + 7); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } static void ws16c48_irq_mask(struct irq_data *data) @@ -232,7 +232,7 @@ static void ws16c48_irq_mask(struct irq_data *data) if (port > 2) return; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); ws16c48gpio->irq_mask &= ~mask; @@ -240,7 +240,7 @@ static void ws16c48_irq_mask(struct irq_data *data) outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); outb(0xC0, ws16c48gpio->base + 7); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } static void ws16c48_irq_unmask(struct irq_data *data) @@ -256,7 +256,7 @@ static void ws16c48_irq_unmask(struct irq_data *data) if (port > 2) return; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); ws16c48gpio->irq_mask |= mask; @@ -264,7 +264,7 @@ static void ws16c48_irq_unmask(struct irq_data *data) outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port); outb(0xC0, ws16c48gpio->base + 7); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); } static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) @@ -280,7 +280,7 @@ static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) if (port > 2) return -EINVAL; - spin_lock_irqsave(&ws16c48gpio->lock, flags); + raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); switch (flow_type) { case IRQ_TYPE_NONE: @@ -292,7 +292,7 @@ static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) ws16c48gpio->flow_mask &= ~mask; break; default: - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); return -EINVAL; } @@ -300,7 +300,7 @@ static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type) outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port); outb(0xC0, ws16c48gpio->base + 7); - spin_unlock_irqrestore(&ws16c48gpio->lock, flags); + raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags); return 0; } @@ -387,7 +387,7 @@ static int ws16c48_probe(struct device *dev, unsigned int id) ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple; ws16c48gpio->base = base[id]; - spin_lock_init(&ws16c48gpio->lock); + raw_spin_lock_init(&ws16c48gpio->lock); err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio); if (err) { |