diff options
| author | Andrey Grodzovsky <andrey.grodzovsky@amd.com> | 2021-12-06 14:59:35 -0500 |
|---|---|---|
| committer | Andrey Grodzovsky <andrey.grodzovsky@amd.com> | 2022-02-09 12:15:04 -0500 |
| commit | 5fd8518d187ed03403a4d4f7f56f52c00b11c148 (patch) | |
| tree | 52eb7f73ebb898c8be2ea5f86eb7c10a968a0311 /drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | |
| parent | a4c63cafa58b4bd9e15511bab77a4752b93d3aa0 (diff) | |
| download | linux-5fd8518d187ed03403a4d4f7f56f52c00b11c148.tar.gz linux-5fd8518d187ed03403a4d4f7f56f52c00b11c148.tar.bz2 linux-5fd8518d187ed03403a4d4f7f56f52c00b11c148.zip | |
drm/amdgpu: Move scheduler init to after XGMI is ready
Before we initialize schedulers we must know which reset
domain are we in - for single device there iis a single
domain per device and so single wq per device. For XGMI
the reset domain spans the entire XGMI hive and so the
reset wq is per hive.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Link: https://www.spinics.net/lists/amd-gfx/msg74112.html
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index fae7d185ad0d..48365da213dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -114,9 +114,7 @@ struct amdgpu_fence_driver { void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring); void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); -int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, - unsigned num_hw_submission, - atomic_t *sched_score); +int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, struct amdgpu_irq_src *irq_src, unsigned irq_type); @@ -251,6 +249,8 @@ struct amdgpu_ring { bool has_compute_vm_bug; bool no_scheduler; int hw_prio; + unsigned num_hw_submission; + atomic_t *sched_score; }; #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) |