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authorHawking Zhang <Hawking.Zhang@amd.com>2020-12-07 20:17:45 +0800
committerAlex Deucher <alexander.deucher@amd.com>2021-03-10 00:01:00 -0500
commitb9dd2add842c0e4d50cbafe135356c2431fdbc8b (patch)
tree8829c6d33cdc251f70c4e449498bd5515eb7f721 /drivers/gpu/drm/amd/include
parent301a16138285ebfce961dbaa7d9da86c26ca7428 (diff)
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drm/amdgpu: add mmhub v1_7 ip headers (v3)
v1: Add mmhub v1_7 register offset and shift masks in header files (Hawking) v2: Clean up mmhub v1_7 registers (Alex) v3: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h5125
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_sh_mask.h32178
2 files changed, 37303 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h
new file mode 100644
index 000000000000..adb7a21e2a10
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_7_offset.h
@@ -0,0 +1,5125 @@
+/*
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _mmhub_1_7_OFFSET_HEADER
+#define _mmhub_1_7_OFFSET_HEADER
+
+
+
+// addressBlock: mmhub_dagb_dagbdec0
+// base address: 0x68000
+#define regDAGB0_RDCLI0 0x0000
+#define regDAGB0_RDCLI0_BASE_IDX 0
+#define regDAGB0_RDCLI1 0x0001
+#define regDAGB0_RDCLI1_BASE_IDX 0
+#define regDAGB0_RDCLI2 0x0002
+#define regDAGB0_RDCLI2_BASE_IDX 0
+#define regDAGB0_RDCLI3 0x0003
+#define regDAGB0_RDCLI3_BASE_IDX 0
+#define regDAGB0_RDCLI4 0x0004
+#define regDAGB0_RDCLI4_BASE_IDX 0
+#define regDAGB0_RDCLI5 0x0005
+#define regDAGB0_RDCLI5_BASE_IDX 0
+#define regDAGB0_RDCLI6 0x0006
+#define regDAGB0_RDCLI6_BASE_IDX 0
+#define regDAGB0_RDCLI7 0x0007
+#define regDAGB0_RDCLI7_BASE_IDX 0
+#define regDAGB0_RDCLI8 0x0008
+#define regDAGB0_RDCLI8_BASE_IDX 0
+#define regDAGB0_RDCLI9 0x0009
+#define regDAGB0_RDCLI9_BASE_IDX 0
+#define regDAGB0_RDCLI10 0x000a
+#define regDAGB0_RDCLI10_BASE_IDX 0
+#define regDAGB0_RDCLI11 0x000b
+#define regDAGB0_RDCLI11_BASE_IDX 0
+#define regDAGB0_RDCLI12 0x000c
+#define regDAGB0_RDCLI12_BASE_IDX 0
+#define regDAGB0_RDCLI13 0x000d
+#define regDAGB0_RDCLI13_BASE_IDX 0
+#define regDAGB0_RDCLI14 0x000e
+#define regDAGB0_RDCLI14_BASE_IDX 0
+#define regDAGB0_RDCLI15 0x000f
+#define regDAGB0_RDCLI15_BASE_IDX 0
+#define regDAGB0_RD_CNTL 0x0010
+#define regDAGB0_RD_CNTL_BASE_IDX 0
+#define regDAGB0_RD_GMI_CNTL 0x0011
+#define regDAGB0_RD_GMI_CNTL_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB 0x0012
+#define regDAGB0_RD_ADDR_DAGB_BASE_IDX 0
+#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013
+#define regDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014
+#define regDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB0_RD_CGTT_CLK_CTRL 0x0015
+#define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016
+#define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017
+#define regDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a
+#define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b
+#define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB0_RD_VC0_CNTL 0x001c
+#define regDAGB0_RD_VC0_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC1_CNTL 0x001d
+#define regDAGB0_RD_VC1_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC2_CNTL 0x001e
+#define regDAGB0_RD_VC2_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC3_CNTL 0x001f
+#define regDAGB0_RD_VC3_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC4_CNTL 0x0020
+#define regDAGB0_RD_VC4_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC5_CNTL 0x0021
+#define regDAGB0_RD_VC5_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC6_CNTL 0x0022
+#define regDAGB0_RD_VC6_CNTL_BASE_IDX 0
+#define regDAGB0_RD_VC7_CNTL 0x0023
+#define regDAGB0_RD_VC7_CNTL_BASE_IDX 0
+#define regDAGB0_RD_CNTL_MISC 0x0024
+#define regDAGB0_RD_CNTL_MISC_BASE_IDX 0
+#define regDAGB0_RD_TLB_CREDIT 0x0025
+#define regDAGB0_RD_TLB_CREDIT_BASE_IDX 0
+#define regDAGB0_RD_RDRET_CREDIT_CNTL 0x0026
+#define regDAGB0_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
+#define regDAGB0_RD_RDRET_CREDIT_CNTL2 0x0027
+#define regDAGB0_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB0_RDCLI_ASK_PENDING 0x0028
+#define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_GO_PENDING 0x0029
+#define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_GBLSEND_PENDING 0x002a
+#define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_TLB_PENDING 0x002b
+#define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_OARB_PENDING 0x002c
+#define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB0_RDCLI_OSD_PENDING 0x002d
+#define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI0 0x002e
+#define regDAGB0_WRCLI0_BASE_IDX 0
+#define regDAGB0_WRCLI1 0x002f
+#define regDAGB0_WRCLI1_BASE_IDX 0
+#define regDAGB0_WRCLI2 0x0030
+#define regDAGB0_WRCLI2_BASE_IDX 0
+#define regDAGB0_WRCLI3 0x0031
+#define regDAGB0_WRCLI3_BASE_IDX 0
+#define regDAGB0_WRCLI4 0x0032
+#define regDAGB0_WRCLI4_BASE_IDX 0
+#define regDAGB0_WRCLI5 0x0033
+#define regDAGB0_WRCLI5_BASE_IDX 0
+#define regDAGB0_WRCLI6 0x0034
+#define regDAGB0_WRCLI6_BASE_IDX 0
+#define regDAGB0_WRCLI7 0x0035
+#define regDAGB0_WRCLI7_BASE_IDX 0
+#define regDAGB0_WRCLI8 0x0036
+#define regDAGB0_WRCLI8_BASE_IDX 0
+#define regDAGB0_WRCLI9 0x0037
+#define regDAGB0_WRCLI9_BASE_IDX 0
+#define regDAGB0_WRCLI10 0x0038
+#define regDAGB0_WRCLI10_BASE_IDX 0
+#define regDAGB0_WRCLI11 0x0039
+#define regDAGB0_WRCLI11_BASE_IDX 0
+#define regDAGB0_WRCLI12 0x003a
+#define regDAGB0_WRCLI12_BASE_IDX 0
+#define regDAGB0_WRCLI13 0x003b
+#define regDAGB0_WRCLI13_BASE_IDX 0
+#define regDAGB0_WRCLI14 0x003c
+#define regDAGB0_WRCLI14_BASE_IDX 0
+#define regDAGB0_WRCLI15 0x003d
+#define regDAGB0_WRCLI15_BASE_IDX 0
+#define regDAGB0_WR_CNTL 0x003e
+#define regDAGB0_WR_CNTL_BASE_IDX 0
+#define regDAGB0_WR_GMI_CNTL 0x003f
+#define regDAGB0_WR_GMI_CNTL_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB 0x0040
+#define regDAGB0_WR_ADDR_DAGB_BASE_IDX 0
+#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x0041
+#define regDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0042
+#define regDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB0_WR_CGTT_CLK_CTRL 0x0043
+#define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0044
+#define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0045
+#define regDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0046
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0047
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0048
+#define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0049
+#define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB 0x004a
+#define regDAGB0_WR_DATA_DAGB_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x004b
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004c
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004d
+#define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004e
+#define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB0_WR_VC0_CNTL 0x004f
+#define regDAGB0_WR_VC0_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC1_CNTL 0x0050
+#define regDAGB0_WR_VC1_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC2_CNTL 0x0051
+#define regDAGB0_WR_VC2_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC3_CNTL 0x0052
+#define regDAGB0_WR_VC3_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC4_CNTL 0x0053
+#define regDAGB0_WR_VC4_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC5_CNTL 0x0054
+#define regDAGB0_WR_VC5_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC6_CNTL 0x0055
+#define regDAGB0_WR_VC6_CNTL_BASE_IDX 0
+#define regDAGB0_WR_VC7_CNTL 0x0056
+#define regDAGB0_WR_VC7_CNTL_BASE_IDX 0
+#define regDAGB0_WR_CNTL_MISC 0x0057
+#define regDAGB0_WR_CNTL_MISC_BASE_IDX 0
+#define regDAGB0_WR_TLB_CREDIT 0x0058
+#define regDAGB0_WR_TLB_CREDIT_BASE_IDX 0
+#define regDAGB0_WR_DATA_CREDIT 0x0059
+#define regDAGB0_WR_DATA_CREDIT_BASE_IDX 0
+#define regDAGB0_WR_MISC_CREDIT 0x005a
+#define regDAGB0_WR_MISC_CREDIT_BASE_IDX 0
+#define regDAGB0_WR_OSD_CREDIT_CNTL1 0x005b
+#define regDAGB0_WR_OSD_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB0_WR_OSD_CREDIT_CNTL2 0x005c
+#define regDAGB0_WR_OSD_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x005d
+#define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 0
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x005e
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 0
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x005f
+#define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 0
+#define regDAGB0_WRCLI_ASK_PENDING 0x0060
+#define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_GO_PENDING 0x0061
+#define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_GBLSEND_PENDING 0x0062
+#define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_TLB_PENDING 0x0063
+#define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_OARB_PENDING 0x0064
+#define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_OSD_PENDING 0x0065
+#define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x0066
+#define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 0
+#define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0067
+#define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 0
+#define regDAGB0_DAGB_DLY 0x0068
+#define regDAGB0_DAGB_DLY_BASE_IDX 0
+#define regDAGB0_CNTL_MISC 0x0069
+#define regDAGB0_CNTL_MISC_BASE_IDX 0
+#define regDAGB0_CNTL_MISC2 0x006a
+#define regDAGB0_CNTL_MISC2_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_CNTL 0x006b
+#define regDAGB0_FATAL_ERROR_CNTL_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_CLEAR 0x006c
+#define regDAGB0_FATAL_ERROR_CLEAR_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_STATUS0 0x006d
+#define regDAGB0_FATAL_ERROR_STATUS0_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_STATUS1 0x006e
+#define regDAGB0_FATAL_ERROR_STATUS1_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_STATUS2 0x006f
+#define regDAGB0_FATAL_ERROR_STATUS2_BASE_IDX 0
+#define regDAGB0_FATAL_ERROR_STATUS3 0x0070
+#define regDAGB0_FATAL_ERROR_STATUS3_BASE_IDX 0
+#define regDAGB0_FIFO_EMPTY 0x0071
+#define regDAGB0_FIFO_EMPTY_BASE_IDX 0
+#define regDAGB0_FIFO_FULL 0x0072
+#define regDAGB0_FIFO_FULL_BASE_IDX 0
+#define regDAGB0_WR_CREDITS_FULL 0x0073
+#define regDAGB0_WR_CREDITS_FULL_BASE_IDX 0
+#define regDAGB0_RD_CREDITS_FULL 0x0074
+#define regDAGB0_RD_CREDITS_FULL_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER_LO 0x0075
+#define regDAGB0_PERFCOUNTER_LO_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER_HI 0x0076
+#define regDAGB0_PERFCOUNTER_HI_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER0_CFG 0x0077
+#define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER1_CFG 0x0078
+#define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER2_CFG 0x0079
+#define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 0
+#define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x007a
+#define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0
+#define regDAGB0_L1TLB_REG_RW 0x007b
+#define regDAGB0_L1TLB_REG_RW_BASE_IDX 0
+#define regDAGB0_RESERVE1 0x007c
+#define regDAGB0_RESERVE1_BASE_IDX 0
+#define regDAGB0_RESERVE2 0x007d
+#define regDAGB0_RESERVE2_BASE_IDX 0
+#define regDAGB0_RESERVE3 0x007e
+#define regDAGB0_RESERVE3_BASE_IDX 0
+#define regDAGB0_RESERVE4 0x007f
+#define regDAGB0_RESERVE4_BASE_IDX 0
+
+
+// addressBlock: mmhub_dagb_dagbdec1
+// base address: 0x68200
+#define regDAGB1_RDCLI0 0x0080
+#define regDAGB1_RDCLI0_BASE_IDX 0
+#define regDAGB1_RDCLI1 0x0081
+#define regDAGB1_RDCLI1_BASE_IDX 0
+#define regDAGB1_RDCLI2 0x0082
+#define regDAGB1_RDCLI2_BASE_IDX 0
+#define regDAGB1_RDCLI3 0x0083
+#define regDAGB1_RDCLI3_BASE_IDX 0
+#define regDAGB1_RDCLI4 0x0084
+#define regDAGB1_RDCLI4_BASE_IDX 0
+#define regDAGB1_RDCLI5 0x0085
+#define regDAGB1_RDCLI5_BASE_IDX 0
+#define regDAGB1_RDCLI6 0x0086
+#define regDAGB1_RDCLI6_BASE_IDX 0
+#define regDAGB1_RDCLI7 0x0087
+#define regDAGB1_RDCLI7_BASE_IDX 0
+#define regDAGB1_RDCLI8 0x0088
+#define regDAGB1_RDCLI8_BASE_IDX 0
+#define regDAGB1_RDCLI9 0x0089
+#define regDAGB1_RDCLI9_BASE_IDX 0
+#define regDAGB1_RDCLI10 0x008a
+#define regDAGB1_RDCLI10_BASE_IDX 0
+#define regDAGB1_RDCLI11 0x008b
+#define regDAGB1_RDCLI11_BASE_IDX 0
+#define regDAGB1_RDCLI12 0x008c
+#define regDAGB1_RDCLI12_BASE_IDX 0
+#define regDAGB1_RDCLI13 0x008d
+#define regDAGB1_RDCLI13_BASE_IDX 0
+#define regDAGB1_RDCLI14 0x008e
+#define regDAGB1_RDCLI14_BASE_IDX 0
+#define regDAGB1_RDCLI15 0x008f
+#define regDAGB1_RDCLI15_BASE_IDX 0
+#define regDAGB1_RD_CNTL 0x0090
+#define regDAGB1_RD_CNTL_BASE_IDX 0
+#define regDAGB1_RD_GMI_CNTL 0x0091
+#define regDAGB1_RD_GMI_CNTL_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB 0x0092
+#define regDAGB1_RD_ADDR_DAGB_BASE_IDX 0
+#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093
+#define regDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094
+#define regDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB1_RD_CGTT_CLK_CTRL 0x0095
+#define regDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096
+#define regDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097
+#define regDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098
+#define regDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099
+#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a
+#define regDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b
+#define regDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 0
+#define regDAGB1_RD_VC0_CNTL 0x009c
+#define regDAGB1_RD_VC0_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC1_CNTL 0x009d
+#define regDAGB1_RD_VC1_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC2_CNTL 0x009e
+#define regDAGB1_RD_VC2_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC3_CNTL 0x009f
+#define regDAGB1_RD_VC3_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC4_CNTL 0x00a0
+#define regDAGB1_RD_VC4_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC5_CNTL 0x00a1
+#define regDAGB1_RD_VC5_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC6_CNTL 0x00a2
+#define regDAGB1_RD_VC6_CNTL_BASE_IDX 0
+#define regDAGB1_RD_VC7_CNTL 0x00a3
+#define regDAGB1_RD_VC7_CNTL_BASE_IDX 0
+#define regDAGB1_RD_CNTL_MISC 0x00a4
+#define regDAGB1_RD_CNTL_MISC_BASE_IDX 0
+#define regDAGB1_RD_TLB_CREDIT 0x00a5
+#define regDAGB1_RD_TLB_CREDIT_BASE_IDX 0
+#define regDAGB1_RD_RDRET_CREDIT_CNTL 0x00a6
+#define regDAGB1_RD_RDRET_CREDIT_CNTL_BASE_IDX 0
+#define regDAGB1_RD_RDRET_CREDIT_CNTL2 0x00a7
+#define regDAGB1_RD_RDRET_CREDIT_CNTL2_BASE_IDX 0
+#define regDAGB1_RDCLI_ASK_PENDING 0x00a8
+#define regDAGB1_RDCLI_ASK_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_GO_PENDING 0x00a9
+#define regDAGB1_RDCLI_GO_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_GBLSEND_PENDING 0x00aa
+#define regDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_TLB_PENDING 0x00ab
+#define regDAGB1_RDCLI_TLB_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_OARB_PENDING 0x00ac
+#define regDAGB1_RDCLI_OARB_PENDING_BASE_IDX 0
+#define regDAGB1_RDCLI_OSD_PENDING 0x00ad
+#define regDAGB1_RDCLI_OSD_PENDING_BASE_IDX 0
+#define regDAGB1_WRCLI0 0x00ae
+#define regDAGB1_WRCLI0_BASE_IDX 0
+#define regDAGB1_WRCLI1 0x00af
+#define regDAGB1_WRCLI1_BASE_IDX 0
+#define regDAGB1_WRCLI2 0x00b0
+#define regDAGB1_WRCLI2_BASE_IDX 0
+#define regDAGB1_WRCLI3 0x00b1
+#define regDAGB1_WRCLI3_BASE_IDX 0
+#define regDAGB1_WRCLI4 0x00b2
+#define regDAGB1_WRCLI4_BASE_IDX 0
+#define regDAGB1_WRCLI5 0x00b3
+#define regDAGB1_WRCLI5_BASE_IDX 0
+#define regDAGB1_WRCLI6 0x00b4
+#define regDAGB1_WRCLI6_BASE_IDX 0
+#define regDAGB1_WRCLI7 0x00b5
+#define regDAGB1_WRCLI7_BASE_IDX 0
+#define regDAGB1_WRCLI8 0x00b6
+#define regDAGB1_WRCLI8_BASE_IDX 0
+#define regDAGB1_WRCLI9 0x00b7
+#define regDAGB1_WRCLI9_BASE_IDX 0
+#define regDAGB1_WRCLI10 0x00b8
+#define regDAGB1_WRCLI10_BASE_IDX 0
+#define regDAGB1_WRCLI11 0x00b9
+#define regDAGB1_WRCLI11_BASE_IDX 0
+#define regDAGB1_WRCLI12 0x00ba
+#define regDAGB1_WRCLI12_BASE_IDX 0
+#define regDAGB1_WRCLI13 0x00bb
+#define regDAGB1_WRCLI13_BASE_IDX 0
+#define regDAGB1_WRCLI14 0x00bc
+#define regDAGB1_WRCLI14_BASE_IDX 0
+#define regDAGB1_WRCLI15 0x00bd
+#define regDAGB1_WRCLI15_BASE_IDX 0
+#define regDAGB1_WR_CNTL 0x00be
+#define regDAGB1_WR_CNTL_BASE_IDX 0
+#define regDAGB1_WR_GMI_CNTL 0x00bf
+#define regDAGB1_WR_GMI_CNTL_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB 0x00c0
+#define regDAGB1_WR_ADDR_DAGB_BASE_IDX 0
+#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00c1
+#define regDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 0
+#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c2
+#define regDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 0
+#define regDAGB1_WR_CGTT_CLK_CTRL 0x00c3
+#define regDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c4
+#define regDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c5
+#define regDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c6
+#define regDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c7
+#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c8
+#define regDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 0
+#define regDAGB1_WR_ADDR_DAGB_LAZY_TIMER1