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| author | Hsiao Chien Sung <shawn.sung@mediatek.com> | 2024-06-20 00:38:46 +0800 |
|---|---|---|
| committer | Chun-Kuang Hu <chunkuang.hu@kernel.org> | 2024-06-20 13:57:35 +0000 |
| commit | 6b9946f4550d8dad8bc1af2db97286ca449af786 (patch) | |
| tree | 2a24d78cdf6a4c9c54c95eb494421376e56d120d /drivers/gpu/drm/mediatek/mtk_ethdr.c | |
| parent | 31c0fbf67c8c0bb38d7fb21d404ea3dbd619d99e (diff) | |
| download | linux-6b9946f4550d8dad8bc1af2db97286ca449af786.tar.gz linux-6b9946f4550d8dad8bc1af2db97286ca449af786.tar.bz2 linux-6b9946f4550d8dad8bc1af2db97286ca449af786.zip | |
drm/mediatek: Turn off the layers with zero width or height
We found that IGT (Intel GPU Tool) will try to commit layers with
zero width or height and lead to undefined behaviors in hardware.
Disable the layers in such a situation.
Fixes: 453c3364632a ("drm/mediatek: Add ovl_adaptor support for MT8195")
Fixes: d886c0009bd0 ("drm/mediatek: Add ETHDR support for MT8195")
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.")
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Link: https://patchwork.kernel.org/project/dri-devel/patch/20240620-igt-v3-6-a9d62d2e2c7e@mediatek.com/
Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/mediatek/mtk_ethdr.c')
| -rw-r--r-- | drivers/gpu/drm/mediatek/mtk_ethdr.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c index 5c52e514ae30..bf5826b7e776 100644 --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -160,7 +160,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx, if (idx >= 4) return; - if (!pending->enable) { + if (!pending->enable || !pending->width || !pending->height) { + /* + * instead of disabling layer with MIX_SRC_CON directly + * set the size to 0 to avoid screen shift due to mixer + * mode switch (hardware behavior) + */ mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx)); return; } |