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| author | Aharon Landau <aharonl@nvidia.com> | 2023-01-26 00:28:02 +0200 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2023-01-27 13:04:09 -0400 |
| commit | a2a88b8e22d1b202225d0e40b02ad068afab2ccb (patch) | |
| tree | e8cb6477c2da02293e9b790fab3f884672045079 /drivers/infiniband/hw/mlx5/mr.c | |
| parent | 592627ccbdff0ec6fff00fc761142a76db750dd4 (diff) | |
| download | linux-a2a88b8e22d1b202225d0e40b02ad068afab2ccb.tar.gz linux-a2a88b8e22d1b202225d0e40b02ad068afab2ccb.tar.bz2 linux-a2a88b8e22d1b202225d0e40b02ad068afab2ccb.zip | |
RDMA/mlx5: Don't keep umrable 'page_shift' in cache entries
mkc.log_page_size can be changed using UMR. Therefore, don't treat it as a
cache entry property.
Removing it from struct mlx5_cache_ent.
All cache mkeys will be created with default PAGE_SHIFT, and updated with
the needed page_shift using UMR when passing them to a user.
Link: https://lore.kernel.org/r/20230125222807.6921-2-michaelgur@nvidia.com
Signed-off-by: Aharon Landau <aharonl@nvidia.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/infiniband/hw/mlx5/mr.c')
| -rw-r--r-- | drivers/infiniband/hw/mlx5/mr.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c index 053fe946e45a..356c99d7ec9a 100644 --- a/drivers/infiniband/hw/mlx5/mr.c +++ b/drivers/infiniband/hw/mlx5/mr.c @@ -297,7 +297,7 @@ static void set_cache_mkc(struct mlx5_cache_ent *ent, void *mkc) MLX5_SET(mkc, mkc, translations_octword_size, get_mkc_octo_size(ent->access_mode, ent->ndescs)); - MLX5_SET(mkc, mkc, log_page_size, ent->page); + MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT); } /* Asynchronously schedule new MRs to be populated in the cache. */ @@ -765,7 +765,6 @@ int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev) if (ent->order > mkey_cache_max_order(dev)) continue; - ent->page = PAGE_SHIFT; ent->ndescs = 1 << ent->order; ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT; if ((dev->mdev->profile.mask & MLX5_PROF_MASK_MR_CACHE) && |