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| author | Werner Fischer <devlists@wefi.net> | 2023-12-13 10:45:25 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-02-05 20:12:56 +0000 |
| commit | c95d2144be7739e2cb0aa3b67fa655c78aff8c4f (patch) | |
| tree | ccb695953aff441249678e92914a0586d1be928e /drivers/md/dm-ps-queue-length.c | |
| parent | ec74a45e80289338ef6e76e13f13d841290a0084 (diff) | |
| download | linux-c95d2144be7739e2cb0aa3b67fa655c78aff8c4f.tar.gz linux-c95d2144be7739e2cb0aa3b67fa655c78aff8c4f.tar.bz2 linux-c95d2144be7739e2cb0aa3b67fa655c78aff8c4f.zip | |
watchdog: it87_wdt: Keep WDTCTRL bit 3 unmodified for IT8784/IT8786
[ Upstream commit d12971849d71781c1e4ffd1117d4878ce233d319 ]
WDTCTRL bit 3 sets the mode choice for the clock input of IT8784/IT8786.
Some motherboards require this bit to be set to 1 (= PCICLK mode),
otherwise the watchdog functionality gets broken. The BIOS of those
motherboards sets WDTCTRL bit 3 already to 1.
Instead of setting all bits of WDTCTRL to 0 by writing 0x00 to it, keep
bit 3 of it unchanged for IT8784/IT8786 chips. In this way, bit 3 keeps
the status as set by the BIOS of the motherboard.
Watchdog tests have been successful with this patch with the following
systems:
IT8784: Thomas-Krenn LES plus v2 (YANLING YL-KBRL2 V2)
IT8786: Thomas-Krenn LES plus v3 (YANLING YL-CLU L2)
IT8786: Thomas-Krenn LES network 6L v2 (YANLING YL-CLU6L)
Link: https://lore.kernel.org/all/140b264d-341f-465b-8715-dacfe84b3f71@roeck-us.net/
Signed-off-by: Werner Fischer <devlists@wefi.net>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20231213094525.11849-4-devlists@wefi.net
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/md/dm-ps-queue-length.c')
0 files changed, 0 insertions, 0 deletions