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authorArun Ramadoss <arun.ramadoss@microchip.com>2022-07-24 14:58:21 +0530
committerDavid S. Miller <davem@davemloft.net>2022-07-27 09:39:17 +0100
commit0ab7f6bf1675b5ffbfcd6fffd13be8d98a4d5757 (patch)
tree220d514a3ff8c7c24b23f96f689e92482f4edeea /drivers/net/dsa/microchip/ksz_common.c
parentb19ac41faa3f9602f245d1ab679f7fa96d388320 (diff)
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net: dsa: microchip: ksz9477: use common xmii function
In ksz9477.c file, configuring the xmii register is performed based on the flag NEW_XMII. The flag is reset for ksz9893 switch and set for other switch. This patch uses the ksz common xmii set and get function. The bit values are configured based on the chip id. Signed-off-by: Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa/microchip/ksz_common.c')
-rw-r--r--drivers/net/dsa/microchip/ksz_common.c38
1 files changed, 37 insertions, 1 deletions
diff --git a/drivers/net/dsa/microchip/ksz_common.c b/drivers/net/dsa/microchip/ksz_common.c
index 237dec7c6e3c..86a2a40cacb4 100644
--- a/drivers/net/dsa/microchip/ksz_common.c
+++ b/drivers/net/dsa/microchip/ksz_common.c
@@ -1436,6 +1436,9 @@ void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
data8 |= bitval[P_RGMII_SEL];
+ /* On KSZ9893, disable RGMII in-band status support */
+ if (dev->features & IS_9893)
+ data8 &= ~P_MII_MAC_MODE;
break;
default:
dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
@@ -1453,6 +1456,39 @@ void ksz_set_xmii(struct ksz_device *dev, int port, phy_interface_t interface)
ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
}
+phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
+{
+ const u8 *bitval = dev->info->xmii_ctrl1;
+ const u16 *regs = dev->info->regs;
+ phy_interface_t interface;
+ u8 data8;
+ u8 val;
+
+ ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
+
+ val = FIELD_GET(P_MII_SEL_M, data8);
+
+ if (val == bitval[P_MII_SEL]) {
+ if (gbit)
+ interface = PHY_INTERFACE_MODE_GMII;
+ else
+ interface = PHY_INTERFACE_MODE_MII;
+ } else if (val == bitval[P_RMII_SEL]) {
+ interface = PHY_INTERFACE_MODE_RGMII;
+ } else {
+ interface = PHY_INTERFACE_MODE_RGMII;
+ if (data8 & P_RGMII_ID_EG_ENABLE)
+ interface = PHY_INTERFACE_MODE_RGMII_TXID;
+ if (data8 & P_RGMII_ID_IG_ENABLE) {
+ interface = PHY_INTERFACE_MODE_RGMII_RXID;
+ if (data8 & P_RGMII_ID_EG_ENABLE)
+ interface = PHY_INTERFACE_MODE_RGMII_ID;
+ }
+ }
+
+ return interface;
+}
+
static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
unsigned int mode,
const struct phylink_link_state *state)
@@ -1484,7 +1520,7 @@ bool ksz_get_gbit(struct ksz_device *dev, int port)
return gbit;
}
-void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
+static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
{
const u8 *bitval = dev->info->xmii_ctrl1;
const u16 *regs = dev->info->regs;