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| author | Sreekanth Reddy <sreekanth.reddy@broadcom.com> | 2021-12-20 19:41:40 +0530 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2021-12-23 00:04:22 -0500 |
| commit | 17d6b9cf89cfdb5a52298bb4abe7f1621f92ba93 (patch) | |
| tree | 9138de21be1e5b17e07568c6253715c226fd0d2a /drivers/scsi/mpi3mr/mpi3mr.h | |
| parent | ec5ebd2c14a9123c0a8e2ae29202adf0ac242565 (diff) | |
| download | linux-17d6b9cf89cfdb5a52298bb4abe7f1621f92ba93.tar.gz linux-17d6b9cf89cfdb5a52298bb4abe7f1621f92ba93.tar.bz2 linux-17d6b9cf89cfdb5a52298bb4abe7f1621f92ba93.zip | |
scsi: mpi3mr: Add support for PCIe Managed Switch SES device
The SAS4 Controller firmware exposes the SES devices in Managed PCIe Switch
as a PCIe Device Type SCSI Device
(MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE).
Driver is enhanced to handle this device type by:
- Exposing the device to the upper layers and
- Not updating any hardware sectors & virtual boundary settings as these
settings are needed only for NVMe devices.
Link: https://lore.kernel.org/r/20211220141159.16117-7-sreekanth.reddy@broadcom.com
Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/scsi/mpi3mr/mpi3mr.h')
| -rw-r--r-- | drivers/scsi/mpi3mr/mpi3mr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/scsi/mpi3mr/mpi3mr.h b/drivers/scsi/mpi3mr/mpi3mr.h index cdbd1cb44d97..fe3cfd5c2823 100644 --- a/drivers/scsi/mpi3mr/mpi3mr.h +++ b/drivers/scsi/mpi3mr/mpi3mr.h @@ -147,6 +147,7 @@ extern int prot_mask; MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC #define MPI3MR_DEFAULT_MDTS (128 * 1024) +#define MPI3MR_DEFAULT_PGSZEXP (12) /* Command retry count definitions */ #define MPI3MR_DEV_RMHS_RETRY_COUNT 3 @@ -389,6 +390,7 @@ struct tgt_dev_sas_sata { * @pgsz: Device page size * @abort_to: Timeout for abort TM * @reset_to: Timeout for Target/LUN reset TM + * @dev_info: Device information bits */ struct tgt_dev_pcie { u32 mdts; @@ -396,6 +398,7 @@ struct tgt_dev_pcie { u8 pgsz; u8 abort_to; u8 reset_to; + u16 dev_info; }; /** |