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| author | Laura Nao <laura.nao@collabora.com> | 2025-11-25 17:16:56 +0100 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2026-01-20 20:41:49 +0100 |
| commit | b5468be97fcc8c78e6904f718a249231b9e54896 (patch) | |
| tree | 615f9818aca45f8064c6bad0ca04233487623604 /drivers/thermal | |
| parent | 6cd9a3b23a2d534fa582b78fd988fef7ed837ee9 (diff) | |
| download | linux-b5468be97fcc8c78e6904f718a249231b9e54896.tar.gz linux-b5468be97fcc8c78e6904f718a249231b9e54896.tar.bz2 linux-b5468be97fcc8c78e6904f718a249231b9e54896.zip | |
thermal/drivers/mediatek/lvts: Support MSR offset for 16-bit calibration data
On MT8196/MT6991, per-sensor calibration data read from eFuses is
16-bit. When the LVTS controller operates in 16-bit mode, a fixed offset
must be added to MSR values during post-processing to obtain correct
temperature readings. Introduce a new msr_offset field in lvts_data,
program the respective register and apply the offset to the calibration
data read from eFuses.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Link: https://patch.msgid.link/20251125-mt8196-lvts-v4-v5-6-6db7eb903fb7@collabora.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'drivers/thermal')
| -rw-r--r-- | drivers/thermal/mediatek/lvts_thermal.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index b53d6a4a7474..93eb62cae512 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -44,6 +44,7 @@ #define LVTS_EDATA01(__base) (__base + 0x0058) #define LVTS_EDATA02(__base) (__base + 0x005C) #define LVTS_EDATA03(__base) (__base + 0x0060) +#define LVTS_MSROFT(__base) (__base + 0x006C) #define LVTS_ATP0(__base) (__base + 0x0070) #define LVTS_ATP1(__base) (__base + 0x0074) #define LVTS_ATP2(__base) (__base + 0x0078) @@ -151,6 +152,7 @@ struct lvts_data { int temp_offset; int gt_calib_bit_offset; unsigned int def_calibration; + u16 msr_offset; }; struct lvts_sensor { @@ -219,6 +221,7 @@ static const struct debugfs_reg32 lvts_regs[] = { LVTS_DEBUG_FS_REGS(LVTS_EDATA01), LVTS_DEBUG_FS_REGS(LVTS_EDATA02), LVTS_DEBUG_FS_REGS(LVTS_EDATA03), + LVTS_DEBUG_FS_REGS(LVTS_MSROFT), LVTS_DEBUG_FS_REGS(LVTS_ATP0), LVTS_DEBUG_FS_REGS(LVTS_ATP1), LVTS_DEBUG_FS_REGS(LVTS_ATP2), @@ -811,6 +814,8 @@ static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl if (gt) { lvts_ctrl->calibration[i] = calib; + if (lvts_ctrl->lvts_data->msr_offset) + lvts_ctrl->calibration[i] += lvts_ctrl->lvts_data->msr_offset; } else if (lvts_ctrl->lvts_data->def_calibration) { lvts_ctrl->calibration[i] = lvts_ctrl->lvts_data->def_calibration; } else { @@ -1118,6 +1123,17 @@ static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) for (i = 0; i < LVTS_SENSOR_MAX; i++) writel(lvts_ctrl->calibration[i], lvts_edata[i]); + /* LVTS_MSROFT : Constant offset applied to MSR values + * for post-processing + * + * Bits: + * + * 20-0 : Constant data added to MSR values + */ + if (lvts_ctrl->lvts_data->msr_offset) + writel(lvts_ctrl->lvts_data->msr_offset, + LVTS_MSROFT(lvts_ctrl->base)); + return 0; } |