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authorMaxime Ripard <maxime@cerno.tech>2020-08-18 14:14:25 +0200
committerMaxime Ripard <maxime@cerno.tech>2020-08-18 14:14:25 +0200
commitd85ddd1318e66c0c2665dbfcbc21a8b66c9152aa (patch)
treee49e401abd2468b398d4bc84c7e05c2c2c3b0966 /include/dt-bindings/mux/mux-j721e-wiz.h
parent652bcaec7da0f06f00be578c200e1c57099449d2 (diff)
parent9123e3a74ec7b934a4a099e98af6a61c2f80bbf5 (diff)
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Merge v5.9-rc1 into drm-misc-next
Sam needs 5.9-rc1 to have dev_err_probe in to merge some patches. Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'include/dt-bindings/mux/mux-j721e-wiz.h')
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diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
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+++ b/include/dt-bindings/mux/mux-j721e-wiz.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for J721E WIZ.
+ */
+
+#ifndef _DT_BINDINGS_J721E_WIZ
+#define _DT_BINDINGS_J721E_WIZ
+
+#define SERDES0_LANE0_QSGMII_LANE1 0x0
+#define SERDES0_LANE0_PCIE0_LANE0 0x1
+#define SERDES0_LANE0_USB3_0_SWAP 0x2
+
+#define SERDES0_LANE1_QSGMII_LANE2 0x0
+#define SERDES0_LANE1_PCIE0_LANE1 0x1
+#define SERDES0_LANE1_USB3_0 0x2
+
+#define SERDES1_LANE0_QSGMII_LANE3 0x0
+#define SERDES1_LANE0_PCIE1_LANE0 0x1
+#define SERDES1_LANE0_USB3_1_SWAP 0x2
+#define SERDES1_LANE0_SGMII_LANE0 0x3
+
+#define SERDES1_LANE1_QSGMII_LANE4 0x0
+#define SERDES1_LANE1_PCIE1_LANE1 0x1
+#define SERDES1_LANE1_USB3_1 0x2
+#define SERDES1_LANE1_SGMII_LANE1 0x3
+
+#define SERDES2_LANE0_PCIE2_LANE0 0x1
+#define SERDES2_LANE0_SGMII_LANE0 0x3
+#define SERDES2_LANE0_USB3_1_SWAP 0x2
+
+#define SERDES2_LANE1_PCIE2_LANE1 0x1
+#define SERDES2_LANE1_USB3_1 0x2
+#define SERDES2_LANE1_SGMII_LANE1 0x3
+
+#define SERDES3_LANE0_PCIE3_LANE0 0x1
+#define SERDES3_LANE0_USB3_0_SWAP 0x2
+
+#define SERDES3_LANE1_PCIE3_LANE1 0x1
+#define SERDES3_LANE1_USB3_0 0x2
+
+#define SERDES4_LANE0_EDP_LANE0 0x0
+#define SERDES4_LANE0_QSGMII_LANE5 0x2
+
+#define SERDES4_LANE1_EDP_LANE1 0x0
+#define SERDES4_LANE1_QSGMII_LANE6 0x2
+
+#define SERDES4_LANE2_EDP_LANE2 0x0
+#define SERDES4_LANE2_QSGMII_LANE7 0x2
+
+#define SERDES4_LANE3_EDP_LANE3 0x0
+#define SERDES4_LANE3_QSGMII_LANE8 0x2
+
+#endif /* _DT_BINDINGS_J721E_WIZ */