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| author | Ben Ben-Ishay <benishay@nvidia.com> | 2020-07-14 14:40:32 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2025-08-28 16:24:02 +0200 |
| commit | 88576404084d1b56f1367b074d138d342a8dd9f5 (patch) | |
| tree | 9cdac95355c43b2fd3cc683b68c4a9a557a498a3 /include/linux | |
| parent | 9737501f26b623a3a2564d1ee856fddbbd3457a4 (diff) | |
| download | linux-88576404084d1b56f1367b074d138d342a8dd9f5.tar.gz linux-88576404084d1b56f1367b074d138d342a8dd9f5.tar.bz2 linux-88576404084d1b56f1367b074d138d342a8dd9f5.zip | |
net/mlx5e: Add support to klm_umr_wqe
[ Upstream commit d7b896acbdcb3ef5dab1fd2f33ba5a8da6ba1dda ]
This commit adds the needed definitions for using the klm_umr_wqe.
UMR stands for user-mode memory registration, is a mechanism to alter
address translation properties of MKEY by posting WorkQueueElement
aka WQE on send queue.
MKEY stands for memory key, MKEY are used to describe a region in memory that
can be later used by HW.
KLM stands for {Key, Length, MemVa}, KLM_MKEY is indirect MKEY that enables
to map multiple memory spaces with different sizes in unified MKEY.
klm_umr_wqe is a UMR that use to update a KLM_MKEY.
SHAMPO feature uses KLM_MKEY for memory registration of his header buffer.
Signed-off-by: Ben Ben-Ishay <benishay@nvidia.com>
Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
Stable-dep-of: 531d0d32de3e ("net/mlx5: Correctly set gso_size when LRO is used")
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/mlx5/device.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 476d8fd5a7e5..afc7e2d81b6d 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -290,6 +290,7 @@ enum { MLX5_UMR_INLINE = (1 << 7), }; +#define MLX5_UMR_KLM_ALIGNMENT 4 #define MLX5_UMR_MTT_ALIGNMENT 0x40 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT |