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| author | Tom Lendacky <thomas.lendacky@amd.com> | 2020-01-09 17:42:16 -0600 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-03-05 16:42:21 +0100 |
| commit | a4e761c9f63ae12c5e2fc586b77082fd07e54212 (patch) | |
| tree | 99a3a86f94b1edeacbcc6a4c25ac8d4d8b9b89b8 /virt | |
| parent | 6390f6ba90d0396e5c207e075a7ab7ba823dc37f (diff) | |
| download | linux-a4e761c9f63ae12c5e2fc586b77082fd07e54212.tar.gz linux-a4e761c9f63ae12c5e2fc586b77082fd07e54212.tar.bz2 linux-a4e761c9f63ae12c5e2fc586b77082fd07e54212.zip | |
KVM: SVM: Override default MMIO mask if memory encryption is enabled
commit 52918ed5fcf05d97d257f4131e19479da18f5d16 upstream.
The KVM MMIO support uses bit 51 as the reserved bit to cause nested page
faults when a guest performs MMIO. The AMD memory encryption support uses
a CPUID function to define the encryption bit position. Given this, it is
possible that these bits can conflict.
Use svm_hardware_setup() to override the MMIO mask if memory encryption
support is enabled. Various checks are performed to ensure that the mask
is properly defined and rsvd_bits() is used to generate the new mask (as
was done prior to the change that necessitated this patch).
Fixes: 28a1f3ac1d0c ("kvm: x86: Set highest physical address bits in non-present/reserved SPTEs")
Suggested-by: Sean Christopherson <sean.j.christopherson@intel.com>
Reviewed-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'virt')
0 files changed, 0 insertions, 0 deletions
