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-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml3
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml8
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml3
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml3
-rw-r--r--Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml1
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml40
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml5
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml16
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml5
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml3
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml85
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml7
-rw-r--r--Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml71
-rw-r--r--drivers/clk/clk-devres.c91
-rw-r--r--drivers/clk/clk-fixed-factor.c56
-rw-r--r--drivers/clk/clk.c48
-rw-r--r--drivers/clk/imx/clk-fracn-gppll.c36
-rw-r--r--drivers/clk/imx/clk-imx93.c6
-rw-r--r--drivers/clk/mediatek/clk-mt2701-eth.c10
-rw-r--r--drivers/clk/mediatek/clk-mt2701-g3d.c10
-rw-r--r--drivers/clk/mediatek/clk-mt2701-hif.c10
-rw-r--r--drivers/clk/mediatek/clk-mt2701.c22
-rw-r--r--drivers/clk/mediatek/clk-mt2712.c22
-rw-r--r--drivers/clk/mediatek/clk-mt7622-eth.c10
-rw-r--r--drivers/clk/mediatek/clk-mt7622-hif.c12
-rw-r--r--drivers/clk/mediatek/clk-mt7622.c22
-rw-r--r--drivers/clk/mediatek/clk-mt7629-eth.c10
-rw-r--r--drivers/clk/mediatek/clk-mt7629-hif.c12
-rw-r--r--drivers/clk/mediatek/clk-mt8135.c22
-rw-r--r--drivers/clk/mediatek/clk-mt8173.c22
-rw-r--r--drivers/clk/mediatek/clk-mt8183.c18
-rw-r--r--drivers/clk/mediatek/clk-mt8186-infra_ao.c23
-rw-r--r--drivers/clk/mediatek/clk-mt8192-msdc.c21
-rw-r--r--drivers/clk/mediatek/clk-mt8192.c29
-rw-r--r--drivers/clk/mediatek/clk-mt8195-infra_ao.c24
-rw-r--r--drivers/clk/mediatek/clk-mtk.c7
-rw-r--r--drivers/clk/mediatek/clk-mtk.h9
-rw-r--r--drivers/clk/mediatek/reset.c198
-rw-r--r--drivers/clk/mediatek/reset.h82
-rw-r--r--drivers/clk/meson/axg-audio.c36
-rw-r--r--drivers/clk/qcom/Kconfig22
-rw-r--r--drivers/clk/qcom/Makefile3
-rw-r--r--drivers/clk/qcom/camcc-sdm845.c4
-rw-r--r--drivers/clk/qcom/camcc-sm8250.c16
-rw-r--r--drivers/clk/qcom/camcc-sm8450.c2856
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.c144
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.h11
-rw-r--r--drivers/clk/qcom/clk-hfpll.c15
-rw-r--r--drivers/clk/qcom/clk-krait.c23
-rw-r--r--drivers/clk/qcom/clk-krait.h1
-rw-r--r--drivers/clk/qcom/clk-rcg2.c16
-rw-r--r--drivers/clk/qcom/clk-regmap-phy-mux.c62
-rw-r--r--drivers/clk/qcom/clk-regmap-phy-mux.h33
-rw-r--r--drivers/clk/qcom/clk-rpm.c24
-rw-r--r--drivers/clk/qcom/clk-rpmh.c5
-rw-r--r--drivers/clk/qcom/dispcc-sm8250.c64
-rw-r--r--drivers/clk/qcom/gcc-ipq8074.c104
-rw-r--r--drivers/clk/qcom/gcc-msm8916.c35
-rw-r--r--drivers/clk/qcom/gcc-msm8939.c47
-rw-r--r--drivers/clk/qcom/gcc-msm8960.c6
-rw-r--r--drivers/clk/qcom/gcc-msm8994.c8
-rw-r--r--drivers/clk/qcom/gcc-sc7280.c49
-rw-r--r--drivers/clk/qcom/gcc-sc8280xp.c142
-rw-r--r--drivers/clk/qcom/gcc-sm6350.c2
-rw-r--r--drivers/clk/qcom/gcc-sm8450.c49
-rw-r--r--drivers/clk/qcom/gdsc.c36
-rw-r--r--drivers/clk/qcom/gdsc.h4
-rw-r--r--drivers/clk/qcom/gpucc-sm8350.c637
-rw-r--r--drivers/clk/qcom/krait-cc.c8
-rw-r--r--drivers/clk/qcom/mmcc-msm8996.c1052
-rw-r--r--drivers/clk/qcom/videocc-sm8250.c4
-rw-r--r--drivers/clk/renesas/clk-r8a73a4.c22
-rw-r--r--drivers/clk/renesas/clk-r8a7740.c20
-rw-r--r--drivers/clk/renesas/clk-r8a7778.c31
-rw-r--r--drivers/clk/renesas/clk-r8a7779.c27
-rw-r--r--drivers/clk/renesas/clk-rz.c33
-rw-r--r--drivers/clk/renesas/clk-sh73a0.c26
-rw-r--r--drivers/clk/renesas/r8a779f0-cpg-mssr.c10
-rw-r--r--drivers/clk/renesas/r9a06g032-clocks.c32
-rw-r--r--drivers/clk/renesas/r9a07g043-cpg.c32
-rw-r--r--drivers/clk/renesas/r9a07g044-cpg.c17
-rw-r--r--drivers/clk/renesas/r9a09g011-cpg.c5
-rw-r--r--drivers/clk/renesas/rcar-gen4-cpg.c2
-rw-r--r--drivers/clk/renesas/rzg2l-cpg.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c15
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-h6.c16
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-de2.c77
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c113
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-r.c40
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-v3s.c80
-rw-r--r--drivers/clk/sunxi/Kconfig4
-rw-r--r--drivers/clk/ti/clk-44xx.c210
-rw-r--r--drivers/clk/ti/clk-54xx.c160
-rw-r--r--drivers/clk/ti/clkctrl.c4
-rw-r--r--include/dt-bindings/clock/qcom,gcc-ipq8074.h1
-rw-r--r--include/dt-bindings/clock/qcom,gcc-msm8939.h1
-rw-r--r--include/dt-bindings/clock/r9a07g043-cpg.h20
-rw-r--r--include/dt-bindings/clock/sprd,ums512-clk.h397
-rw-r--r--include/dt-bindings/reset/mt8186-resets.h5
-rw-r--r--include/dt-bindings/reset/mt8192-resets.h8
-rw-r--r--include/dt-bindings/reset/mt8195-resets.h6
-rw-r--r--include/linux/clk-provider.h36
-rw-r--r--include/linux/clk.h134
103 files changed, 6696 insertions, 1490 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
index 0886e2e335bb..661047d26e11 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
@@ -39,6 +39,9 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
index c8c67c033f8c..b57cc2e69efb 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
@@ -24,7 +24,6 @@ properties:
- mediatek,mt8192-imp_iic_wrap_w
- mediatek,mt8192-imp_iic_wrap_n
- mediatek,mt8192-msdc_top
- - mediatek,mt8192-msdc
- mediatek,mt8192-mfgcfg
- mediatek,mt8192-imgsys
- mediatek,mt8192-imgsys2
@@ -108,13 +107,6 @@ examples:
};
- |
- msdc: clock-controller@11f60000 {
- compatible = "mediatek,mt8192-msdc";
- reg = <0x11f60000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
mfgcfg: clock-controller@13fbf000 {
compatible = "mediatek,mt8192-mfgcfg";
reg = <0x13fbf000 0x1000>;
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
index 5705bcf1fe47..27f79175c678 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
@@ -29,6 +29,9 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
index 57a1503d95fe..95b6bdf99936 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
@@ -37,6 +37,9 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
index f415845b38dd..0b02378a3a0c 100644
--- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
@@ -13,7 +13,6 @@ maintainers:
properties:
compatible:
enum:
- - allwinner,sun4i-a10-pll3-2x-clk
- fixed-factor-clock
"#clock-cells":
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
index 9fafcb080069..3cf404c9325a 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
+title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960
allOf:
- $ref: qcom,gcc.yaml#
@@ -23,11 +23,25 @@ description: |
properties:
compatible:
- const: qcom,gcc-apq8064
+ oneOf:
+ - items:
+ - enum:
+ - qcom,gcc-apq8064
+ - qcom,gcc-msm8960
+ - const: syscon
+ - enum:
+ - qcom,gcc-apq8064
+ - qcom,gcc-msm8960
+ deprecated: true
+
+ thermal-sensor:
+ description: child tsens device
+ $ref: /schemas/thermal/qcom-tsens.yaml#
nvmem-cells:
minItems: 1
maxItems: 2
+ deprecated: true
description:
Qualcomm TSENS (thermal sensor device) on some devices can
be part of GCC and hence the TSENS properties can also be part
@@ -37,31 +51,39 @@ properties:
nvmem-cell-names:
minItems: 1
+ deprecated: true
items:
- const: calib
- const: calib_backup
'#thermal-sensor-cells':
const: 1
+ deprecated: true
required:
- compatible
- - nvmem-cells
- - nvmem-cell-names
- - '#thermal-sensor-cells'
unevaluatedProperties: false
examples:
- |
clock-controller@900000 {
- compatible = "qcom,gcc-apq8064";
+ compatible = "qcom,gcc-apq8064", "syscon";
reg = <0x00900000 0x4000>;
- nvmem-cells = <&tsens_calib>, <&tsens_backup>;
- nvmem-cell-names = "calib", "calib_backup";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
- #thermal-sensor-cells = <1>;
+
+ thermal-sensor {
+ compatible = "qcom,msm8960-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <0 178 4>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
};
...
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
index 98572b4a9b60..21470f52ce36 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
@@ -24,6 +24,9 @@ properties:
'#clock-cells':
const: 1
+ '#power-domain-cells':
+ const: 1
+
'#reset-cells':
const: 1
@@ -38,6 +41,7 @@ required:
- compatible
- reg
- '#clock-cells'
+ -