diff options
82 files changed, 2028 insertions, 1867 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci index 77ad9ec3c801..25c9c39770c6 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci +++ b/Documentation/ABI/testing/sysfs-bus-pci @@ -366,3 +366,12 @@ Contact: Heiner Kallweit <hkallweit1@gmail.com> Description: If ASPM is supported for an endpoint, these files can be used to disable or enable the individual power management states. Write y/1/on to enable, n/0/off to disable. + +What: /sys/bus/pci/devices/.../power_state +Date: November 2020 +Contact: Linux PCI developers <linux-pci@vger.kernel.org> +Description: + This file contains the current PCI power state of the device. + The value comes from the PCI kernel device state and can be one + of: "unknown", "error", "D0", D1", "D2", "D3hot", "D3cold". + The file is read only. diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml index 60b8baf299bb..21e8a8849076 100644 --- a/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml @@ -20,7 +20,4 @@ properties: maximum: 32 default: 32 -required: - - cdns,max-outbound-regions - additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 02bc81bb8b2d..3b55310390a0 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -13,6 +13,7 @@ - "qcom,pcie-ipq8074" for ipq8074 - "qcom,pcie-qcs404" for qcs404 - "qcom,pcie-sdm845" for sdm845 + - "qcom,pcie-sm8250" for sm8250 - reg: Usage: required @@ -27,6 +28,7 @@ - "dbi" DesignWare PCIe registers - "elbi" External local bus interface registers - "config" PCIe configuration space + - "atu" ATU address space (optional) - device_type: Usage: required @@ -131,7 +133,7 @@ - "slave_bus" AXI Slave clock -clock-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: <stringlist> Definition: Should contain the following entries - "aux" Auxiliary clock @@ -206,7 +208,7 @@ - "ahb" AHB reset - reset-names: - Usage: required for sdm845 + Usage: required for sdm845 and sm8250 Value type: <stringlist> Definition: Should contain the following entries - "pci" PCIe core reset diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml new file mode 100644 index 000000000000..4a2bcc0158e2 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car PCIe Host + +maintainers: + - Marek Vasut <marek.vasut+renesas@gmail.com> + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> + +allOf: + - $ref: pci-bus.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,pcie-r8a7742 # RZ/G1H + - renesas,pcie-r8a7743 # RZ/G1M + - renesas,pcie-r8a7744 # RZ/G1N + - renesas,pcie-r8a7790 # R-Car H2 + - renesas,pcie-r8a7791 # R-Car M2-W + - renesas,pcie-r8a7793 # R-Car M2-N + - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1 + - items: + - enum: + - renesas,pcie-r8a774a1 # RZ/G2M + - renesas,pcie-r8a774b1 # RZ/G2N + - renesas,pcie-r8a774c0 # RZ/G2E + - renesas,pcie-r8a774e1 # RZ/G2H + - renesas,pcie-r8a7795 # R-Car H3 + - renesas,pcie-r8a7796 # R-Car M3-W + - renesas,pcie-r8a77961 # R-Car M3-W+ + - renesas,pcie-r8a77965 # R-Car M3-N + - renesas,pcie-r8a77980 # R-Car V3H + - renesas,pcie-r8a77990 # R-Car E3 + - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2 + + reg: + maxItems: 1 + + interrupts: + minItems: 3 + maxItems: 3 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pcie + - const: pcie_bus + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: pcie + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7791-cpg-mssr.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/r8a7791-sysc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@fe000000 { + compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>, + <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/rcar-pci.txt b/Documentation/devicetree/bindings/pci/rcar-pci.txt deleted file mode 100644 index 14d307deff06..000000000000 --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt +++ /dev/null @@ -1,72 +0,0 @@ -* Renesas R-Car PCIe interface - -Required properties: -compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC; - "renesas,pcie-r8a7743" for the R8A7743 SoC; - "renesas,pcie-r8a7744" for the R8A7744 SoC; - "renesas,pcie-r8a774a1" for the R8A774A1 SoC; - "renesas,pcie-r8a774b1" for the R8A774B1 SoC; - "renesas,pcie-r8a774c0" for the R8A774C0 SoC; - "renesas,pcie-r8a7779" for the R8A7779 SoC; - "renesas,pcie-r8a7790" for the R8A7790 SoC; - "renesas,pcie-r8a7791" for the R8A7791 SoC; - "renesas,pcie-r8a7793" for the R8A7793 SoC; - "renesas,pcie-r8a7795" for the R8A7795 SoC; - "renesas,pcie-r8a7796" for the R8A77960 SoC; - "renesas,pcie-r8a77961" for the R8A77961 SoC; - "renesas,pcie-r8a77980" for the R8A77980 SoC; - "renesas,pcie-r8a77990" for the R8A77990 SoC; - "renesas,pcie-rcar-gen2" for a generic R-Car Gen2 or - RZ/G1 compatible device. - "renesas,pcie-rcar-gen3" for a generic R-Car Gen3 or - RZ/G2 compatible device. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: base address and length of the PCIe controller registers. -- #address-cells: set to <3> -- #size-cells: set to <2> -- bus-range: PCI bus numbers covered -- device_type: set to "pci" -- ranges: ranges for the PCI memory and I/O regions. -- dma-ranges: ranges for the inbound memory regions. -- interrupts: two interrupt sources for MSI interrupts, followed by interrupt - source for hardware related interrupts (e.g. link speed change). -- #interrupt-cells: set to <1> -- interrupt-map-mask and interrupt-map: standard PCI properties - to define the mapping of the PCIe interface to interrupt numbers. -- clocks: from common clock binding: clock specifiers for the PCIe controller - and PCIe bus clocks. -- clock-names: from common clock binding: should be "pcie" and "pcie_bus". - -Optional properties: -- phys: from common PHY binding: PHY phandle and specifier (only make sense - for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks). -- phy-names: from common PHY binding: should be "pcie". - -Example: - -SoC-specific DT Entry: - - pcie: pcie@fe000000 { - compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2"; - reg = <0 0xfe000000 0 0x80000>; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - device_type = "pci"; - ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 - 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 - 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 - 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; - dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000 - 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>; - interrupts = <0 116 4>, <0 117 4>, <0 118 4>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0>; - interrupt-map = <0 0 0 0 &gic 0 116 4>; - clocks = <&mstp3_clks R8A7791_CLK_PCIE>, <&pcie_bus_clk>; - clock-names = "pcie", "pcie_bus"; - }; diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml new file mode 100644 index 000000000000..1810bf722350 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SoC series PCIe Host Controller Device Tree Bindings + +maintainers: + - Marek Szyprowski <m.szyprowski@samsung.com> + - Jaehoon Chung <jh80.chung@samsung.com> + +description: |+ + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + designware-pcie.txt. + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: samsung,exynos5433-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: External Local Bus interface (ELBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: elbi + - const: config + + interrupts: + maxItems: 1 + + clocks: + items: + - description: PCIe bridge clock + - description: PCIe bus clock + + clock-names: + items: + - const: pcie + - const: pcie_bus + + phys: + maxItems: 1 + + vdd10-supply: + description: + Phandle to a regulator that provides 1.0V power to the PCIe block. + + vdd18-supply: + description: + Phandle to a regulator that provides 1.8V power to the PCIe block. + + num-lanes: + const: 1 + + num-viewport: + const: 3 + +required: + - reg + - reg-names + - interrupts + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - ranges + - bus-range + - device_type + - num-lanes + - num-viewport + - clocks + - clock-names + - phys + - vdd10-supply + - vdd18-supply + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/exynos5433.h> + + pcie: pcie@15700000 { + compatible = "samsung,exynos5433-pcie"; + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>; + reg-names = "dbi", "elbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; < |