diff options
| -rw-r--r-- | drivers/clk/qcom/gcc-ipq8074.c | 1781 |
1 files changed, 813 insertions, 968 deletions
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 42d185fe19c8..abd5564ea853 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -49,349 +49,6 @@ enum { P_UNIPHY2_TX, }; -static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = { - "xo", - "gpll0", - "gpll0_out_main_div2", -}; - -static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL0_DIV2, 4 }, -}; - -static const struct parent_map gcc_xo_gpll0_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, -}; - -static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { - "xo", - "gpll0", - "gpll2", - "gpll0_out_main_div2", -}; - -static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL2, 2 }, - { P_GPLL0_DIV2, 4 }, -}; - -static const char * const gcc_xo_gpll0_sleep_clk[] = { - "xo", - "gpll0", - "sleep_clk", -}; - -static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = { - { P_XO, 0 }, - { P_GPLL0, 2 }, - { P_SLEEP_CLK, 6 }, -}; - -static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = { - "xo", - "gpll6", - "gpll0", - "gpll0_out_main_div2", -}; - -static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = { - { P_XO, 0 }, - { P_GPLL6, 1 }, - { P_GPLL0, 3 }, - { P_GPLL0_DIV2, 4 }, -}; - -static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = { - "xo", - "gpll0_out_main_div2", - "gpll0", -}; - -static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { - { P_XO, 0 }, - { P_GPLL0_DIV2, 2 }, - { P_GPLL0, 1 }, -}; - -static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = { - "usb3phy_0_cc_pipe_clk", - "xo", -}; - -static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { - { P_USB3PHY_0_PIPE, 0 }, - { P_XO, 2 }, -}; - -static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = { - "usb3phy_1_cc_pipe_clk", - "xo", -}; - -static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = { - { P_USB3PHY_1_PIPE, 0 }, - { P_XO, 2 }, -}; - -static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = { - "pcie20_phy0_pipe_clk", - "xo", -}; - -static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = { - { P_PCIE20_PHY0_PIPE, 0 }, - { P_XO, 2 }, -}; - -static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = { - "pcie20_phy1_pipe_clk", - "xo", -}; - -static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = { - { P_PCIE20_PHY1_PIPE, 0 }, - { P_XO, 2 }, -}; - -static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = { - "xo", - "gpll0", - "gpll6", - "gpll0_out_main_div2", -}; - -static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL6, 2 }, - { P_GPLL0_DIV2, 4 }, -}; - -static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = { - "xo", - "gpll0", - "gpll6", - "gpll0_out_main_div2", -}; - -static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL6, 2 }, - { P_GPLL0_DIV2, 3 }, -}; - -static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = { - "xo", - "bias_pll_nss_noc_clk", - "gpll0", - "gpll2", -}; - -static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = { - { P_XO, 0 }, - { P_BIAS_PLL_NSS_NOC, 1 }, - { P_GPLL0, 2 }, - { P_GPLL2, 3 }, -}; - -static const char * const gcc_xo_nss_crypto_pll_gpll0[] = { - "xo", - "nss_crypto_pll", - "gpll0", -}; - -static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = { - { P_XO, 0 }, - { P_NSS_CRYPTO_PLL, 1 }, - { P_GPLL0, 2 }, -}; - -static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = { - "xo", - "ubi32_pll", - "gpll0", - "gpll2", - "gpll4", - "gpll6", -}; - -static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = { - { P_XO, 0 }, - { P_UBI32_PLL, 1 }, - { P_GPLL0, 2 }, - { P_GPLL2, 3 }, - { P_GPLL4, 4 }, - { P_GPLL6, 5 }, -}; - -static const char * const gcc_xo_gpll0_out_main_div2[] = { - "xo", - "gpll0_out_main_div2", -}; - -static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = { - { P_XO, 0 }, - { P_GPLL0_DIV2, 1 }, -}; - -static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = { - "xo", - "bias_pll_cc_clk", - "gpll0", - "gpll4", - "nss_crypto_pll", - "ubi32_pll", -}; - -static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = { - { P_XO, 0 }, - { P_BIAS_PLL, 1 }, - { P_GPLL0, 2 }, - { P_GPLL4, 3 }, - { P_NSS_CRYPTO_PLL, 4 }, - { P_UBI32_PLL, 5 }, -}; - -static const char * const gcc_xo_gpll0_gpll4[] = { - "xo", - "gpll0", - "gpll4", -}; - -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL4, 2 }, -}; - -static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = { - "xo", - "uniphy0_gcc_rx_clk", - "uniphy0_gcc_tx_clk", - "ubi32_pll", - "bias_pll_cc_clk", -}; - -static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = { - { P_XO, 0 }, - { P_UNIPHY0_RX, 1 }, - { P_UNIPHY0_TX, 2 }, - { P_UBI32_PLL, 5 }, - { P_BIAS_PLL, 6 }, -}; - -static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = { - "xo", - "uniphy0_gcc_tx_clk", - "uniphy0_gcc_rx_clk", - "ubi32_pll", - "bias_pll_cc_clk", -}; - -static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = { - { P_XO, 0 }, - { P_UNIPHY0_TX, 1 }, - { P_UNIPHY0_RX, 2 }, - { P_UBI32_PLL, 5 }, - { P_BIAS_PLL, 6 }, -}; - -static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = { - "xo", - "uniphy0_gcc_rx_clk", - "uniphy0_gcc_tx_clk", - "uniphy1_gcc_rx_clk", - "uniphy1_gcc_tx_clk", - "ubi32_pll", - "bias_pll_cc_clk", -}; - -static const struct parent_map -gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = { - { P_XO, 0 }, - { P_UNIPHY0_RX, 1 }, - { P_UNIPHY0_TX, 2 }, - { P_UNIPHY1_RX, 3 }, - { P_UNIPHY1_TX, 4 }, - { P_UBI32_PLL, 5 }, - { P_BIAS_PLL, 6 }, -}; - -static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = { - "xo", - "uniphy0_gcc_tx_clk", - "uniphy0_gcc_rx_clk", - "uniphy1_gcc_tx_clk", - "uniphy1_gcc_rx_clk", - "ubi32_pll", - "bias_pll_cc_clk", -}; - -static const struct parent_map -gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = { - { P_XO, 0 }, - { P_UNIPHY0_TX, 1 }, - { P_UNIPHY0_RX, 2 }, - { P_UNIPHY1_TX, 3 }, - { P_UNIPHY1_RX, 4 }, - { P_UBI32_PLL, 5 }, - { P_BIAS_PLL, 6 }, -}; - -static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = { - "xo", - "uniphy2_gcc_rx_clk", - "uniphy2_gcc_tx_clk", - "ubi32_pll", - "bias_pll_cc_clk", -}; - -static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = { - { P_XO, 0 }, - { P_UNIPHY2_RX, 1 }, - { P_UNIPHY2_TX, 2 }, - { P_UBI32_PLL, 5 }, - { P_BIAS_PLL, 6 }, -}; - -static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = { - "xo", - "uniphy2_gcc_tx_clk", - "uniphy2_gcc_rx_clk", - "ubi32_pll", - "bias_pll_cc_clk", -}; - -static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = { - { P_XO, 0 }, - { P_UNIPHY2_TX, 1 }, - { P_UNIPHY2_RX, 2 }, - { P_UBI32_PLL, 5 }, - { P_BIAS_PLL, 6 }, -}; - -static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = { - "xo", - "gpll0", - "gpll6", - "gpll0_out_main_div2", - "sleep_clk", -}; - -static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = { - { P_XO, 0 }, - { P_GPLL0, 1 }, - { P_GPLL6, 2 }, - { P_GPLL0_DIV2, 4 }, - { P_SLEEP_CLK, 6 }, -}; - static struct clk_alpha_pll gpll0_main = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], @@ -400,8 +57,9 @@ static struct clk_alpha_pll gpll0_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_main", - .parent_names = (const char *[]){ - "xo" + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -414,9 +72,8 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll0_out_main_div2", - .parent_names = (const char *[]){ - "gpll0_main" - }, + .parent_hws = (const struct clk_hw *[]){ + &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, .flags = CLK_SET_RATE_PARENT, @@ -429,9 +86,8 @@ static struct clk_alpha_pll_postdiv gpll0 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll0", - .parent_names = (const char *[]){ - "gpll0_main" - }, + .parent_hws = (const struct clk_hw *[]){ + &gpll0_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, }, @@ -445,8 +101,9 @@ static struct clk_alpha_pll gpll2_main = { .enable_mask = BIT(2), .hw.init = &(struct clk_init_data){ .name = "gpll2_main", - .parent_names = (const char *[]){ - "xo" + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -461,9 +118,8 @@ static struct clk_alpha_pll_postdiv gpll2 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll2", - .parent_names = (const char *[]){ - "gpll2_main" - }, + .parent_hws = (const struct clk_hw *[]){ + &gpll2_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, .flags = CLK_SET_RATE_PARENT, @@ -478,8 +134,9 @@ static struct clk_alpha_pll gpll4_main = { .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gpll4_main", - .parent_names = (const char *[]){ - "xo" + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -494,9 +151,8 @@ static struct clk_alpha_pll_postdiv gpll4 = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll4", - .parent_names = (const char *[]){ - "gpll4_main" - }, + .parent_hws = (const struct clk_hw *[]){ + &gpll4_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, .flags = CLK_SET_RATE_PARENT, @@ -512,8 +168,9 @@ static struct clk_alpha_pll gpll6_main = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gpll6_main", - .parent_names = (const char *[]){ - "xo" + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -528,9 +185,8 @@ static struct clk_alpha_pll_postdiv gpll6 = { .width = 2, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll6", - .parent_names = (const char *[]){ - "gpll6_main" - }, + .parent_hws = (const struct clk_hw *[]){ + &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, .flags = CLK_SET_RATE_PARENT, @@ -542,9 +198,8 @@ static struct clk_fixed_factor gpll6_out_main_div2 = { .div = 2, .hw.init = &(struct clk_init_data){ .name = "gpll6_out_main_div2", - .parent_names = (const char *[]){ - "gpll6_main" - }, + .parent_hws = (const struct clk_hw *[]){ + &gpll6_main.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, .flags = CLK_SET_RATE_PARENT, @@ -560,8 +215,9 @@ static struct clk_alpha_pll ubi32_pll_main = { .enable_mask = BIT(6), .hw.init = &(struct clk_init_data){ .name = "ubi32_pll_main", - .parent_names = (const char *[]){ - "xo" + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_huayra_ops, @@ -575,9 +231,8 @@ static struct clk_alpha_pll_postdiv ubi32_pll = { .width = 2, .clkr.hw.init = &(struct clk_init_data){ .name = "ubi32_pll", - .parent_names = (const char *[]){ - "ubi32_pll_main" - }, + .parent_hws = (const struct clk_hw *[]){ + &ubi32_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, .flags = CLK_SET_RATE_PARENT, @@ -592,8 +247,9 @@ static struct clk_alpha_pll nss_crypto_pll_main = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "nss_crypto_pll_main", - .parent_names = (const char *[]){ - "xo" + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo", }, .num_parents = 1, .ops = &clk_alpha_pll_ops, @@ -607,9 +263,8 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { .width = 4, .clkr.hw.init = &(struct clk_init_data){ .name = "nss_crypto_pll", - .parent_names = (const char *[]){ - "nss_crypto_pll_main" - }, + .parent_hws = (const struct clk_hw *[]){ + &nss_crypto_pll_main.clkr.hw }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, .flags = CLK_SET_RATE_PARENT, @@ -623,6 +278,18 @@ static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { { } }; +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &gpll0.clkr.hw}, + { .hw = &gpll0_out_main_div2.hw}, +}; + +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL0_DIV2, 4 }, +}; + static struct clk_rcg2 pcnoc_bfdcd_clk_src = { .cmd_rcgr = 0x27000, .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, @@ -630,8 +297,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pcnoc_bfdcd_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, .flags = CLK_IS_CRITICAL, }, @@ -642,9 +309,8 @@ static struct clk_fixed_factor pcnoc_clk_src = { .div = 1, .hw.init = &(struct clk_init_data){ .name = "pcnoc_clk_src", - .parent_names = (const char *[]){ - "pcnoc_bfdcd_clk_src" - }, + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, .num_parents = 1, .ops = &clk_fixed_factor_ops, .flags = CLK_SET_RATE_PARENT, @@ -658,8 +324,9 @@ static struct clk_branch gcc_sleep_clk_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_sleep_clk_src", - .parent_names = (const char *[]){ - "sleep_clk" + .parent_data = &(const struct clk_parent_data){ + .fw_name = "sleep_clk", + .name = "sleep_clk", }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -682,8 +349,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -708,8 +375,8 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -721,8 +388,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -735,8 +402,8 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -748,8 +415,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -762,8 +429,8 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -775,8 +442,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -789,8 +456,8 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -802,8 +469,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -816,8 +483,8 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup5_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -829,8 +496,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_i2c_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -843,8 +510,8 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup6_spi_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -877,8 +544,8 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -891,8 +558,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -905,8 +572,8 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -919,8 +586,8 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart4_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -933,8 +600,8 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart5_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -947,8 +614,8 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart6_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; @@ -958,6 +625,11 @@ static const struct clk_parent_data gcc_xo_gpll0[] = { { .hw = &gpll0.clkr.hw }, }; +static const struct parent_map gcc_xo_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, +}; + static const struct freq_tbl ftbl_pcie_axi_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(200000000, P_GPLL0, 4, 0, 0), @@ -972,7 +644,7 @@ static struct clk_rcg2 pcie0_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie0_axi_clk_src", .parent_data = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -981,6 +653,18 @@ static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { F(19200000, P_XO, 1, 0, 0), }; +static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "sleep_clk", .name = "sleep_clk" }, +}; + +static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = { + { P_XO, 0 }, + { P_GPLL0, 2 }, + { P_SLEEP_CLK, 6 }, +}; + static struct clk_rcg2 pcie0_aux_clk_src = { .cmd_rcgr = 0x75024, .freq_tbl = ftbl_pcie_aux_clk_src, @@ -989,12 +673,22 @@ static struct clk_rcg2 pcie0_aux_clk_src = { .parent_map = gcc_xo_gpll0_sleep_clk_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie0_aux_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk), .ops = &clk_rcg2_ops, }, }; +static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = { + { .name = "pcie20_phy0_pipe_clk" }, + { .fw_name = "xo", .name = "xo" }, +}; + +static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = { + { P_PCIE20_PHY0_PIPE, 0 }, + { P_XO, 2 }, +}; + static struct clk_regmap_mux pcie0_pipe_clk_src = { .reg = 0x7501c, .shift = 8, @@ -1003,8 +697,8 @@ static struct clk_regmap_mux pcie0_pipe_clk_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "pcie0_pipe_clk_src", - .parent_names = gcc_pcie20_phy0_pipe_clk_xo, - .num_parents = 2, + .parent_data = gcc_pcie20_phy0_pipe_clk_xo, + .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -1019,7 +713,7 @@ static struct clk_rcg2 pcie1_axi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie1_axi_clk_src", .parent_data = gcc_xo_gpll0, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1032,12 +726,22 @@ static struct clk_rcg2 pcie1_aux_clk_src = { .parent_map = gcc_xo_gpll0_sleep_clk_map, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie1_aux_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk), .ops = &clk_rcg2_ops, }, }; +static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = { + { .name = "pcie20_phy1_pipe_clk" }, + { .fw_name = "xo", .name = "xo" }, +}; + +static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = { + { P_PCIE20_PHY1_PIPE, 0 }, + { P_XO, 2 }, +}; + static struct clk_regmap_mux pcie1_pipe_clk_src = { .reg = 0x7601c, .shift = 8, @@ -1046,8 +750,8 @@ static struct clk_regmap_mux pcie1_pipe_clk_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "pcie1_pipe_clk_src", - .parent_names = gcc_pcie20_phy1_pipe_clk_xo, - .num_parents = 2, + .parent_data = gcc_pcie20_phy1_pipe_clk_xo, + .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -1066,6 +770,20 @@ static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { { } }; +static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL2, 2 }, + { P_GPLL0_DIV2, 4 }, +}; + static struct clk_rcg2 sdcc1_apps_clk_src = { .cmd_rcgr = 0x42004, .freq_tbl = ftbl_sdcc_apps_clk_src, @@ -1074,8 +792,8 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, - .num_parents = 4, + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), .ops = &clk_rcg2_floor_ops, }, }; @@ -1086,6 +804,20 @@ static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = { F(308570000, P_GPLL6, 3.5, 0, 0), }; +static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = { + { P_XO, 0 }, + { P_GPLL0, 1 }, + { P_GPLL6, 2 }, + { P_GPLL0_DIV2, 4 }, +}; + static struct clk_rcg2 sdcc1_ice_core_clk_src = { .cmd_rcgr = 0x5d000, .freq_tbl = ftbl_sdcc_ice_core_clk_src, @@ -1094,8 +826,8 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", - .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2, - .num_parents = 4, + .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2), .ops = &clk_rcg2_ops, }, }; @@ -1108,8 +840,8 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", - .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, - .num_parents = 4, + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2), .ops = &clk_rcg2_floor_ops, }, }; @@ -1121,6 +853,18 @@ static const struct freq_tbl ftbl_usb_master_clk_src[] = { { } }; +static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &gpll0_out_main_div2.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { + { P_XO, 0 }, + { P_GPLL0_DIV2, 2 }, + { P_GPLL0, 1 }, +}; + static struct clk_rcg2 usb0_master_clk_src = { .cmd_rcgr = 0x3e00c, .freq_tbl = ftbl_usb_master_clk_src, @@ -1129,8 +873,8 @@ static struct clk_rcg2 usb0_master_clk_src = { .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "usb0_master_clk_src", - .parent_names = gcc_xo_gpll0_out_main_div2_gpll0, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1148,8 +892,8 @@ static struct clk_rcg2 usb0_aux_clk_src = { .parent_map = gcc_xo_gpll0_sleep_clk_map, .clkr.hw.init = &(struct clk_init_data){ .name = "usb0_aux_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -1161,6 +905,20 @@ static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = { { } }; +static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = { + { P_XO, 0 }, + { P_GPLL6, 1 }, + { P_GPLL0, 3 }, + { P_GPLL0_DIV2, 4 }, +}; + static struct clk_rcg2 usb0_mock_utmi_clk_src = { .cmd_rcgr = 0x3e020, .freq_tbl = ftbl_usb_mock_utmi_clk_src, @@ -1169,12 +927,22 @@ static struct clk_rcg2 usb0_mock_utmi_clk_src = { .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "usb0_mock_utmi_clk_src", - .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2, - .num_parents = 4, + .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; +static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = { + { .name = "usb3phy_0_cc_pipe_clk" }, + { .fw_name = "xo", .name = "xo" }, +}; + +static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { + { P_USB3PHY_0_PIPE, 0 }, + { P_XO, 2 }, +}; + static struct clk_regmap_mux usb0_pipe_clk_src = { .reg = 0x3e048, .shift = 8, @@ -1183,8 +951,8 @@ static struct clk_regmap_mux usb0_pipe_clk_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "usb0_pipe_clk_src", - .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo, - .num_parents = 2, + .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, + .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -1199,8 +967,8 @@ static struct clk_rcg2 usb1_master_clk_src = { .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, .clkr.hw.init = &(struct clk_init_data){ .name = "usb1_master_clk_src", - .parent_names = gcc_xo_gpll0_out_main_div2_gpll0, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0), .ops = &clk_rcg2_ops, }, }; @@ -1213,8 +981,8 @@ static struct clk_rcg2 usb1_aux_clk_src = { .parent_map = gcc_xo_gpll0_sleep_clk_map, .clkr.hw.init = &(struct clk_init_data){ .name = "usb1_aux_clk_src", - .parent_names = gcc_xo_gpll0_sleep_clk, - .num_parents = 3, + .parent_data = gcc_xo_gpll0_sleep_clk, + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk), .ops = &clk_rcg2_ops, }, }; @@ -1227,12 +995,22 @@ static struct clk_rcg2 usb1_mock_utmi_clk_src = { .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map, .clkr.hw.init = &(struct clk_init_data){ .name = "usb1_mock_utmi_clk_src", - .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2, - .num_parents = 4, + .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2, + .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2), .ops = &clk_rcg2_ops, }, }; +static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = { + { .name = "usb3phy_1_cc_pipe_clk" }, + { .fw_name = "xo", .name = "xo" }, +}; + +static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = { + { P_USB3PHY_1_PIPE, 0 }, + { P_XO, 2 }, +}; + static struct clk_regmap_mux usb1_pipe_clk_src = { .reg = 0x3f048, .shift = 8, @@ -1241,8 +1019,8 @@ static struct clk_regmap_mux usb1_pipe_clk_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "usb1_pipe_clk_src", - .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo, - .num_parents = 2, + .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo, + .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo), .ops = &clk_regmap_mux_closest_ops, .flags = CLK_SET_RATE_PARENT, }, @@ -1256,8 +1034,9 @@ static struct clk_branch gcc_xo_clk_src = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gcc_xo_clk_src", - .parent_names = (const char *[]){ - "xo" + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo", }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, @@ -1271,9 + |