diff options
Diffstat (limited to 'drivers/phy')
37 files changed, 4832 insertions, 617 deletions
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index de9362c25c07..01b53f86004c 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -49,6 +49,17 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config USB_LGM_PHY + tristate "INTEL Lightning Mountain USB PHY Driver" + depends on USB_SUPPORT + select USB_PHY + select REGULATOR + select REGULATOR_FIXED_VOLTAGE + help + Enable this to support Intel DWC3 PHY USB phy. This driver provides + interface to interact with USB GEN-II and USB 3.x PHY that is part + of the Intel network SOC. + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c27408e4daae..6eb2916773c5 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o +obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o obj-y += allwinner/ \ amlogic/ \ broadcom/ \ diff --git a/drivers/phy/broadcom/phy-bcm-ns-usb3.c b/drivers/phy/broadcom/phy-bcm-ns-usb3.c index 14f45bc35cc5..47b029fbebbd 100644 --- a/drivers/phy/broadcom/phy-bcm-ns-usb3.c +++ b/drivers/phy/broadcom/phy-bcm-ns-usb3.c @@ -13,6 +13,7 @@ #include <linux/bcma/bcma.h> #include <linux/delay.h> #include <linux/err.h> +#include <linux/iopoll.h> #include <linux/mdio.h> #include <linux/module.h> #include <linux/of_address.h> @@ -258,29 +259,24 @@ static struct mdio_driver bcm_ns_usb3_mdio_driver = { **************************************************/ static int bcm_ns_usb3_wait_reg(struct bcm_ns_usb3 *usb3, void __iomem *addr, - u32 mask, u32 value, unsigned long timeout) + u32 mask, u32 value, int usec) { - unsigned long deadline = jiffies + timeout; u32 val; + int ret; - do { - val = readl(addr); - if ((val & mask) == value) - return 0; - cpu_relax(); - udelay(10); - } while (!time_after_eq(jiffies, deadline)); + ret = readl_poll_timeout_atomic(addr, val, ((val & mask) == value), + 10, usec); + if (ret) + dev_err(usb3->dev, "Timeout waiting for register %p\n", addr); - dev_err(usb3->dev, "Timeout waiting for register %p\n", addr); - - return -EBUSY; + return ret; } static inline int bcm_ns_usb3_mii_mng_wait_idle(struct bcm_ns_usb3 *usb3) { return bcm_ns_usb3_wait_reg(usb3, usb3->ccb_mii + BCMA_CCB_MII_MNG_CTL, 0x0100, 0x0000, - usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US)); + BCM_NS_USB3_MII_MNG_TIMEOUT_US); } static int bcm_ns_usb3_platform_phy_write(struct bcm_ns_usb3 *usb3, u16 reg, diff --git a/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c b/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c index 527625912b78..9630ac127366 100644 --- a/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c +++ b/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c @@ -18,6 +18,7 @@ #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/irq.h> #include <linux/mfd/syscon.h> #include <linux/module.h> @@ -87,17 +88,11 @@ static const unsigned int usb_extcon_cable[] = { static inline int pll_lock_stat(u32 usb_reg, int reg_mask, struct ns2_phy_driver *driver) { - int retry = PLL_LOCK_RETRY; u32 val; - do { - udelay(1); - val = readl(driver->icfgdrd_regs + usb_reg); - if (val & reg_mask) - return 0; - } while (--retry > 0); - - return -EBUSY; + return readl_poll_timeout_atomic(driver->icfgdrd_regs + usb_reg, + val, (val & reg_mask), 1, + PLL_LOCK_RETRY); } static int ns2_drd_phy_init(struct phy *phy) diff --git a/drivers/phy/broadcom/phy-bcm-sr-usb.c b/drivers/phy/broadcom/phy-bcm-sr-usb.c index 77c025a0720c..c3e99ad17487 100644 --- a/drivers/phy/broadcom/phy-bcm-sr-usb.c +++ b/drivers/phy/broadcom/phy-bcm-sr-usb.c @@ -5,6 +5,7 @@ #include <linux/delay.h> #include <linux/io.h> +#include <linux/iopoll.h> #include <linux/module.h> #include <linux/of.h> #include <linux/phy/phy.h> @@ -109,19 +110,15 @@ static inline void bcm_usb_reg32_setbits(void __iomem *addr, uint32_t set) static int bcm_usb_pll_lock_check(void __iomem *addr, u32 bit) { - int retry; - u32 rd_data; + u32 data; + int ret; - retry = PLL_LOCK_RETRY_COUNT; - do { - rd_data = readl(addr); - if (rd_data & bit) - return 0; - udelay(1); - } while (--retry > 0); + ret = readl_poll_timeout_atomic(addr, data, (data & bit), 1, + PLL_LOCK_RETRY_COUNT); + if (ret) + pr_err("%s: FAIL\n", __func__); - pr_err("%s: FAIL\n", __func__); - return -ETIMEDOUT; + return ret; } static int bcm_usb_ss_phy_init(struct bcm_usb_phy_cfg *phy_cfg) diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c index 016514e4aa54..88e239adc3b8 100644 --- a/drivers/phy/cadence/phy-cadence-salvo.c +++ b/drivers/phy/cadence/phy-cadence-salvo.c @@ -97,7 +97,7 @@ struct cdns_reg_pairs { struct cdns_salvo_data { u8 reg_offset_shift; - struct cdns_reg_pairs *init_sequence_val; + const struct cdns_reg_pairs *init_sequence_val; u8 init_sequence_length; }; @@ -126,7 +126,7 @@ static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy, * Below bringup sequence pair are from Cadence PHY's User Guide * and NXP platform tuning results. */ -static struct cdns_reg_pairs cdns_nxp_sequence_pair[] = { +static const struct cdns_reg_pairs cdns_nxp_sequence_pair[] = { {0x0830, PHY_PMA_CMN_CTRL1}, {0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL}, {0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR}, @@ -217,7 +217,7 @@ static int cdns_salvo_phy_init(struct phy *phy) return ret; for (i = 0; i < data->init_sequence_length; i++) { - struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i; + const struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i; cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val); } @@ -251,7 +251,7 @@ static int cdns_salvo_phy_power_off(struct phy *phy) return 0; } -static struct phy_ops cdns_salvo_phy_ops = { +static const struct phy_ops cdns_salvo_phy_ops = { .init = cdns_salvo_phy_init, .power_on = cdns_salvo_phy_power_on, .power_off = cdns_salvo_phy_power_off, diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index faed652b73f7..453ef26fa1c7 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -172,10 +172,10 @@ struct cdns_sierra_data { u32 pcie_ln_regs; u32 usb_cmn_regs; u32 usb_ln_regs; - struct cdns_reg_pairs *pcie_cmn_vals; - struct cdns_reg_pairs *pcie_ln_vals; - struct cdns_reg_pairs *usb_cmn_vals; - struct cdns_reg_pairs *usb_ln_vals; + const struct cdns_reg_pairs *pcie_cmn_vals; + const struct cdns_reg_pairs *pcie_ln_vals; + const struct cdns_reg_pairs *usb_cmn_vals; + const struct cdns_reg_pairs *usb_ln_vals; }; struct cdns_regmap_cdb_context { @@ -233,7 +233,7 @@ static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) .reg_read = cdns_regmap_read, \ } -static struct regmap_config cdns_sierra_lane_cdb_config[] = { +static const struct regmap_config cdns_sierra_lane_cdb_config[] = { SIERRA_LANE_CDB_REGMAP_CONF("0"), SIERRA_LANE_CDB_REGMAP_CONF("1"), SIERRA_LANE_CDB_REGMAP_CONF("2"), @@ -252,7 +252,7 @@ static struct regmap_config cdns_sierra_lane_cdb_config[] = { SIERRA_LANE_CDB_REGMAP_CONF("15"), }; -static struct regmap_config cdns_sierra_common_cdb_config = { +static const struct regmap_config cdns_sierra_common_cdb_config = { .name = "sierra_common_cdb", .reg_stride = 1, .fast_io = true, @@ -260,7 +260,7 @@ static struct regmap_config cdns_sierra_common_cdb_config = { .reg_read = cdns_regmap_read, }; -static struct regmap_config cdns_sierra_phy_config_ctrl_config = { +static const struct regmap_config cdns_sierra_phy_config_ctrl_config = { .name = "sierra_phy_config_ctrl", .reg_stride = 1, .fast_io = true, @@ -274,7 +274,7 @@ static int cdns_sierra_phy_init(struct phy *gphy) struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent); struct regmap *regmap; int i, j; - struct cdns_reg_pairs *cmn_vals, *ln_vals; + const struct cdns_reg_pairs *cmn_vals, *ln_vals; u32 num_cmn_regs, num_ln_regs; /* Initialise the PHY registers, unless auto configured */ @@ -654,7 +654,7 @@ static int cdns_sierra_phy_remove(struct platform_device *pdev) } /* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */ -static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { +static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, {0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, {0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG}, @@ -663,7 +663,7 @@ static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = { }; /* refclk100MHz_32b_PCIe_ln_ext_ssc */ -static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { +static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { {0x813E, SIERRA_CLKPATHCTRL_TMR_PREG}, {0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG}, {0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG}, @@ -674,7 +674,7 @@ static struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { }; /* refclk100MHz_20b_USB_cmn_pll_ext_ssc */ -static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { +static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG}, {0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG}, {0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}, @@ -682,7 +682,7 @@ static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = { }; /* refclk100MHz_20b_USB_ln_ext_ssc */ -static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { +static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = { {0xFE0A, SIERRA_DET_STANDEC_A_PREG}, {0x000F, SIERRA_DET_STANDEC_B_PREG}, {0x55A5, SIERRA_DET_STANDEC_C_PREG}, diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c index 7116127358ee..f310e15d94cb 100644 --- a/drivers/phy/cadence/phy-cadence-torrent.c +++ b/drivers/phy/cadence/phy-cadence-torrent.c @@ -25,11 +25,14 @@ #define REF_CLK_19_2MHz 19200000 #define REF_CLK_25MHz 25000000 -#define DEFAULT_NUM_LANES 4 #define MAX_NUM_LANES 4 #define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ +#define NUM_SSC_MODE 3 +#define NUM_PHY_TYPE 6 + #define POLL_TIMEOUT_US 5000 +#define PLL_LOCK_TIMEOUT 100000 #define TORRENT_COMMON_CDB_OFFSET 0x0 @@ -79,6 +82,8 @@ #define CMN_PLLSM0_PLLLOCK_TMR 0x002CU #define CMN_PLLSM1_PLLPRE_TMR 0x0032U #define CMN_PLLSM1_PLLLOCK_TMR 0x0034U +#define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U +#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U #define CMN_BGCAL_INIT_TMR 0x0064U #define CMN_BGCAL_ITER_TMR 0x0065U #define CMN_IBCAL_INIT_TMR 0x0074U @@ -99,6 +104,14 @@ #define CMN_PLL0_LOCK_REFCNT_START 0x009CU #define CMN_PLL0_LOCK_PLLCNT_START 0x009EU #define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU +#define CMN_PLL0_INTDIV_M1 0x00A0U +#define CMN_PLL0_FRACDIVH_M1 0x00A2U +#define CMN_PLL0_HIGH_THR_M1 0x00A3U +#define CMN_PLL0_DSM_DIAG_M1 0x00A4U +#define CMN_PLL0_SS_CTRL1_M1 0x00A8U +#define CMN_PLL0_SS_CTRL2_M1 0x00A9U +#define CMN_PLL0_SS_CTRL3_M1 0x00AAU +#define CMN_PLL0_SS_CTRL4_M1 0x00ABU #define CMN_PLL1_VCOCAL_TCTRL 0x00C2U #define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U #define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U @@ -116,8 +129,10 @@ #define CMN_PLL1_LOCK_REFCNT_START 0x00DCU #define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU #define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU +#define CMN_TXPUCAL_TUNE 0x0103U #define CMN_TXPUCAL_INIT_TMR 0x0104U #define CMN_TXPUCAL_ITER_TMR 0x0105U +#define CMN_TXPDCAL_TUNE 0x010BU #define CMN_TXPDCAL_INIT_TMR 0x010CU #define CMN_TXPDCAL_ITER_TMR 0x010DU #define CMN_RXCAL_INIT_TMR 0x0114U @@ -131,24 +146,31 @@ #define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U #define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U #define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U +#define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U +#define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U #define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U #define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U +#define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U #define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U #define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U #define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U #define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U #define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U +#define CMN_DIAG_BIAS_OVRD1 0x01E1U /* PMA TX Lane registers */ #define TX_TXCC_CTRL 0x0040U #define TX_TXCC_CPOST_MULT_00 0x004CU +#define TX_TXCC_CPOST_MULT_01 0x004DU #define TX_TXCC_MGNFS_MULT_000 0x0050U #define DRV_DIAG_TX_DRV 0x00C6U #define XCVR_DIAG_PLLDRC_CTRL 0x00E5U #define XCVR_DIAG_HSCLK_SEL 0x00E6U #define XCVR_DIAG_HSCLK_DIV 0x00E7U #define XCVR_DIAG_BIDI_CTRL 0x00EAU +#define XCVR_DIAG_PSC_OVRD 0x00EBU #define TX_PSC_A0 0x0100U +#define TX_PSC_A1 0x0101U #define TX_PSC_A2 0x0102U #define TX_PSC_A3 0x0103U #define TX_RCVDET_ST_TMR 0x0123U @@ -157,23 +179,49 @@ /* PMA RX Lane registers */ #define RX_PSC_A0 0x0000U +#define RX_PSC_A1 0x0001U #define RX_PSC_A2 0x0002U #define RX_PSC_A3 0x0003U #define RX_PSC_CAL 0x0006U +#define RX_CDRLF_CNFG 0x0080U +#define RX_CDRLF_CNFG3 0x0082U +#define RX_SIGDET_HL_FILT_TMR 0x0090U #define RX_REE_GCSM1_CTRL 0x0108U +#define RX_REE_GCSM1_EQENM_PH1 0x0109U +#define RX_REE_GCSM1_EQENM_PH2 0x010AU #define RX_REE_GCSM2_CTRL 0x0110U #define RX_REE_PERGCSM_CTRL 0x0118U +#define RX_REE_ATTEN_THR 0x0149U +#define RX_REE_TAP1_CLIP 0x0171U +#define RX_REE_TAP2TON_CLIP 0x0172U +#define RX_REE_SMGM_CTRL1 0x0177U +#define RX_REE_SMGM_CTRL2 0x0178U +#define RX_DIAG_DFE_CTRL 0x01E0U +#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U +#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U +#define RX_DIAG_NQST_CTRL 0x01E5U +#define RX_DIAG_SIGDET_TUNE 0x01E8U +#define RX_DIAG_PI_RATE 0x01F4U +#define RX_DIAG_PI_CAP 0x01F5U +#define RX_DIAG_ACYA 0x01FFU /* PHY PCS common registers */ #define PHY_PLL_CFG 0x000EU +#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U +#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U +#define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U /* PHY PMA common registers */ +#define PHY_PMA_CMN_CTRL1 0x0000U #define PHY_PMA_CMN_CTRL2 0x0001U #define PHY_PMA_PLL_RAW_CTRL 0x0003U static const struct reg_field phy_pll_cfg = REG_FIELD(PHY_PLL_CFG, 0, 1); +static const struct reg_field phy_pma_cmn_ctrl_1 = + REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0); + static const struct reg_field phy_pma_cmn_ctrl_2 = REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7); @@ -183,14 +231,28 @@ static const struct reg_field phy_pma_pll_raw_ctrl = static const struct reg_field phy_reset_ctrl = REG_FIELD(PHY_RESET, 8, 8); -static const struct of_device_id cdns_torrent_phy_of_match[]; +enum cdns_torrent_phy_type { + TYPE_NONE, + TYPE_DP, + TYPE_PCIE, + TYPE_SGMII, + TYPE_QSGMII, + TYPE_USB, +}; + +enum cdns_torrent_ssc_mode { + NO_SSC, + EXTERNAL_SSC, + INTERNAL_SSC +}; struct cdns_torrent_inst { struct phy *phy; u32 mlane; - u32 phy_type; + enum cdns_torrent_phy_type phy_type; u32 num_lanes; struct reset_control *lnk_rst; + enum cdns_torrent_ssc_mode ssc_mode; }; struct cdns_torrent_phy { @@ -198,11 +260,13 @@ struct cdns_torrent_phy { void __iomem *sd_base; /* SD0801 registers base */ u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */ struct reset_control *phy_rst; + struct reset_control *apb_rst; struct device *dev; struct clk *clk; unsigned long ref_clk_rate; struct cdns_torrent_inst phys[MAX_NUM_LANES]; int nsubnodes; + const struct cdns_torrent_data *init_data; struct regmap *regmap; struct regmap *regmap_common_cdb; struct regmap *regmap_phy_pcs_common_cdb; @@ -211,6 +275,7 @@ struct cdns_torrent_phy { struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES]; struct regmap *regmap_dptx_phy_reg; struct regmap_field *phy_pll_cfg; + struct regmap_field *phy_pma_cmn_ctrl_1; struct regmap_field *phy_pma_cmn_ctrl_2; struct regmap_field *phy_pma_pll_raw_ctrl; struct regmap_field *phy_reset_ctrl; @@ -223,8 +288,8 @@ enum phy_powerstate { POWERSTATE_A3 = 3, }; +static int cdns_torrent_phy_init(struct phy *phy); static int cdns_torrent_dp_init(struct phy *phy); -static int cdns_torrent_dp_exit(struct phy *phy); static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, u32 num_lanes); static @@ -254,17 +319,38 @@ static int cdns_torrent_phy_on(struct phy *phy); static int cdns_torrent_phy_off(struct phy *phy); static const struct phy_ops cdns_torrent_phy_ops = { - .init = cdns_torrent_dp_init, - .exit = cdns_torrent_dp_exit, + .init = cdns_torrent_phy_init, .configure = cdns_torrent_dp_configure, .power_on = cdns_torrent_phy_on, .power_off = cdns_torrent_phy_off, .owner = THIS_MODULE, }; +struct cdns_reg_pairs { + u32 val; + u32 off; +}; + +struct cdns_torrent_vals { + struct cdns_reg_pairs *reg_pairs; + u32 num_regs; +}; + struct cdns_torrent_data { - u8 block_offset_shift; - u8 reg_offset_shift; + u8 block_offset_shift; + u8 reg_offset_shift; + struct cdns_torrent_vals *link_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *xcvr_diag_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *tx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; + struct cdns_torrent_vals *rx_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE] + [NUM_SSC_MODE]; }; struct cdns_regmap_cdb_context { @@ -331,21 +417,21 @@ static int cdns_regmap_dptx_read(void *context, unsigned int reg, .reg_read = cdns_regmap_read, \ } -static struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { +static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { TORRENT_TX_LANE_CDB_REGMAP_CONF("0"), TORRENT_TX_LANE_CDB_REGMAP_CONF("1"), TORRENT_TX_LANE_CDB_REGMAP_CONF("2"), TORRENT_TX_LANE_CDB_REGMAP_CONF("3"), }; -static struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { +static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { TORRENT_RX_LANE_CDB_REGMAP_CONF("0"), TORRENT_RX_LANE_CDB_REGMAP_CONF("1"), TORRENT_RX_LANE_CDB_REGMAP_CONF("2"), TORRENT_RX_LANE_CDB_REGMAP_CONF("3"), }; -static struct regmap_config cdns_torrent_common_cdb_config = { +static const struct regmap_config cdns_torrent_common_cdb_config = { .name = "torrent_common_cdb", .reg_stride = 1, .fast_io = true, @@ -353,7 +439,7 @@ static struct regmap_config cdns_torrent_common_cdb_config = { .reg_read = cdns_regmap_read, }; -static struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { +static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { .name = "torrent_phy_pcs_cmn_cdb", .reg_stride = 1, .fast_io = true, @@ -361,7 +447,7 @@ static struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { .reg_read = cdns_regmap_read, }; -static struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { +static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { .name = "torrent_phy_pma_cmn_cdb", .reg_stride = 1, .fast_io = true, @@ -369,7 +455,7 @@ static struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { .reg_read = cdns_regmap_read, }; -static struct regmap_config cdns_torrent_dptx_phy_config = { +static const struct regmap_config cdns_torrent_dptx_phy_config = { .name = "torrent_dptx_phy", .reg_stride = 1, .fast_io = true, @@ -848,19 +934,6 @@ static int cdns_torrent_dp_init(struct phy *phy) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; - ret = clk_prepare_enable(cdns_phy->clk); - if (ret) { - dev_err(cdns_phy->dev, "Failed to prepare ref clock\n"); - return ret; - } - - cdns_phy->ref_clk_rate = clk_get_rate(cdns_phy->clk); - if (!(cdns_phy->ref_clk_rate)) { - dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); - clk_disable_unprepare(cdns_phy->clk); - return -EINVAL; - } - switch (cdns_phy->ref_clk_rate) { case REF_CLK_19_2MHz: case REF_CLK_25MHz: @@ -920,14 +993,6 @@ static int cdns_torrent_dp_init(struct phy *phy) return ret; } -static int cdns_torrent_dp_exit(struct phy *phy) -{ - struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); - - clk_disable_unprepare(cdns_phy->clk); - return 0; -} - static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) { @@ -1543,15 +1608,34 @@ static int cdns_torrent_phy_on(struct phy *phy) { struct cdns_torrent_inst *inst = phy_get_drvdata(phy); struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); + u32 read_val; int ret; - /* Take the PHY out of reset */ - ret = reset_control_deassert(cdns_phy->phy_rst); - if (ret) + if (cdns_phy->nsubnodes == 1) { + /* Take the PHY lane group out of reset */ + reset_control_deassert(inst->lnk_rst); + + /* Take the PHY out of reset */ + ret = reset_control_deassert(cdns_phy->phy_rst); + if (ret) + return ret; + } + + /* + * Wait for cmn_ready assertion + * PHY_PMA_CMN_CTRL1[0] == 1 + */ + ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1, + read_val, read_val, 1000, + PLL_LOCK_TIMEOUT); + if (ret) { + dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n"); return ret; + } + + mdelay(10); - /* Take the PHY lane group out of reset */ - return reset_control_deassert(inst->lnk_rst); + return 0; } static int cdns_torrent_phy_off(struct phy *phy) @@ -1560,6 +1644,9 @@ static int cdns_torrent_phy_off(struct phy *phy) struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); int ret; + if (cdns_phy->nsubnodes != 1) + return 0; + ret = reset_control_assert(cdns_phy->phy_rst); if (ret) return ret; @@ -1585,7 +1672,24 @@ static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, return devm_regmap_init(dev, NULL, ctx, config); } -static int cdns_regfield_init(struct cdns_torrent_phy *cdns_phy) +static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy) +{ + struct device *dev = cdns_phy->dev; + struct regmap_field *field; + struct regmap *regmap; + + regmap = cdns_phy->regmap_dptx_phy_reg; + field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl); + if (IS_ERR(field)) { + dev_err(dev, "PHY_RESET reg field init failed\n"); + return PTR_ERR(field); + } + cdns_phy->phy_reset_ctrl = field; + + return 0; +} + +static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy) { struct device *dev = cdns_phy->dev; struct regmap_field *field; @@ -1600,6 +1704,14 @@ static int cdns_regfield_init(struct cdns_torrent_phy *cdns_phy) cdns_phy->phy_pll_cfg = field; regmap = cdns_phy->regmap_phy_pma_common_cdb; + field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1); + if (IS_ERR(field)) { + dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n"); + return PTR_ERR(field); + } + cdns_phy->phy_pma_cmn_ctrl_1 = field; + + regmap = cdns_phy->regmap_phy_pma_common_cdb; field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2); if (IS_ERR(field)) { dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n"); @@ -1615,28 +1727,44 @@ static int cdns_regfield_init(struct cdns_torrent_phy *cdns_phy) } cdns_phy->phy_pma_pll_raw_ctrl = field; - regmap = cdns_phy->regmap_dptx_phy_reg; - field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl); - if (IS_ERR(field)) { - dev_err(dev, "PHY_RESET reg field init failed\n"); - return PTR_ERR(field); + return 0; +} + +static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy) +{ + void __iomem *base = cdns_phy->base; + struct device *dev = cdns_phy->dev; + struct regmap *regmap; + u8 reg_offset_shift; + u32 block_offset; + |