diff options
Diffstat (limited to 'drivers/pinctrl')
38 files changed, 4125 insertions, 307 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index b3fe1d339632..0e75d94972ba 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -254,6 +254,7 @@ config PINCTRL_ZYNQ help This selects the pinctrl driver for Xilinx Zynq. +source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" source "drivers/pinctrl/freescale/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 8ebd7b8e1621..11bad373dfe0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o +obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-y += bcm/ obj-$(CONFIG_PINCTRL_BERLIN) += berlin/ obj-y += freescale/ diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig new file mode 100644 index 000000000000..998eabef3a65 --- /dev/null +++ b/drivers/pinctrl/aspeed/Kconfig @@ -0,0 +1,24 @@ +config PINCTRL_ASPEED + bool + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + depends on MFD_SYSCON + select PINMUX + select PINCONF + select GENERIC_PINCONF + select REGMAP_MMIO + +config PINCTRL_ASPEED_G4 + bool "Aspeed G4 SoC pin control" + depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 4th + generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G5 + bool "Aspeed G5 SoC pin control" + depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 5th + generation SoCs. GPIO is provided by a separate GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile new file mode 100644 index 000000000000..191ed0fc1804 --- /dev/null +++ b/drivers/pinctrl/aspeed/Makefile @@ -0,0 +1,6 @@ +# Aspeed pinctrl support + +ccflags-y += -Woverride-init +obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o +obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o +obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c new file mode 100644 index 000000000000..a21b071ff290 --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -0,0 +1,1231 @@ +/* + * Copyright (C) 2016 IBM Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include <linux/bitops.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/string.h> +#include <linux/types.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-aspeed.h" + +/* + * Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK, + * TIMER3 etc. + * + * Pins are defined in GPIO bank order: + * + * GPIOA0: 0 + * ... + * GPIOA7: 7 + * GPIOB0: 8 + * ... + * GPIOZ7: 207 + * GPIOAA0: 208 + * ... + * GPIOAB3: 219 + * + * Not all pins have their signals defined (yet). + */ + +#define A4 2 +SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); + +#define I2C9_DESC SIG_DESC_SET(SCU90, 22) + +#define C5 4 +SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); +MS_PIN_DECL(C5, GPIOA4, SCL9, TIMER5); + +FUNC_GROUP_DECL(TIMER5, C5); + +#define B4 5 +SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); +MS_PIN_DECL(B4, GPIOA5, SDA9, TIMER6); + +FUNC_GROUP_DECL(TIMER6, B4); +FUNC_GROUP_DECL(I2C9, C5, B4); + +#define MDIO2_DESC SIG_DESC_SET(SCU90, 2) + +#define A3 6 +SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); +MS_PIN_DECL(A3, GPIOA6, MDC2, TIMER7); + +FUNC_GROUP_DECL(TIMER7, A3); + +#define D5 7 +SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); +MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8); + +FUNC_GROUP_DECL(TIMER8, D5); +FUNC_GROUP_DECL(MDIO2, A3, D5); + +#define H19 13 +#define H19_DESC SIG_DESC_SET(SCU80, 13) +SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC); +MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI); + +FUNC_GROUP_DECL(LPCPD, H19); +FUNC_GROUP_DECL(LPCSMI, H19); + +#define H20 14 +SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); + +#define SD1_DESC SIG_DESC_SET(SCU90, 0) +#define I2C10_DESC SIG_DESC_SET(SCU90, 23) + +#define C4 16 +SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); +MS_PIN_DECL(C4, GPIOC0, SD1CLK, SCL10); + +#define B3 17 +SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); +MS_PIN_DECL(B3, GPIOC1, SD1CMD, SDA10); + +FUNC_GROUP_DECL(I2C10, C4, B3); + +#define I2C11_DESC SIG_DESC_SET(SCU90, 24) + +#define A2 18 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); +MS_PIN_DECL(A2, GPIOC2, SD1DAT0, SCL11); + +#define E5 19 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); +MS_PIN_DECL(E5, GPIOC3, SD1DAT1, SDA11); + +FUNC_GROUP_DECL(I2C11, A2, E5); + +#define I2C12_DESC SIG_DESC_SET(SCU90, 25) + +#define D4 20 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); +MS_PIN_DECL(D4, GPIOC4, SD1DAT2, SCL12); + +#define C3 21 +SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); +MS_PIN_DECL(C3, GPIOC5, SD1DAT3, SDA12); + +FUNC_GROUP_DECL(I2C12, D4, C3); + +#define I2C13_DESC SIG_DESC_SET(SCU90, 26) + +#define B2 22 +SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); +MS_PIN_DECL(B2, GPIOC6, SD1CD, SCL13); + +#define A1 23 +SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); +MS_PIN_DECL(A1, GPIOC7, SD1WP, SDA13); + +FUNC_GROUP_DECL(I2C13, B2, A1); +FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); + +#define SD2_DESC SIG_DESC_SET(SCU90, 1) +#define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) +#define GPID0_DESC SIG_DESC_SET(SCU8C, 8) + +#define A18 24 +SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); +MS_PIN_DECL(A18, GPIOD0, SD2CLK, GPID0IN); + +#define D16 25 +SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); +MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT); + +FUNC_GROUP_DECL(GPID0, A18, D16); + +#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22) +#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) +#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) +#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) +#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) + +#define D15 32 +SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); +MS_PIN_DECL(D15, GPIOE0, NCTS3, GPIE0IN); + +FUNC_GROUP_DECL(NCTS3, D15); + +#define C15 33 +SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); +SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); +MS_PIN_DECL(C15, GPIOE1, NDCD3, GPIE0OUT); + +FUNC_GROUP_DECL(NDCD3, C15); +FUNC_GROUP_DECL(GPIE0, D15, C15); + +#define B15 34 +SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); +MS_PIN_DECL(B15, GPIOE2, NDSR3, GPIE2IN); + +FUNC_GROUP_DECL(NDSR3, B15); + +#define A15 35 +SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); +MS_PIN_DECL(A15, GPIOE3, NRI3, GPIE2OUT); + +FUNC_GROUP_DECL(NRI3, A15); +FUNC_GROUP_DECL(GPIE2, B15, A15); + +#define E14 36 +SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); +MS_PIN_DECL(E14, GPIOE4, NDTR3, GPIE4IN); + +FUNC_GROUP_DECL(NDTR3, E14); + +#define D14 37 +SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); +MS_PIN_DECL(D14, GPIOE5, NRTS3, GPIE4OUT); + +FUNC_GROUP_DECL(NRTS3, D14); +FUNC_GROUP_DECL(GPIE4, E14, D14); + +#define C14 38 +SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); +MS_PIN_DECL(C14, GPIOE6, TXD3, GPIE6IN); + +FUNC_GROUP_DECL(TXD3, C14); + +#define B14 39 +SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); +MS_PIN_DECL(B14, GPIOE7, RXD3, GPIE6OUT); + +FUNC_GROUP_DECL(RXD3, B14); +FUNC_GROUP_DECL(GPIE6, C14, B14); + +#define D18 40 +SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24)); + +#define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0) + +#define B19 41 +SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +SIG_EXPR_DECL(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL(SIOPBI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); +MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI); +FUNC_GROUP_DECL(NDCD4, B19); +FUNC_GROUP_DECL(SIOPBI, B19); + +#define D17 43 +SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); +SIG_EXPR_DECL(SIOPBO, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); +MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO); +FUNC_GROUP_DECL(NRI4, D17); +FUNC_GROUP_DECL(SIOPBO, D17); + +FUNC_GROUP_DECL(ACPI, B19, D17); + +#define E16 46 +SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); + +#define C17 47 +SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31)); + +#define AA22 54 +SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6)); + +#define U18 55 +SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); + +#define UART6_DESC SIG_DESC_SET(SCU90, 7) +#define ROM16_DESC SIG_DESC_SET(SCU90, 6) +#define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4) +#define BOOT_SRC_NOR { HW_STRAP1, GENMASK(1, 0), 0, 0 } + +#define A8 56 +SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD8, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, UART6_DESC); +MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); + +#define C7 57 +SIG_EXPR_DECL(ROMD9, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD9, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDCD6, NDCD6, UART6_DESC); +MS_PIN_DECL(C7, GPIOH1, ROMD9, NDCD6); + +#define B7 58 +SIG_EXPR_DECL(ROMD10, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD10, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDSR6, NDSR6, UART6_DESC); +MS_PIN_DECL(B7, GPIOH2, ROMD10, NDSR6); + +#define A7 59 +SIG_EXPR_DECL(ROMD11, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD11, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NRI6, NRI6, UART6_DESC); +MS_PIN_DECL(A7, GPIOH3, ROMD11, NRI6); + +#define D7 60 +SIG_EXPR_DECL(ROMD12, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD12, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NDTR6, NDTR6, UART6_DESC); +MS_PIN_DECL(D7, GPIOH4, ROMD12, NDTR6); + +#define B6 61 +SIG_EXPR_DECL(ROMD13, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD13, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(NRTS6, NRTS6, UART6_DESC); +MS_PIN_DECL(B6, GPIOH5, ROMD13, NRTS6); + +#define A6 62 +SIG_EXPR_DECL(ROMD14, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD14, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(TXD6, TXD6, UART6_DESC); +MS_PIN_DECL(A6, GPIOH6, ROMD14, TXD6); + +#define E7 63 +SIG_EXPR_DECL(ROMD15, ROM16, ROM16_DESC); +SIG_EXPR_DECL(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(ROMD15, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(RXD6, RXD6, UART6_DESC); +MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6); + +FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); + +#define J3 75 +SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11)); + +#define T4 76 +SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12)); + +#define U2 77 +SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13)); + +#define T2 78 +SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14)); + +#define T1 79 +SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15)); + +#define I2C5_DESC SIG_DESC_SET(SCU90, 18) + +#define E3 80 +SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); +SS_PIN_DECL(E3, GPIOK0, SCL5); + +#define D2 81 +SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); +SS_PIN_DECL(D2, GPIOK1, SDA5); + +FUNC_GROUP_DECL(I2C5, E3, D2); + +#define I2C6_DESC SIG_DESC_SET(SCU90, 19) + +#define C1 82 +SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); +SS_PIN_DECL(C1, GPIOK2, SCL6); + +#define F4 83 +SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); +SS_PIN_DECL(F4, GPIOK3, SDA6); + +FUNC_GROUP_DECL(I2C6, C1, F4); + +#define I2C7_DESC SIG_DESC_SET(SCU90, 20) + +#define E2 84 +SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); +SS_PIN_DECL(E2, GPIOK4, SCL7); + +#define D1 85 +SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); +SS_PIN_DECL(D1, GPIOK5, SDA7); + +FUNC_GROUP_DECL(I2C7, E2, D1); + +#define I2C8_DESC SIG_DESC_SET(SCU90, 21) + +#define G5 86 +SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); +SS_PIN_DECL(G5, GPIOK6, SCL8); + +#define F3 87 +SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); +SS_PIN_DECL(F3, GPIOK7, SDA8); + +FUNC_GROUP_DECL(I2C8, G5, F3); + +#define U1 88 +SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); + +#define VPI18_DESC { SCU90, GENMASK(5, 4), 1, 0 } +#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 } +#define VPI30_DESC { SCU90, GENMASK(5, 4), 3, 0 } + +#define T5 89 +#define T5_DESC SIG_DESC_SET(SCU84, 17) +SIG_EXPR_DECL(VPIDE, VPI18, VPI18_DESC, T5_DESC); +SIG_EXPR_DECL(VPIDE, VPI24, VPI24_DESC, T5_DESC); +SIG_EXPR_DECL(VPIDE, VPI30, VPI30_DESC, T5_DESC); +SIG_EXPR_LIST_DECL(VPIDE, SIG_EXPR_PTR(VPIDE, VPI18), + SIG_EXPR_PTR(VPIDE, VPI24), + SIG_EXPR_PTR(VPIDE, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T5_DESC); +MS_PIN_DECL(T5, GPIOL1, VPIDE, NDCD1); +FUNC_GROUP_DECL(NDCD1, T5); + +#define U3 90 +#define U3_DESC SIG_DESC_SET(SCU84, 18) +SIG_EXPR_DECL(VPIODD, VPI18, VPI18_DESC, U3_DESC); +SIG_EXPR_DECL(VPIODD, VPI24, VPI24_DESC, U3_DESC); +SIG_EXPR_DECL(VPIODD, VPI30, VPI30_DESC, U3_DESC); +SIG_EXPR_LIST_DECL(VPIODD, SIG_EXPR_PTR(VPIODD, VPI18), + SIG_EXPR_PTR(VPIODD, VPI24), + SIG_EXPR_PTR(VPIODD, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U3_DESC); +MS_PIN_DECL(U3, GPIOL2, VPIODD, NDSR1); +FUNC_GROUP_DECL(NDSR1, U3); + +#define V1 91 +#define V1_DESC SIG_DESC_SET(SCU84, 19) +SIG_EXPR_DECL(VPIHS, VPI18, VPI18_DESC, V1_DESC); +SIG_EXPR_DECL(VPIHS, VPI24, VPI24_DESC, V1_DESC); +SIG_EXPR_DECL(VPIHS, VPI30, VPI30_DESC, V1_DESC); +SIG_EXPR_LIST_DECL(VPIHS, SIG_EXPR_PTR(VPIHS, VPI18), + SIG_EXPR_PTR(VPIHS, VPI24), + SIG_EXPR_PTR(VPIHS, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, V1_DESC); +MS_PIN_DECL(V1, GPIOL3, VPIHS, NRI1); +FUNC_GROUP_DECL(NRI1, V1); + +#define U4 92 +#define U4_DESC SIG_DESC_SET(SCU84, 20) +SIG_EXPR_DECL(VPIVS, VPI18, VPI18_DESC, U4_DESC); +SIG_EXPR_DECL(VPIVS, VPI24, VPI24_DESC, U4_DESC); +SIG_EXPR_DECL(VPIVS, VPI30, VPI30_DESC, U4_DESC); +SIG_EXPR_LIST_DECL(VPIVS, SIG_EXPR_PTR(VPIVS, VPI18), + SIG_EXPR_PTR(VPIVS, VPI24), + SIG_EXPR_PTR(VPIVS, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, U4_DESC); +MS_PIN_DECL(U4, GPIOL4, VPIVS, NDTR1); +FUNC_GROUP_DECL(NDTR1, U4); + +#define V2 93 +#define V2_DESC SIG_DESC_SET(SCU84, 21) +SIG_EXPR_DECL(VPICLK, VPI18, VPI18_DESC, V2_DESC); +SIG_EXPR_DECL(VPICLK, VPI24, VPI24_DESC, V2_DESC); +SIG_EXPR_DECL(VPICLK, VPI30, VPI30_DESC, V2_DESC); +SIG_EXPR_LIST_DECL(VPICLK, SIG_EXPR_PTR(VPICLK, VPI18), + SIG_EXPR_PTR(VPICLK, VPI24), + SIG_EXPR_PTR(VPICLK, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, V2_DESC); +MS_PIN_DECL(V2, GPIOL5, VPICLK, NRTS1); +FUNC_GROUP_DECL(NRTS1, V2); + +#define W1 94 +#define W1_DESC SIG_DESC_SET(SCU84, 22) +SIG_EXPR_LIST_DECL_SINGLE(VPIB0, VPI30, VPI30_DESC, W1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, W1_DESC); +MS_PIN_DECL(W1, GPIOL6, VPIB0, TXD1); +FUNC_GROUP_DECL(TXD1, W1); + +#define U5 95 +#define U5_DESC SIG_DESC_SET(SCU84, 23) +SIG_EXPR_LIST_DECL_SINGLE(VPIB1, VPI30, VPI30_DESC, U5_DESC); +SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC); +MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1); +FUNC_GROUP_DECL(RXD1, U5); + +#define W4 104 +#define W4_DESC SIG_DESC_SET(SCU88, 0) +SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, W4_DESC); +MS_PIN_DECL(W4, GPION0, VPIG0, PWM0); +FUNC_GROUP_DECL(PWM0, W4); + +#define Y3 105 +#define Y3_DESC SIG_DESC_SET(SCU88, 1) +SIG_EXPR_LIST_DECL_SINGLE(VPIG1, VPI30, VPI30_DESC, Y3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, Y3_DESC); +MS_PIN_DECL(Y3, GPION1, VPIG1, PWM1); +FUNC_GROUP_DECL(PWM1, Y3); + +#define AA2 106 +#define AA2_DESC SIG_DESC_SET(SCU88, 2) +SIG_EXPR_DECL(VPIG2, VPI18, VPI18_DESC, AA2_DESC); +SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, AA2_DESC); +SIG_EXPR_DECL(VPIG2, VPI30, VPI30_DESC, AA2_DESC); +SIG_EXPR_LIST_DECL(VPIG2, SIG_EXPR_PTR(VPIG2, VPI18), + SIG_EXPR_PTR(VPIG2, VPI24), + SIG_EXPR_PTR(VPIG2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, AA2_DESC); +MS_PIN_DECL(AA2, GPION2, VPIG2, PWM2); +FUNC_GROUP_DECL(PWM2, AA2); + +#define AB1 107 +#define AB1_DESC SIG_DESC_SET(SCU88, 3) +SIG_EXPR_DECL(VPIG3, VPI18, VPI18_DESC, AB1_DESC); +SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, AB1_DESC); +SIG_EXPR_DECL(VPIG3, VPI30, VPI30_DESC, AB1_DESC); +SIG_EXPR_LIST_DECL(VPIG3, SIG_EXPR_PTR(VPIG3, VPI18), + SIG_EXPR_PTR(VPIG2, VPI24), + SIG_EXPR_PTR(VPIG2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, AB1_DESC); +MS_PIN_DECL(AB1, GPION3, VPIG3, PWM3); +FUNC_GROUP_DECL(PWM3, AB1); + +#define W5 108 +#define W5_DESC SIG_DESC_SET(SCU88, 4) +SIG_EXPR_DECL(VPIG4, VPI18, VPI18_DESC, W5_DESC); +SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W5_DESC); +SIG_EXPR_DECL(VPIG4, VPI30, VPI30_DESC, W5_DESC); +SIG_EXPR_LIST_DECL(VPIG4, SIG_EXPR_PTR(VPIG4, VPI18), + SIG_EXPR_PTR(VPIG2, VPI24), + SIG_EXPR_PTR(VPIG2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W5_DESC); +MS_PIN_DECL(W5, GPION4, VPIG4, PWM4); +FUNC_GROUP_DECL(PWM4, W5); + +#define Y4 109 +#define Y4_DESC SIG_DESC_SET(SCU88, 5) +SIG_EXPR_DECL(VPIG5, VPI18, VPI18_DESC, Y4_DESC); +SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, Y4_DESC); +SIG_EXPR_DECL(VPIG5, VPI30, VPI30_DESC, Y4_DESC); +SIG_EXPR_LIST_DECL(VPIG5, SIG_EXPR_PTR(VPIG5, VPI18), + SIG_EXPR_PTR(VPIG2, VPI24), + SIG_EXPR_PTR(VPIG2, VPI30)); +SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, Y4_DESC); +MS_PIN_DECL(Y4, GPION5, VPIG5, PWM5); +FUNC_GROUP_DECL(PWM5, Y4); + +#define AA3 110 +#define AA3_DESC SIG_DESC_SET(SCU88, 6) +SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI30, VPI30_DESC, AA3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, AA3_DESC); +MS_PIN_DECL(AA3, GPION6, VPIG6, PWM6); +FUNC_GROUP_DECL(PWM6, AA3); + +#define AB2 111 +#define AB2_DESC SIG_DESC_SET(SCU88, 7) +SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI30, VPI30_DESC, AB2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, AB2_DESC); +MS_PIN_DECL(AB2, GPION7, VPIG7, PWM7); +FUNC_GROUP_DECL(PWM7, AB2); + +#define V6 112 +SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8)); +SS_PIN_DECL(V6, GPIOO0, VPIG8); + +#define Y5 113 +SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); +SS_PIN_DECL(Y5, GPIOO1, VPIG9); + +FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2); +FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2, V6, Y5); +FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA22, W5, Y4, AA3, + AB2); + +#define Y7 125 +SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5); +MS_PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(GPIOP5)); + +#define AA7 126 +SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22)); + +#define AB7 127 +SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23)); + +#define I2C3_DESC SIG_DESC_SET(SCU90, 16) + +#define D3 128 +SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); +SS_PIN_DECL(D3, GPIOQ0, SCL3); + +#define C2 129 +SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); +SS_PIN_DECL(C2, GPIOQ1, SDA3); + +FUNC_GROUP_DECL(I2C3, D3, C2); + +#define I2C4_DESC SIG_DESC_SET(SCU90, 17) + +#define B1 130 +SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); +SS_PIN_DECL(B1, GPIOQ2, SCL4); + +#define F5 131 +SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); +SS_PIN_DECL(F5, GPIOQ3, SDA4); + +FUNC_GROUP_DECL(I2C4, B1, F5); + +#define DASH9028_DESC SIG_DESC_SET(SCU90, 28) + +#define H2 134 +SIG_EXPR_LIST_DECL_SINGLE(DASHH2, DASHH2, DASH9028_DESC); +SS_PIN_DECL(H2, GPIOQ6, DASHH2); + +#define H1 135 +SIG_EXPR_LIST_DECL_SINGLE(DASHH1, DASHH1, DASH9028_DESC); +SS_PIN_DECL(H1, GPIOQ7, DASHH1); + +#define V20 136 +SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24)); + +#define W21 137 +SSSF_PIN_DECL(W21, GPIOR1, ROMCS2, SIG_DESC_SET(SCU88, 25)); + +#define Y22 138 +SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26)); + +#define U19 139 +SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); + +#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 } +#define VPO12_DESC { SCU94, GENMASK(1, 0), 1, 0 } +#define VPO24_DESC { SCU94, GENMASK(1, 0), 2, 0 } +#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 3, 0 } +#define VPO_OFF_12 { SCU94, 0x2, 0, 0 } +#define VPO_24_OFF SIG_DESC_SET(SCU94, 1) + +#define V21 140 +#define V21_DESC SIG_DESC_SET(SCU88, 28) +SIG_EXPR_DECL(ROMA24, ROM8, V21_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA24, ROM16, V21_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA24, ROM16S, V21_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA24, SIG_EXPR_PTR(ROMA24, ROM8), + SIG_EXPR_PTR(ROMA24, ROM16), + SIG_EXPR_PTR(ROMA24, ROM16S)); +SIG_EXPR_LIST_DECL_SINGLE(VPOR6, VPO24, V21_DESC, VPO_24_OFF); +MS_PIN_DECL(V21, GPIOR4, ROMA24, VPOR6); + +#define W22 141 +#define W22_DESC SIG_DESC_SET(SCU88, 29) +SIG_EXPR_DECL(ROMA25, ROM8, W22_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA25, ROM16, W22_DESC, VPO_OFF_12); +SIG_EXPR_DECL(ROMA25, ROM16S, W22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA25, SIG_EXPR_PTR(ROMA25, ROM8), + SIG_EXPR_PTR(ROMA25, ROM16), + SIG_EXPR_PTR(ROMA25, ROM16S)); +SI |