diff options
Diffstat (limited to 'drivers')
45 files changed, 19696 insertions, 302 deletions
diff --git a/drivers/clk/clk-renesas-pcie.c b/drivers/clk/clk-renesas-pcie.c index 380245f635d6..6606aba253c5 100644 --- a/drivers/clk/clk-renesas-pcie.c +++ b/drivers/clk/clk-renesas-pcie.c @@ -163,7 +163,7 @@ static u8 rs9_calc_dif(const struct rs9_driver_data *rs9, int idx) enum rs9_model model = rs9->chip_info->model; if (model == RENESAS_9FGV0241) - return BIT(idx) + 1; + return BIT(idx + 1); else if (model == RENESAS_9FGV0441) return BIT(idx); diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c index 845b451511d2..6e8dd7387cfd 100644 --- a/drivers/clk/clk-si5341.c +++ b/drivers/clk/clk-si5341.c @@ -895,10 +895,8 @@ static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate, r[0] = r_div ? (r_div & 0xff) : 1; r[1] = (r_div >> 8) & 0xff; r[2] = (r_div >> 16) & 0xff; - err = regmap_bulk_write(output->data->regmap, + return regmap_bulk_write(output->data->regmap, SI5341_OUT_R_REG(output), r, 3); - - return 0; } static int si5341_output_reparent(struct clk_si5341_output *output, u8 index) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index a9a0bc448a4b..4ce83c5265b8 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -506,6 +506,8 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, { struct si5351_hw_data *hwdata = container_of(hw, struct si5351_hw_data, hw); + struct si5351_platform_data *pdata = + hwdata->drvdata->client->dev.platform_data; u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : SI5351_PLLB_PARAMETERS; @@ -518,9 +520,10 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); /* Do a pll soft reset on the affected pll */ - si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, - hwdata->num == 0 ? SI5351_PLL_RESET_A : - SI5351_PLL_RESET_B); + if (pdata->pll_reset[hwdata->num]) + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + hwdata->num == 0 ? SI5351_PLL_RESET_A : + SI5351_PLL_RESET_B); dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", @@ -1222,6 +1225,44 @@ static int si5351_dt_parse(struct i2c_client *client, } } + /* + * Parse PLL reset mode. For compatibility with older device trees, the + * default is to always reset a PLL after setting its rate. + */ + pdata->pll_reset[0] = true; + pdata->pll_reset[1] = true; + + of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) { + if (num >= 2) { + dev_err(&client->dev, + "invalid pll %d on pll-reset-mode prop\n", num); + return -EINVAL; + } + + p = of_prop_next_u32(prop, p, &val); + if (!p) { + dev_err(&client->dev, + "missing pll-reset-mode for pll %d\n", num); + return -EINVAL; + } + + switch (val) { + case 0: + /* Reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = true; + break; + case 1: + /* Don't reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = false; + break; + default: + dev_err(&client->dev, + "invalid pll-reset-mode %d for pll %d\n", val, + num); + return -EINVAL; + } + } + /* per clkout properties */ for_each_child_of_node(np, child) { if (of_property_read_u32(child, "reg", &num)) { diff --git a/drivers/clk/clk-sp7021.c b/drivers/clk/clk-sp7021.c index 01d3c4c7b0b2..7cb7d501d7a6 100644 --- a/drivers/clk/clk-sp7021.c +++ b/drivers/clk/clk-sp7021.c @@ -604,14 +604,14 @@ static int sp7021_clk_probe(struct platform_device *pdev) int i; clk_base = devm_platform_ioremap_resource(pdev, 0); - if (!clk_base) - return -ENXIO; + if (IS_ERR(clk_base)) + return PTR_ERR(clk_base); pll_base = devm_platform_ioremap_resource(pdev, 1); - if (!pll_base) - return -ENXIO; + if (IS_ERR(pll_base)) + return PTR_ERR(pll_base); sys_base = devm_platform_ioremap_resource(pdev, 2); - if (!sys_base) - return -ENXIO; + if (IS_ERR(sys_base)) + return PTR_ERR(sys_base); /* enable default clks */ for (i = 0; i < ARRAY_SIZE(sp_clken); i++) diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index 00930d7bca77..76d7ea1964c3 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -37,7 +37,7 @@ #define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0)) #define VC3_PLL1_VCO_N_DIVIDER 0x9 -#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0x0a +#define VC3_PLL1_LOOP_FILTER_N_DIV_MSB 0xa #define VC3_OUT_DIV1_DIV2_CTRL 0xf @@ -148,16 +148,16 @@ struct vc3_pfd_data { }; struct vc3_pll_data { + unsigned long vco_min; + unsigned long vco_max; u8 num; u8 int_div_msb_offs; u8 int_div_lsb_offs; - unsigned long vco_min; - unsigned long vco_max; }; struct vc3_div_data { - u8 offs; const struct clk_div_table *table; + u8 offs; u8 shift; u8 width; u8 flags; @@ -210,7 +210,7 @@ static const struct clk_div_table div3_divs[] = { static struct clk_hw *clk_out[6]; -static unsigned char vc3_pfd_mux_get_parent(struct clk_hw *hw) +static u8 vc3_pfd_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *pfd_mux = vc3->data; @@ -226,9 +226,8 @@ static int vc3_pfd_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *pfd_mux = vc3->data; - regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, - index ? pfd_mux->bitmsk : 0); - return 0; + return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, + index ? pfd_mux->bitmsk : 0); } static const struct clk_ops vc3_pfd_mux_ops = { @@ -440,7 +439,7 @@ static const struct clk_ops vc3_pll_ops = { .set_rate = vc3_pll_set_rate, }; -static unsigned char vc3_div_mux_get_parent(struct clk_hw *hw) +static u8 vc3_div_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *div_mux = vc3->data; @@ -456,10 +455,8 @@ static int vc3_div_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *div_mux = vc3->data; - regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, - index ? div_mux->bitmsk : 0); - - return 0; + return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, + index ? div_mux->bitmsk : 0); } static const struct clk_ops vc3_div_mux_ops = { @@ -477,7 +474,7 @@ static unsigned int vc3_get_div(const struct clk_div_table *table, if (clkt->val == val) return clkt->div; - return 0; + return 1; } static unsigned long vc3_div_recalc_rate(struct clk_hw *hw, @@ -524,10 +521,9 @@ static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate, value = divider_get_val(rate, parent_rate, div_data->table, div_data->width, div_data->flags); - regmap_update_bits(vc3->regmap, div_data->offs, - VC3_DIV_MASK(div_data->width) << div_data->shift, - value << div_data->shift); - return 0; + return regmap_update_bits(vc3->regmap, div_data->offs, + VC3_DIV_MASK(div_data->width) << div_data->shift, + value << div_data->shift); } static const struct clk_ops vc3_div_ops = { @@ -539,11 +535,9 @@ static const struct clk_ops vc3_div_ops = { static int vc3_clk_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - int ret; int frc; - ret = clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT); - if (ret) { + if (clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT)) { /* The below check is equivalent to (best_parent_rate/rate) */ if (req->best_parent_rate >= req->rate) { frc = DIV_ROUND_CLOSEST_ULL(req->best_parent_rate, @@ -552,13 +546,12 @@ static int vc3_clk_mux_determine_rate(struct clk_hw *hw, return clk_mux_determine_rate_flags(hw, req, CLK_SET_RATE_PARENT); } - ret = 0; } - return ret; + return 0; } -static unsigned char vc3_clk_mux_get_parent(struct clk_hw *hw) +static u8 vc3_clk_mux_get_parent(struct clk_hw *hw) { struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *clk_mux = vc3->data; @@ -574,9 +567,8 @@ static int vc3_clk_mux_set_parent(struct clk_hw *hw, u8 index) struct vc3_hw_data *vc3 = container_of(hw, struct vc3_hw_data, hw); const struct vc3_clk_data *clk_mux = vc3->data; - regmap_update_bits(vc3->regmap, clk_mux->offs, - clk_mux->bitmsk, index ? clk_mux->bitmsk : 0); - return 0; + return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk, + index ? clk_mux->bitmsk : 0); } static const struct clk_ops vc3_clk_mux_ops = { @@ -605,7 +597,7 @@ static struct vc3_hw_data clk_pfd_mux[] = { .offs = VC3_PLL_OP_CTRL, .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL) }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd2_mux", .ops = &vc3_pfd_mux_ops, .parent_data = pfd_mux_parent_data, @@ -618,7 +610,7 @@ static struct vc3_hw_data clk_pfd_mux[] = { .offs = VC3_GENERAL_CTR, .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL) }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd3_mux", .ops = &vc3_pfd_mux_ops, .parent_data = pfd_mux_parent_data, @@ -636,7 +628,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL1_M_DIV1, .mdiv2_bitmsk = VC3_PLL1_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd1", .ops = &vc3_pfd_ops, .parent_data = &(const struct clk_parent_data) { @@ -653,7 +645,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL2_M_DIV1, .mdiv2_bitmsk = VC3_PLL2_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd2", .ops = &vc3_pfd_ops, .parent_hws = (const struct clk_hw *[]) { @@ -670,7 +662,7 @@ static struct vc3_hw_data clk_pfd[] = { .mdiv1_bitmsk = VC3_PLL3_M_DIV1, .mdiv2_bitmsk = VC3_PLL3_M_DIV2 }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pfd3", .ops = &vc3_pfd_ops, .parent_hws = (const struct clk_hw *[]) { @@ -691,7 +683,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL1_VCO_MIN, .vco_max = VC3_PLL1_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll1", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -709,7 +701,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL2_VCO_MIN, .vco_max = VC3_PLL2_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll2", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -727,7 +719,7 @@ static struct vc3_hw_data clk_pll[] = { .vco_min = VC3_PLL3_VCO_MIN, .vco_max = VC3_PLL3_VCO_MAX }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "pll3", .ops = &vc3_pll_ops, .parent_hws = (const struct clk_hw *[]) { @@ -760,7 +752,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_GENERAL_CTR, .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div1_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV1_MUX], @@ -773,7 +765,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_PLL3_CHARGE_PUMP_CTRL, .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div3_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV3_MUX], @@ -786,7 +778,7 @@ static struct vc3_hw_data clk_div_mux[] = { .offs = VC3_OUTPUT_CTR, .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div4_mux", .ops = &vc3_div_mux_ops, .parent_data = div_mux_parent_data[VC3_DIV4_MUX], @@ -805,7 +797,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div1", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -823,7 +815,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div2", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -841,7 +833,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div3", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -859,7 +851,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div4", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -877,7 +869,7 @@ static struct vc3_hw_data clk_div[] = { .width = 4, .flags = CLK_DIVIDER_READ_ONLY }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "div5", .ops = &vc3_div_ops, .parent_hws = (const struct clk_hw *[]) { @@ -895,7 +887,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE1_DIV4_CTRL, .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se1_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -911,7 +903,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE2_CTRL_REG0, .bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se2_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -927,7 +919,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_SE3_DIFF1_CTRL_REG, .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "se3_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -943,7 +935,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_DIFF1_CTRL_REG, .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "diff1_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { @@ -959,7 +951,7 @@ static struct vc3_hw_data clk_mux[] = { .offs = VC3_DIFF2_CTRL_REG, .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL }, - .hw.init = &(struct clk_init_data){ + .hw.init = &(struct clk_init_data) { .name = "diff2_mux", .ops = &vc3_clk_mux_ops, .parent_hws = (const struct clk_hw *[]) { diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c index 2d7186905abd..5d0226530fdb 100644 --- a/drivers/clk/hisilicon/clk-hi3620.c +++ b/drivers/clk/hisilicon/clk-hi3620.c @@ -466,8 +466,10 @@ static void __init hi3620_mmc_clk_init(struct device_node *node) return; clk_data->clks = kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL); - if (!clk_data->clks) + if (!clk_data->clks) { + kfree(clk_data); return; + } for (i = 0; i < num; i++) { struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i]; diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index 41f0a45aa162..7d8883916cac 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -66,6 +66,22 @@ static const char * const lcd_pxl_sels[] = { "lcd_pxl_bypass_div_clk", }; +static const char *const lvds0_sels[] = { + "clk_dummy", + "clk_dummy", + "clk_dummy", + "clk_dummy", + "mipi0_lvds_bypass_clk", +}; + +static const char *const lvds1_sels[] = { + "clk_dummy", + "clk_dummy", + "clk_dummy", + "clk_dummy", + "mipi1_lvds_bypass_clk", +}; + static const char * const mipi_sels[] = { "clk_dummy", "clk_dummy", @@ -207,9 +223,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) /* MIPI-LVDS SS */ imx_clk_scu("mipi0_bypass_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("mipi0_pixel_clk", IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PER); - imx_clk_scu("mipi0_lvds_pixel_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi0_lvds_bypass_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu("mipi0_lvds_phy_clk", IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); + imx_clk_scu2("mipi0_lvds_pixel_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("mipi0_lvds_phy_clk", lvds0_sels, ARRAY_SIZE(lvds0_sels), IMX_SC_R_LVDS_0, IMX_SC_PM_CLK_MISC3); imx_clk_scu2("mipi0_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu2("mipi0_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_SLV_BUS); imx_clk_scu2("mipi0_dsi_phy_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_0, IMX_SC_PM_CLK_PHY); @@ -219,9 +235,9 @@ static int imx8qxp_clk_probe(struct platform_device *pdev) imx_clk_scu("mipi1_bypass_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_BYPASS); imx_clk_scu("mipi1_pixel_clk", IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_PER); - imx_clk_scu("mipi1_lvds_pixel_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); imx_clk_scu("mipi1_lvds_bypass_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_BYPASS); - imx_clk_scu("mipi1_lvds_phy_clk", IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); + imx_clk_scu2("mipi1_lvds_pixel_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC2); + imx_clk_scu2("mipi1_lvds_phy_clk", lvds1_sels, ARRAY_SIZE(lvds1_sels), IMX_SC_R_LVDS_1, IMX_SC_PM_CLK_MISC3); imx_clk_scu2("mipi1_dsi_tx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_MST_BUS); imx_clk_scu2("mipi1_dsi_rx_esc_clk", mipi_sels, ARRAY_SIZE(mipi_sels), IMX_SC_R_MIPI_1, IMX_SC_PM_CLK_SLV_BUS); diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 0d58d85c375e..d63564dbb12c 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -104,15 +104,15 @@ static const struct imx_pll14xx_rate_table *imx_get_pll_settings( static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, int sdiv, int kdiv, unsigned long prate) { - u64 fvco = prate; + u64 fout = prate; - /* fvco = (m * 65536 + k) * Fin / (p * 65536) */ - fvco *= (mdiv * 65536 + kdiv); + /* fout = (m * 65536 + k) * Fin / (p * 65536) / (1 << sdiv) */ + fout *= (mdiv * 65536 + kdiv); pdiv *= 65536; - do_div(fvco, pdiv << sdiv); + do_div(fout, pdiv << sdiv); - return fvco; + return fout; } static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, @@ -131,7 +131,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat { u32 pll_div_ctl0, pll_div_ctl1; int mdiv, pdiv, sdiv, kdiv; - long fvco, rate_min, rate_max, dist, best = LONG_MAX; + long fout, rate_min, rate_max, dist, best = LONG_MAX; const struct imx_pll14xx_rate_table *tt; /* @@ -143,6 +143,7 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat * d) -32768 <= k <= 32767 * * fvco = (m * 65536 + k) * prate / (p * 65536) + * fout = (m * 65536 + k) * prate / (p * 65536) / (1 << sdiv) */ /* First try if we can get the desired rate from one of the static entries */ @@ -173,8 +174,8 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n", clk_hw_get_name(&pll->hw), prate, rate, FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv); - fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate); - t->rate = (unsigned int)fvco; + fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate); + t->rate = (unsigned int)fout; t->mdiv = mdiv; t->pdiv = pdiv; t->sdiv = sdiv; @@ -190,13 +191,13 @@ static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rat mdiv = clamp(mdiv, 64, 1023); kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate); - fvco = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate); + fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate); /* best match */ - dist = abs((long)rate - (long)fvco); + dist = abs((long)rate - (long)fout); if (dist < best) { best = dist; - t->rate = (unsigned int)fvco; + t->rate = (unsigned int)fout; t->mdiv = mdiv; t->pdiv = pdiv; t->sdiv = sdiv; diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c index be89180dd19c..e48a904c0013 100644 --- a/drivers/clk/imx/clk-scu.c +++ b/drivers/clk/imx/clk-scu.c @@ -886,8 +886,10 @@ struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_na return ERR_PTR(-EINVAL); } - if (!imx_clk_is_resource_owned(rsrc_id)) + if (!imx_clk_is_resource_owned(rsrc_id)) { + kfree(clk_node); return NULL; + } clk = kzalloc(sizeof(*clk), GFP_KERNEL); if (!clk) { diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index f373a8d48b1d..90f4c6103014 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -3549,6 +3549,22 @@ static struct clk_regmap g12a_cts_encp_sel = { }, }; +static struct clk_regmap g12a_cts_encl_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_VIID_CLK_DIV, + .mask = 0xf, + .shift = 12, + .table = mux_table_cts_sel, + }, + .hw.init = &(struct clk_init_data){ + .name = "cts_encl_sel", + .ops = &clk_regmap_mux_ops, + .parent_hws = g12a_cts_parent_hws, + .num_parents = ARRAY_SIZE(g12a_cts_parent_hws |