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2024-04-02arm64: dts: marvell: cn9130-db: drop wrong unit-addressesKrzysztof Kozlowski1-3/+3
Top-level nodes, not being on MMIO bus, do not have "reg" properties and should not have unit addresses. Correct their name as well to match "Generic node names" recommendation from Devicetree specification. This also fixes dtc W=1 warnings: cn9130-db.dtsi:28.11-31.4: Warning (unique_unit_address_if_enabled): /memory@0: duplicate unit-address (also used in node /ap0_sd_vccq@0) cn9130-db.dtsi:28.11-31.4: Warning (unique_unit_address_if_enabled): /memory@0: duplicate unit-address (also used in node /cp0_usb3_vbus@0) cn9130-db.dtsi:33.33-40.4: Warning (unique_unit_address_if_enabled): /ap0_sd_vccq@0: duplicate unit-address (also used in node /cp0_usb3_vbus@0) cn9130-db.dtsi:28.11-31.4: Warning (unique_unit_address_if_enabled): /memory@0: duplicate unit-address (also used in node /cp0_usb3_phy@0) cn9130-db.dtsi:33.33-40.4: Warning (unit_address_vs_reg): /ap0_sd_vccq@0: node has a unit name, but no reg or ranges property cn9130-db.dtsi:42.38-49.4: Warning (unit_address_vs_reg): /cp0_usb3_vbus@0: node has a unit name, but no reg or ranges property cn9130-db.dtsi:51.34-54.4: Warning (unit_address_vs_reg): /cp0_usb3_phy@0: node has a unit name, but no reg or ranges property cn9130-db.dtsi:56.38-63.4: Warning (unit_address_vs_reg): /cp0_usb3_vbus@1: node has a unit name, but no reg or ranges property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2024-04-02arm64: dts: marvell: cn9131-db: drop unneeded flash address/size-cellsKrzysztof Kozlowski1-2/+0
Flash node uses single "partition" node to describe partitions, so remove deprecated address/size-cells properties to also fix dtc W=1 warnings: cn9131-db.dtsi:140.10-163.4: Warning (avoid_unnecessary_addr_size): /cp1/config-space@f4000000/spi@700680/flash@0: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2022-07-12arch: arm64: dts: marvell: rename the sfp GPIO propertiesIoana Ciornei1-4/+4
Rename the GPIO related sfp properties to include the preffered -gpios suffix. Also, with this change the dtb_check will no longer complain when trying to verify the DTS against the sff,sfp.yaml binding. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-04-26arm64: dts: marvell: align SPI NOR node name with dtschemaKrzysztof Kozlowski1-1/+1
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220407143234.295426-2-krzysztof.kozlowski@linaro.org
2021-07-23arch/arm64: dts: change 10gbase-kr to 10gbase-r in ArmadaKonstantin Porotchkin1-1/+1
Change all 10G port modes in Armada family device trees from 10gbase-kr to 10gbase-r Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-07-23dts: marvell: Enable 10G interfaces on 9130-DB and 9131-DB boardsStefan Chulski1-1/+1
This patch enables eth0 10G interface on CN9130-DB paltforms and eth0 10G and eth3 10G interfaces on CN9131-DB. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2021-07-23arm64: dts: cn913x: add device trees for topology B boardsKonstantin Porotchkin1-0/+206
The CN913x DB with topology B is similar to a regular setup (A) boards, but uses NAND flash as a boot device, while topology A boards are booting from SPI flash. Since NAND and SPI on CN913x DB boards share some wires, they cannot be activated simultaneously. The DTS files for setup "B" are based on setup "A", in which the CP0 NAND controller enabled and CP0 SPI1 disabled. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>