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2021-12-16arm64: tegra: Adjust length of CCPLEX cluster MMIO regionThierry Reding1-1/+1
The Tegra186 CCPLEX cluster register region is 4 MiB is length, not 4 MiB - 1. This was likely presumed to be the "limit" rather than length. Fix it up. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix Tegra186 compatible string listThierry Reding1-9/+9
The I2C controller found on Tegra186 is not fully compatible with the Tegra210 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename power-monitor input nodesThierry Reding3-16/+16
Child nodes of the TI INA3221 power monitor device tree node should be called input@* according to the DT schema. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename thermal zones nodesThierry Reding8-55/+49
The DT schema requires that nodes representing thermal zones include a "-thermal" suffix in their name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Sort Tegra132 XUSB clocks correctlyThierry Reding1-2/+2
Make the order of the clocks and clock-names properties match the order in the device tree bindings. This isn't strictly necessary from a point of view of the operating system because matching will be done based on the clock-names, but it makes it easier to validate the device trees against the DT schema. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Drop unused AHCI clocks on Tegra132Thierry Reding1-4/+2
The CML1 and PLL_E clocks are never explicitly used by the AHCI controller found on Tegra132, so drop them from the corresponding device tree node. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix Tegra132 I2C compatible string listThierry Reding1-6/+6
The I2C controller found on Tegra124 is not fully compatible with the Tegra114 version, so drop the fallback compatible string from the list. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add OPP tables on Tegra132Thierry Reding2-1/+438
Add peripheral OPP tables on Tegra132 and wire them up to ACTMON and the EMC. While at it, add the missing "#interconnect-cells" properties to the memory controller and external memory controller nodes. Also set the "#reset-cells" property for the memory controller because it exports the hotflush reset controls. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix compatible string for Tegra132 timerThierry Reding1-1/+1
The TKE (time-keeping engine) found on Tegra132 is not backwards compatible with the version found on Tegra20, so update the compatible string list accordingly. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Remove unsupported properties on NorrinThierry Reding1-2/+0
The Tegra PMC device tree bindings don't support the "#wake-cells" and "nvidia,reset-gpio" properties, so remove them. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fix unit-addresses on NorrinThierry Reding1-3/+3
The AS3722 pinmux device tree node doesn't have a "reg" property and therefore must not have a unit-address, so drop it. While at it, add missing unit-addresses for the charger and smart battery IC's on the ChromeOS embedded controller's I2C tunnel bus. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add native timer support on Tegra186Thierry Reding1-0/+16
The native timers IP block found on NVIDIA Tegra SoCs implements a watchdog timer that can be used to recover from system hangs. Add the device tree node on Tegra186. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename top-level regulatorsThierry Reding12-86/+86
Regulators defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the regulator to the node name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Rename top-level clocksThierry Reding6-6/+6
Clocks defined at the top level in device tree are no longer part of a simple bus and therefore don't have a reg property. Nodes without a reg property shouldn't have a unit-address either, so drop the unit address from the node names. To ensure nodes aren't duplicated (in which case they would end up merged in the final DTB), append the name of the clock to the node name. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add ISO SMMU controller for Tegra194Jon Hunter1-0/+76
The display controllers are attached to a separate ARM SMMU instance that is dedicated to servicing isochronous memory clients. Add this ISO instance of the ARM SMMU to device tree. Please note that the display controllers are not hooked up to this SMMU yet, because we are still missing a means to transition framebuffers used by the bootloader to the kernel. This based upon an initial patch by Thierry Reding <treding@nvidia.com>. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194Jon Hunter2-0/+84
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on Tegra186 and Tegra194. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add support to enumerate SD in UHS modePrathamesh Shete1-0/+34
Add support to enumerate SD in UHS mode on Tegra194. Add required device-tree properties in SDMMC1 and SDMMC3 instances to enable dynamic pad voltage switching and enumerate SD card in UHS-I modes. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add NVIDIA Jetson AGX Orin Developer Kit supportMikko Perttunen4-0/+55
The Jetson AGX Orin Developer Kit is a continuation of the Jetson Developer Kit line using the new NVIDIA Tegra234 (Orin) SoC. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Describe Tegra234 CPU hierarchyThierry Reding1-2/+363
The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each, for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches with each cluster having an additional 256 KiB unified L2 cache and a 2 MiB L3 cache. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add main and AON GPIO controllers on Tegra234Thierry Reding1-0/+74
These two controllers expose general purpose I/O pins that can be used to control or monitor a variety of signals. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add Tegra234 TCU deviceMikko Perttunen1-0/+8
Add a device for TCU (Tegra Combined UART) used for serial console. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fill in properties for Tegra234 eMMCMikko Perttunen1-3/+16
Add missing properties to the eMMC controller, as required to use it on actual hardware. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Update Tegra234 BPMP channel addressesMikko Perttunen1-6/+6
On final Tegra234 systems, shared memory for communication with BPMP is located at offset 0x70000 in SYSRAM. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Add clock for Tegra234 RTCMikko Perttunen1-0/+2
The RTC device requires a clock. Add it. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-12-16arm64: tegra: Fixup SYSRAM referencesThierry Reding3-6/+6
The json-schema bindings for SRAM expect the nodes to be called "sram" rather than "sysram" or "shmem". Furthermore, place the brackets around the SYSRAM references such that a two-element array is created rather than a two-element array nested in a single-element array. This is not relevant for device tree itself, but allows the nodes to be properly validated against json-schema bindings. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Fix pcie-ep DT nodesMauro Carvalho Chehab3-5/+5
As defined by Documentation/devicetree/bindings/pci/pci-ep.yaml, PCIe endpoints match this pattern: properties: $nodename: pattern: "^pcie-ep@" Change the existing ones in order to avoid those warnings: arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0001.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@14160000: $nodename:0: 'pcie_ep@14160000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@14180000: $nodename:0: 'pcie_ep@14180000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dt.yaml: pcie_ep@141a0000: $nodename:0: 'pcie_ep@141a0000' does not match '^pcie-ep@' From schema: Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Remove useless usb-ehci compatible stringThierry Reding2-5/+5
There's no such thing as a generic USB EHCI controller. The EHCI controllers found on Tegra SoCs are instantiations that need Tegra- specific glue to work properly, so drop the generic compatible string and keep only the Tegra-specific ones. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Extend APE audio support on Jetson platformsSameer Pujar5-0/+5481
Extend APE audio support by adding more audio components such as SFC, MVC, AMX, ADX and Mixer. These components can be plugged into an audio path and required processing can be done. ASoC audio-graph based sound driver is used to facilitate this and thus extend sound bindings as well. The components in the path may require different PCM parameters (such as sample rate, channels or sample size). Depending on the pre-defined audio paths, these can be statically configured with "convert-xxx" DT properties in endpoint subnode. The support for the rate and channel conversion is already available in generic audio-graph driver. Sample size conversion support can be added based on the need in future. The support is extended for following platforms: * Jertson TX1 * Jetson Nano * Jetson TX2 * Jetson AGX Xavier * Jetson Xavier NX Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Add few AHUB devices for Tegra210 and laterSameer Pujar3-0/+313
Add DT nodes for following AHUB devices: * SFC (Sampling Frequency Converter) * MVC (Master Volume Control) * AMX (Audio Multiplexer) * ADX (Audio Demultiplexer) * Mixer Above devices are added for Tegra210, Tegra186 and Tegra194 generations of Tegra SoC. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-07arm64: tegra: Remove unused backlight-boot-off propertyDavid Heidelberg1-2/+0
The backlight-boot-off property was proposed as a patch, but ended not being accepted since different solution was already in the place: https://patchwork.kernel.org/project/linux-arm-kernel/patch/1406806970-12561-1-git-send-email-thierry.reding@gmail.com/#21327479 Signed-off-by: David Heidelberg <david@ixit.cz> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-06arm64: tegra: Add NVDEC to Tegra186/194 device treesMikko Perttunen2-0/+54
Add a device tree node for NVDEC on Tegra186, and device tree nodes for NVDEC and NVDEC1 on Tegra194. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-10-04arm64: tegra: Add new USB PHY properties on Tegra132Dmitry Osipenko1-0/+6
Add new properties to USB PHYs needed for enabling USB OTG mode. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-09-24arm64: tegra: Update HDA card name on Jetson TX2 NXSameer Pujar1-1/+1
Inspired by commit b8928c2b5dba ("arm64: tegra: Consolidate audio card names"). Based on this update HDA card name on Jetson TX2 NX platform. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-09-24arm64: tegra: Audio graph sound card for Jetson TX2 NXSameer Pujar1-0/+504
Enable support for audio-graph based sound card on Jetson TX2 NX. Following I/O interfaces are enabled. * I2S1 and I2S3 * DMIC1 and DMIC2 Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-09-24arm64: tegra: Add additional GPIO interrupt entries on Tegra194pshete1-2/+47
Tegra194 supports 8 entries per GPIO controller. This change adds the missing interrupt entires for all GPIO controllers. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-09-01Merge tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds6-6/+816
Pull ARM SoC DT updates from Arnd Bergmann: "As usual, the bulk of work in the SoC tree goes into DT files, this time with a roughly even split between 32-bit and 64-bit SoCs rather than the usual mostly 64-bit changes. New SoCs: - Microchip SAMA7 SoC family based on Cortex-A7, a new 32-bit platform based on the older SAMA5 series. - Qualcomm Snapdragon SDM636 and SM8150, variations of the existing phone SoCs. - Renesas R-Car H3e-2G and M3e-2G SoCs, variations of older Renesas SoCs. New boards: - Marvell CN913x reference boards - ASpeed AST2600 BMC implementations for Facebook Cloudripper, Elbert and Fuji server boards. - Snapdragon 665 based Sony Xperia 10II - Snapdragon MSM8916 based Xiaomi Redmi 2 - Snapdragon MSM8226 based Samsung Galaxy S3 Neo - NXP i.MX based 32-bit boards: - DHCOM based PicoITX - DHSOM based DRC0ỉ - SolidRun SolidSense - SKOV i.MX6 boards. - NXP i.MX based 64-bit boards: - Nitrogen8 SoM and MNT Reform2 - LS1088A based Traverse Ten64 - i.MX8M based GW7902. - NVIDIA Jetson TX2 NX Developer Kit - 4KOpen STiH418-b2264 development board - ux500 based Samsung phones: Gavini, Codina and Kyle - TI AM335x based Sancloud BBE Lite - ixp4xx dts files to replace all old board files Other changes: - Treewide fixes for dtc warnings - Rockchips i/o domain support - TI OMAP/AM3 CPSW switch driver support - Improved device support for allwinner, aspeed, qualcomm, NXP, nvidia, Renesas, Samsung, Amlogic, Mediatek, ixp4xx, stm32, sti, OMAP and actions" * tag 'dt-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (412 commits) arm/arm64: dts: Fix remaining dtc 'unit_address_format' warnings ARM: dts: rockchip: Add SFC to RV1108 arm64: dts: marvell: armada-37xx: Extend PCIe MEM space ARM: dts: aspeed: p10bmc: Add power control pins ARM: dts: aspeed: cloudripper: Add comments for "mdio1" ARM: dts: aspeed: minipack: Update flash partition table dt-bindings: arm: fsl: Add Traverse Ten64 (LS1088A) board dt-bindings: vendor-prefixes: add Traverse Technologies arm64: dts: add device tree for Traverse Ten64 (LS1088A) arm64: dts: ls1088a: add missing PMU node arm64: dts: ls1088a: add internal PCS for DPMAC1 node ARM: dts: imx6qp-prtwd3: configure ENET_REF clock to 125MHz ARM: dts: vf610-zii-dev-rev-b: Remove #address-cells and #size-cells property from at93c46d dt node ARM: dts: add SKOV imx6q and imx6dl based boards dt-bindings: arm: fsl: add SKOV imx6q and imx6dl based boards dt-bindings: vendor-prefixes: Add an entry for SKOV A/S arm64: dts: imx8mq-reform2: add sound support arm64: dts: imx8m: drop interrupt-affinity for pmu arm64: dts: imx8qxp: update pmu compatible arm64: dts: imx8mm: update pmu compatible ...
2021-08-16Merge tag 'tegra-for-5.15-arm64-dt' of ↵Arnd Bergmann6-6/+816
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.15-rc1 Contains a couple of fixes across the board and adds support for the recently released NVIDIA Jetson TX2 NX Developer Kit. * tag 'tegra-for-5.15-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Fix compatible string for Tegra132 CPUs arm64: tegra: Add missing interconnects property for USB on Tegra186 arm64: tegra: Add NVIDIA Jetson TX2 NX Developer Kit support arm64: tegra: Add PWM nodes on Tegra186 arm64: tegra194: p2888: Correct interrupt trigger type of temperature sensor arm64: tegra: Fix Tegra194 PCIe EP compatible string Link: https://lore.kernel.org/r/20210813162157.2820913-6-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-08-13arm64: tegra: Fix compatible string for Tegra132 CPUsThierry Reding1-2/+2
The documented compatible string for the CPUs found on Tegra132 is "nvidia,tegra132-denver", rather than the previously used compatible string "nvidia,denver". Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add missing interconnects property for USB on Tegra186Thierry Reding1-0/+3
The device tree node for the XUDC (USB device mode controller) is missing the interconnects property that describes the path to memory for the controller. Add the property so that the things like the DMA mask can be set by the operating system. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add NVIDIA Jetson TX2 NX Developer Kit supportThierry Reding2-0/+719
The Jetson TX2 NX Developer Kit is very similar to the Jetson Nano, but uses the more powerful Tegra186 SoC. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-12arm64: tegra: Add PWM nodes on Tegra186Thierry Reding1-0/+88
These PWMs can be used for fan or LED backlight control. Add the device tree nodes for all existing controllers found on Tegra186 SoCs. None of these are enabled by default, which is left for the board DTS files to do when necessary. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-11arm64: tegra194: p2888: Correct interrupt trigger type of temperature sensorDmitry Osipenko1-1/+1
The LM90 temperature sensor should use edge-triggered interrupt because LM90 hardware doesn't deassert interrupt line until temperature is back to normal state, which results in interrupt storm. Correct the interrupt trigger type. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-08-02arm64: tegra: Fix Tegra194 PCIe EP compatible stringVidya Sagar1-3/+3
The initialization sequence performed by the generic platform driver pcie-designware-plat.c for a DWC based implementation doesn't work for Tegra194. Tegra194 has a different initialization sequence requirement which can only be satisfied by the Tegra194 specific platform driver pcie-tegra194.c. So, remove the generic compatible string "snps,dw-pcie-ep" from Tegra194's endpoint controller nodes. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-07-17arm64: tegra: Enable SMMU support for PCIe on Tegra194Vidya Sagar1-6/+54
As of commit c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194"), SMMU support is enabled system-wide on Tegra194. However, there was a bit of overlap between the SMMU enablement and the PCIe support addition, so the PCIe device tree nodes are missing the iommus and interconnects properties. This in turn leads to SMMU faults for these devices, since by default the ARM SMMU will fault. Add the iommus and interconnects properties to all the PCIe device tree nodes to restore their functionality. Fixes: c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-07-09arm64: tegra: Enable SMMU support for USB on Tegra194Thierry Reding1-0/+8
As of commit c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194"), SMMU support is enabled system-wide on Tegra194. However, there was a bit of overlap between the SMMU enablement and the USB support addition, so the USB device tree nodes are missing the iommus and interconnects properties. This in turn leads to SMMU faults for these devices, since by default the ARM SMMU will fault. Add the iommus and interconnects properties to the XUSB and XUDC device tree nodes to restore their functionality. Fixes: c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194") Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-07-09arm64: tegra: Enable audio IOMMU support on Tegra194Thierry Reding1-0/+5
Add iommus and interconnects properties to the sound device tree node on Tegra194. This ensures that the correct SID is used for translation of physical to I/O virtual addresses and that the path to system memory is properly described, which in turn can impact the range of memory that the device can address. Fixes: c7289b1c8a4e ("arm64: tegra: Enable SMMU support on Tegra194") Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-11arm64: tegra: Enable SMMU support on Tegra194Thierry Reding1-0/+86
Add the device tree node for the dual-SMMU found on Tegra194 and hook up peripherals such as host1x, BPMP, HDA, SDMMC, EQOS and VIC. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-11arm64: tegra: Hook up memory controller to SMMU on Tegra186Thierry Reding1-0/+2
On Tegra186 and later, the memory controller needs to be programmed in coordination with any of the ARM SMMU instances to configure the stream ID used for each memory client. To support this, add a phandle reference to the memory controller to the SMMU device tree node. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-11arm64: tegra: Use correct compatible string for Tegra186 SMMUThierry Reding1-1/+1
The SMMU found on Tegra186 requires interoperation with the memory controller in order to program stream ID overrides. The generic ARM SMMU 500 compatible is therefore inaccurate. Replace it with a more correct, SoC-specific compatible string. Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-06-08arm64: tegra: Audio graph sound card for Jetson Xavier NXSameer Pujar1-0/+593
Enable support for audio-graph based sound card on Jetson Xavier NX. Following I/O interfaces are enabled. - I2S3 and I2S5 - DMIC1, DMIC2 and DMIC4 - DSPK1 and DSPK2 Signed-off-by: Sameer Pujar <spujar@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-08 04:06:05 +0000