summaryrefslogtreecommitdiff
path: root/arch/riscv/boot/dts/sifive/Makefile
AgeCommit message (Collapse)AuthorFilesLines
2024-03-06riscv: dts: Move BUILTIN_DTB_SOURCE to common KconfigYangyu Chen1-1/+0
The BUILTIN_DTB_SOURCE was only configured for K210 before. Since SOC_BUILTIN_DTB_DECLARE was removed at commit d5805af9fe9f ("riscv: Fix builtin DTB handling") from patch [1], the kernel cannot choose one of the dtbs from then on and always take the first one dtb to use. Then, another commit 0ddd7eaffa64 ("riscv: Fix BUILTIN_DTB for sifive and microchip soc") from patch [2] supports BUILTIN_DTB_SOURCE for other SoCs. However, this feature will only work if the Kconfig we use links the dtb we expected in the first place as mentioned in the thread [3]. Thus, a config BUILTIN_DTB_SOURCE is needed for all SoCs to choose one dtb to use. For some considerations, this patch also removes default y if XIP_KERNEL for BUILTIN_DTB, as this requires setting a proper dtb to use on the BUILTIN_DTB_SOURCE, else the kernel with XIP but does not set BUILTIN_DTB_SOURCE or unselect BUILTIN_DTB will not boot. Also, this patch removes the default dtb string for k210 from Kconfig to nommu_k210_defconfig and nommu_k210_sdcard_defconfig to avoid complex Kconfig settings for other SoCs in the future. [1] https://lore.kernel.org/linux-riscv/20201208073355.40828-5-damien.lemoal@wdc.com/ [2] https://lore.kernel.org/linux-riscv/20210604120639.1447869-1-alex@ghiti.fr/ [3] https://lore.kernel.org/linux-riscv/CAK7LNATt_56mO2Le4v4EnPnAfd3gC8S_Sm5-GCsfa=qXy=8Lrg@mail.gmail.com/ Signed-off-by: Yangyu Chen <cyy@cyyself.name> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-12-27RISC-V: kbuild: convert all use of SOC_FOO to ARCH_FOOConor Dooley1-2/+2
Convert all non user visible use of SOC_FOO symbols to their ARCH_FOO variants. The canaan DTs are an outlier in that they're gated at the directory and the file level. Drop the directory level gating while we are swapping the symbol names over. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2021-06-11riscv: Fix BUILTIN_DTB for sifive and microchip socAlexandre Ghiti1-0/+1
Fix BUILTIN_DTB config which resulted in a dtb that was actually not built into the Linux image: in the same manner as Canaan soc does, create an object file from the dtb file that will get linked into the Linux image. Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2021-01-07riscv: dts: add initial board data for the SiFive HiFive UnmatchedYash Shah1-1/+2
Add initial board data for the SiFive HiFive Unmatched A00. This patch is dependent on Zong's Patchset[0]. [0]: https://lore.kernel.org/linux-riscv/20201130082330.77268-4-zong.li@sifive.com/T/#u Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2019-07-01arch: riscv: add config option for building SiFive's SoC resourceLoys Ollivier1-1/+1
Create a config option for building SiFive SoC specific resources e.g. SiFive device tree, platform drivers... Signed-off-by: Loys Ollivier <lollivier@baylibre.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-06-17riscv: dts: add initial board data for the SiFive HiFive UnleashedPaul Walmsley1-0/+2
Add initial board data for the SiFive HiFive Unleashed A00. Currently the data populated in this DT file describes the board DRAM configuration and the external clock sources that supply the PRCI. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Loys Ollivier <lollivier@baylibre.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org