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2020-09-22clk: imx: imx35: Remove mx35_clocks_init()Fabio Estevam1-68/+0
mx35_clocks_init() has been used to register clocks on i.MX35 non-devicetree platforms. Now that i.MX is a devicetree-only platform, it is safe to remove mx35_clocks_init() as there are no more users. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22clk: imx: imx31: Remove mx31_clocks_init()Fabio Estevam1-71/+0
mx31_clocks_init() has been used to register clocks on i.MX31 non-devicetree platforms. Now that i.MX is a devicetree-only platform, it is safe to remove mx31_clocks_init() as there are no more users. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-22clk: imx: imx27: Remove mx27_clocks_init()Fabio Estevam1-73/+0
mx27_clocks_init() has been used to register clocks on i.MX27 non-devicetree platforms. Now that i.MX is a devicetree-only platform, it is safe to remove mx27_clocks_init() as there are no more users. Signed-off-by: Fabio Estevam <festevam@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-21clk: tegra: Fix missing prototype for tegra210_clk_register_emc()Thierry Reding1-0/+2
Include the Tegra driver's clk.h to pull in the prototype definition for this function so that compilers don't warn about it being missing. Fixes: 0ac65fc946d3 ("clk: tegra: Implement Tegra210 EMC clock") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-21clk: tegra: Always program PLL_E when enabledThierry Reding1-3/+0
Commit bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") added checks to avoid enabling PLLs that have already been enabled by the bootloader. However, the PLL_E configuration inherited from the bootloader isn't necessarily the one that is needed for the kernel. This can cause SATA to fail like this: [ 5.310270] phy phy-sata.6: phy poweron failed --> -110 [ 5.315604] tegra-ahci 70027000.sata: failed to power on AHCI controller: -110 [ 5.323022] tegra-ahci: probe of 70027000.sata failed with error -110 Fix this by always programming the PLL_E. This ensures that any mis- configuration by the bootloader will be overwritten by the kernel. Fixes: bff1cef5f23a ("clk: tegra: Don't enable already enabled PLLs") Reported-by: LABBE Corentin <clabbe@baylibre.com> Tested-by: Corentin Labbe <clabbe@baylibre.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-21clk: tegra: Capitalization fixesThierry Reding1-2/+2
HW, XUSB and PLL are abbreviations and should be all-uppercase. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-09-17clk: renesas: rcar-gen3: Update description for RZ/G2Lad Prabhakar1-1/+1
The rcar-gen3-cpg driver is also used on Renesas RZ/G2 SoC's, update the description for the CLK_RCAR_GEN3_CPG config symbol to reflect this. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com> Link: https://lore.kernel.org/r/20200911101703.20521-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-17clk: renesas: cpg-mssr: Add support for R-Car V3UYoshihiro Shimoda5-1/+316
Initial support for R-Car V3U (r8a779a0), including core, module clocks, resets, and register access, because register specification differs from R-Car Gen2/3. Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-17clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_privYoshihiro Shimoda1-35/+47
To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_priv. After that, we can remove unused macros like MSTPSR(). No behavioral changes. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-17clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flagYoshihiro Shimoda3-19/+22
Geert suggested defining multiple register layout variants using an enum [1] to support further devices like R-Car V3U. So, use enum clk_reg_layout instead of a boolean .stbyctrl flag. No behavioral change. [1] https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/ Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-17clk: samsung: Use cached clk_hws instead of __clk_lookup() callsSylwester Nawrocki7-36/+42
For the CPU clock registration two parent clocks are required, these are now being passed as struct clk_hw pointers, rather than by the global scope names. That allows us to avoid __clk_lookup() calls and simplifies a bit the CPU clock registration function. While at it drop unneeded extern keyword in the function declaration. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20200826171529.23618-3-s.nawrocki@samsung.com Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-09-17clk: samsung: exynos5420/5250: Add IDs to the CPU parent clk definitionsSylwester Nawrocki2-7/+8
Use non-zero clock IDs in definitions of the CPU parent clocks for exynos5420, exynos5250 SoCs. This will allow us to reference the parent clocks directly in the driver by cached struct clk_hw pointers, rather than doing clk lookup by name. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Link: https://lore.kernel.org/r/20200826171529.23618-2-s.nawrocki@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-09-17clk: samsung: exynos5420: Avoid __clk_lookup() calls when enabling clocksSylwester Nawrocki1-4/+6
This patch adds a clk ID to the mout_sw_aclk_g3d clk definition so related clk pointer gets cached in the driver's private data and can be used later instead of a __clk_lookup() call. With that we have all clocks used in the clk_prepare_enable() calls in the clk provider init callback cached in clk_data.hws[] and we can reference the clk pointers directly rather than using __clk_lookup() with global names. Link: https://lore.kernel.org/r/20200811151251.31613-2-s.nawrocki@samsung.com Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-09-15Merge tag 'v5.9-clk-samsung-fixes' of ↵Stephen Boyd1-0/+5
https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-fixes Pull a Samsung clk driver fix from Sylwester Nawrocki: - fix for a regression in v5.9-rc1 on Odroid XU3/XU4, i.e. booting failure due to the DRAM controller root clock being disabled * tag 'v5.9-clk-samsung-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Keep top BPLL mux on Exynos542x enabled
2020-09-15clk: samsung: Keep top BPLL mux on Exynos542x enabledMarek Szyprowski1-0/+5
BPLL clock must not be disabled because it is needed for proper DRAM operation. This is normally handled by respective memory devfreq driver, but when that driver is not yet probed or its probe has been deferred the clock might get disabled what causes board hang. Fix this by calling clk_prepare_enable() directly from the clock provider driver. Cc: stable@vger.kernel.org Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Lukasz Luba <lukasz.luba@arm.com> Tested-by: Lukasz Luba <lukasz.luba@arm.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200807133143.22748-1-m.szyprowski@samsung.com Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422") Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-09-13clk: imx: gate2: Fix a few typosJonathan Neuschäfer1-1/+1
A few words were misspelled in this comment. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-10clk: qcom: lpass: Correct goto target in lpass_core_sc7180_probe()Jing Xiangfeng1-3/+4
lpass_core_sc7180_probe() misses to call pm_clk_destroy() and pm_runtime_disable() in error paths. Correct goto target to fix it. This issue is found by code inspection. Signed-off-by: Jing Xiangfeng <jingxiangfeng@huawei.com> Link: https://lore.kernel.org/r/20200827141629.101802-1-jingxiangfeng@huawei.com Fixes: edab812d802d ("clk: qcom: lpass: Add support for LPASS clock controller for SC7180") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-10clk: meson: make shipped controller configurableJerome Brunet1-9/+17
Add the necessary bits so unnecessary amlogic clock controllers can be compiled out. This allows to save a few kB when necessary. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200828154735.435374-1-jbrunet@baylibre.com
2020-09-10clk: versatile: Add of_node_put() before return statementSumera Priyadarsini1-1/+3
Every iteration of for_each_available_child_of_node() decrements the reference count of the previous node, however when control is transferred from the middle of the loop, as in the case of a return or break or goto, there is no decrement thus ultimately resulting in a memory leak. Fix a potential memory leak in clk-impd1.c by inserting of_node_put() before a return statement. Issue found with Coccinelle. Signed-off-by: Sumera Priyadarsini <sylphrenadin@gmail.com> Link: https://lore.kernel.org/r/20200829175704.GA10998@Kaladin Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-10clk: bcm: dvp: Select the reset frameworkMaxime Ripard1-0/+1
The DVP driver depends both on the RESET_SIMPLE driver but also on the reset framework itself. Let's make sure we have it enabled. Fixes: 1bc95972715a ("clk: bcm: Add BCM2711 DVP driver") Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200903082636.3844629-1-maxime@cerno.tech Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-09-07clk: imx: Fix and update kerneldocKrzysztof Kozlowski3-3/+6
Fix and add missing kerneldoc to fix compile warnings like: drivers/clk/imx/clk-pfd.c:27: warning: Function parameter or member 'hw' not described in 'clk_pfd' drivers/clk/imx/clk-pllv3.c:53: warning: Function parameter or member 'ref_clock' not described in 'clk_pllv3' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-07clk: imx: fix i.MX7D peripheral clk mux flagsPeng Fan1-65/+66
According to RM, Page 574, Chapter 5.2.6.4.3 Peripheral clock slice, "IP clock slices must be stopped to change the clock source.". So we must have CLK_SET_PARENT_GATE flag to avoid glitch. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-07clk: imx: fix composite peripheral flagsPeng Fan1-0/+1
According to RM, for peripheral clock slice, "IP clock slices must be stopped to change the clock source.". So we must have CLK_SET_PARENT_GATE flag to avoid glitch. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-09-04clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r)Lad Prabhakar7-8/+8
VSP1 instances VSPS (which stands for "VSP Standard") and VSPR (which stands for "VSP for Resizing") were wrongly named as "vsp1-sy" and "vsp1-rt". The clock section in the SoC datasheets misunderstood the abbreviations as meaning VSP System and VSP Realtime, and named the corresponding clocks VSP1(SY) and VSP1(RT). This mistake has been carried over to the kernel code. This patch fixes this by renaming the clock names to "vsps" and "vspr". Inspired from commit 79ea9934b8df ("ARM: shmobile: r8a7790: Rename VSP1_(SY|RT) clocks to VSP1_(S|R)") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20200831183722.8165-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-09-04clk: renesas: r8a7742: Add clk entry for VSPRLad Prabhakar1-1/+2
Add clock entry 130 for VSPR (VSP for Resizing) module, so that this module can be used on R8A7742 (RZ/G1H) SoC. Alongside rename clock entry "vsp1-sy" to "vsps" (VSP Standard), so that VSP1 clock names are in sync. Note: The entry for VSPR clock was accidentally dropped from RZ/G manual when all the information related to RT were removed. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20200831180312.7453-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-08-31clk: imx: Correct the memrepair clock on imx8mpJacky Bai1-10/+4
The root clock slice at offset 0xbf80 should be memrepair clock, so correct it. And this clock should be always on to make sure the memory repair function can works well. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-31clk: imx: Correct the root clk of media ldb on imx8mpJacky Bai1-5/+5
The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref, so correct it. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-29clk: meson: g12a: mark fclk_div2 as criticalStefan Agner1-0/+11
On Amlogic Meson G12b platform, similar to fclk_div3, the fclk_div2 seems to be necessary for the system to operate correctly as well. Typically, the clock also gets chosen by the eMMC peripheral. This probably masked the problem so far. However, when booting from a SD card the clock seems to get disabled which leads to a system freeze. Let's mark this clock as critical, fixing boot from SD card on G12b platforms. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Anand Moon <linux.amoon@gmail.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/577e0129e8ee93972d92f13187ff4e4286182f67.1598629915.git.stefan@agner.ch
2020-08-25clk: sunxi-ng: sun8i: r40: Use sigma delta modulation for audio PLLJernej Skrabec1-13/+24
Audio cores need specific clock rates which can't be simply obtained by adjusting integer multipliers and dividers. HW for such cases supports delta-sigma modulation which enables fractional multipliers. Port H3 delta-sigma table to R40. They have identical audio PLLs. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200825131049.1277596-1-jernej.skrabec@siol.net
2020-08-25clk: sunxi-ng: add support for the Allwinner A100 CCUYangtao Li6-0/+1579
Add support for a100 in the sunxi-ng CCU framework. Signed-off-by: Yangtao Li <frank@allwinnertech.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1eb41bf6c966a0e54820200650d27a5d4f2ac160.1595572867.git.frank@allwinnertech.com
2020-08-23clk: imx: vf610: Add CRC clockKrzysztof Kozlowski1-0/+1
Add the clock for CRC block allowing it to be enabled by consumers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: imx: Explicitly include bits.hAnson Huang13-1/+13
It is better to explicitly include the required header file rather then get it through some recursive include. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: imx8qxp: Support building i.MX8QXP clock driver as moduleAnson Huang4-9/+18
Change configuration to "tristate", add module author, description and license to support building i.MX8QXP clock drivers as module. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: imx8m: Support module buildAnson Huang5-8/+24
Change configuration to "tristate", add module author, description and license to support building i.MX8M SoCs clock driver as module. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: imx: Add clock configuration for ARMv7 platformsAnson Huang2-16/+76
Add CONFIG_CLK_xxx for i.MX ARMv7 platforms, and use it as build option instead of CONFIG_SOC_xxx, the CONFIG_CLK_xxx will be selected by default according to CONFIG_SOC_xxx. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: imx: Support building i.MX common clock driver as moduleAnson Huang10-26/+60
There are more and more requirements of building SoC specific drivers as modules, add support for building i.MX common clock driver as module to meet the requirement. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: composite: Export clk_hw_register_composite()Anson Huang1-0/+1
Export clk_hw_register_composite() to support user built as module. ERROR: modpost: "clk_hw_register_composite" [drivers/clk/imx/mxc-clk.ko] undefined! Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-22clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bitsAnson Huang1-7/+8
Use readl_relaxed() instead of __raw_readl(), and use BIT(x) instead of (1 << X) to fix below build warning reported by kernel test robot: drivers/clk/imx/clk-imx6sl.c:149:49: warning: Shifting signed 32-bit value by 31 bits is undefined behaviour [shiftTooManyBitsSigned] while (!(__raw_readl(anatop_base + PLL_ARM) & BM_PLL_ARM_LOCK)) Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-08-19ARM: s3c24xx: pass pointer to clk driver via platform dataKrzysztof Kozlowski1-1/+6
Passing pointers directly as platform data is fragile and undocumented. Better to create a platform data structure which explicitly documents what is passed to the driver. Suggested-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200806182059.2431-6-krzk@kernel.org
2020-08-19ARM: s3c24xx: make S3C24XX_MISCCR access indirectArnd Bergmann1-6/+4
The clk driver uses both a function call into an exported platform file and a direct register access to a hardcoded virtual address for accessing the MISCCR register, both become are a problem for a multiplatform kernel because of the header file dependency. Make this an indirect function call through platform data instead. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200806182059.2431-5-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-08-18clk: rockchip: Fix initialization of mux_pll_src_4plls_pNathan Chancellor1-1/+1
A new warning in Clang points out that the initialization of mux_pll_src_4plls_p appears incorrect: ../drivers/clk/rockchip/clk-rk3228.c:140:58: warning: suspicious concatenation of string literals in an array initialization; did you mean to separate the elements with a comma? [-Wstring-concatenation] PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; ^ , ../drivers/clk/rockchip/clk-rk3228.c:140:48: note: place parentheses around the string literal to silence warning PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy" "usb480m" }; ^ 1 warning generated. Given the name of the variable and the same variable name in rv1108, it seems that this should have been four distinct elements. Fix it up by adding the comma as suggested. Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228") Link: https://github.com/ClangBuiltLinux/linux/issues/1123 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Link: https://lore.kernel.org/r/20200810044020.2063350-1-natechancellor@gmail.com Reviewed-by: Heiko Stübner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-18clk: davinci: Use the correct size when allocating memoryChristophe JAILLET1-1/+1
'sizeof(*pllen)' should be used in place of 'sizeof(*pllout)' to avoid a small over-allocation. Fixes: 2d1726915159 ("clk: davinci: New driver for davinci PLL clocks") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20200809144959.747986-1-christophe.jaillet@wanadoo.fr Reviewed-by: David Lechner <david@lechnology.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-08-17clk: samsung: s3c24xx: declare s3c24xx_common_clk_init() in shared headerKrzysztof Kozlowski3-0/+3
The s3c2410_common_clk_init() and others are defined and used by the clk-s3c24xx driver and also used in the mach-s3c24xx machine code. Move the declaration to a header to fix W=1 build warnings: drivers/clk/samsung/clk-s3c2410.c:320:13: warning: no previous prototype for 's3c2410_common_clk_init' [-Wmissing-prototypes] 320 | void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f, drivers/clk/samsung/clk-s3c2412.c:205:13: warning: no previous prototype for 's3c2412_common_clk_init' [-Wmissing-prototypes] 205 | void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f, drivers/clk/samsung/clk-s3c2443.c:341:13: warning: no previous prototype for 's3c2443_common_clk_init' [-Wmissing-prototypes] 341 | void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f, Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2020-08-17clk: samsung: s3c64xx: declare s3c64xx_clk_init() in shared headerKrzysztof Kozlowski1-0/+1
The s3c64xx_clk_init() is defined and used by the clk-s3c64xx driver and also used in the mach-s3c64xx machine code. Move the declaration to a header to fix W=1 build warning: drivers/clk/samsung/clk-s3c64xx.c:391:13: warning: no previous prototype for 's3c64xx_clk_init' [-Wmissing-prototypes] 391 | void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f, Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
2020-08-17clk: meson: axg-audio: fix g12a tdmout sclk inverterJerome Brunet1-25/+60
Fix the tdmout inverter of the g12a and following SoC families. This inverter is special and needs two bits to be the inverse of each other for the inverter to operate properly. Fixes: 075001385c66 ("clk: meson: axg-audio: add g12a support") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200729154359.1983085-4-jbrunet@baylibre.com
2020-08-17clk: meson: axg-audio: separate axg and g12a regmap tablesJerome Brunet1-8/+127
There are more differences than what we initially thought. Let's keeps things clear and separate the axg and g12a regmap tables of the audio clock controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200729154359.1983085-3-jbrunet@baylibre.com
2020-08-17clk: meson: add sclk-ws driverJerome Brunet2-0/+62
This is yet another simple but odd driver for the audio block of the g12a and sm1 SoC families. For TDMOUT's sclk to be properly inverted, bit 29 of AUDIO_CLK_TDMOUT_x_CTRL should be the inverse of bit 28. IOW bit28 == !bit29 at all times This setting is automatically applied on axg and the manual setting was added on g12a. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200729154359.1983085-2-jbrunet@baylibre.com
2020-08-15Merge tag 'acpi-5.9-rc1-2' of ↵Linus Torvalds3-79/+102
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull more ACPI updates from Rafael Wysocki: "Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk driver and the Designware i2c driver (changes from Akshu Agrawal and Pu Wen)" * tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: clk: x86: Support RV architecture ACPI: APD: Add a fmw property is_raven clk: x86: Change name from ST to FCH ACPI: APD: Change name from ST to FCH i2c: designware: Add device HID for Hygon I2C controller
2020-08-14Merge tag 'pwm/for-5.9-rc1' of ↵Linus Torvalds1-1/+6
git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm updates from Thierry Reding: "The majority of this batch is conversion of the PWM period and duty cycle to 64-bit unsigned integers, which is required so that some types of hardware can generate the full range of signals that they're capable of. The remainder is mostly minor fixes and cleanups" * tag 'pwm/for-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: bcm-iproc: handle clk_get_rate() return pwm: Replace HTTP links with HTTPS ones pwm: omap-dmtimer: Repair pwm_omap_dmtimer_chip's broken kerneldoc header pwm: mediatek: Provide missing kerneldoc description for 'soc' arg pwm: bcm-kona: Remove impossible comparison when validating duty cycle pwm: bcm-iproc: Remove impossible comparison when validating duty cycle pwm: iqs620a: Use lowercase hexadecimal literals for consistency pwm: Convert period and duty cycle to u64 clk: pwm: Use 64-bit division function backlight: pwm_bl: Use 64-bit division function pwm: sun4i: Use nsecs_to_jiffies to avoid a division pwm: sifive: Use 64-bit division macro pwm: iqs620a: Use 64-bit division pwm: imx27: Use 64-bit division macro pwm: imx-tpm: Use 64-bit division macro pwm: clps711x: Use 64-bit division macro hwmon: pwm-fan: Use 64-bit division macro drm/i915: Use 64-bit division macro
2020-08-12Merge tag 'clk-for-linus' of ↵Linus Torvalds61-588/+4230
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull more clk updates from Stephen Boyd: "Here's some more updates that missed the last pull request because I happened to tag the tree at an earlier point in the history of clk-next. I must have fat fingered it and checked out an older version of clk-next on this second computer I'm using. This time it actually includes more code for Qualcomm SoCs, the AT91 major updates, and some Rockchip SoC clk driver updates as well. I've corrected this flow so this shouldn't happen again" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (83 commits) clk: bcm2835: Do not use prediv with bcm2711's PLLs clk: drop unused function __clk_get_flags clk: hsdk: Fix bad dependency on IOMEM dt-bindings: clock: Fix YAML schemas for LPASS clocks on SC7180 clk: mmp: avoid missing prototype warning clk: sparx5: Add Sparx5 SoC DPLL clock driver dt-bindings: clock: sparx5: Add bindings include file clk: qoriq: add LS1021A core pll mux options clk: clk-atlas6: fix return value check in atlas6_clk_init() clk: tegra: pll: Improve PLLM enable-state detection clk: X1000: Add support for calculat REFCLK of USB PHY. clk: JZ4780: Reformat the code to align it. clk: JZ4780: Add functions for enable and disable USB PHY. clk: Ingenic: Add RTC related clocks for Ingenic SoCs. dt-bindings: clock: Add tabs to align code. dt-bindings: clock: Add RTC related clocks for Ingenic SoCs. clk: davinci: Use fallthrough pseudo-keyword clk: imx: Use fallthrough pseudo-keyword clk: qcom: gcc-sdm660: Fix up gcc_mss_mnoc_bimc_axi_clk clk: qcom: gcc-sdm660: Add missing modem reset ...
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