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path: root/drivers/crypto/hisilicon
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2021-04-02crypto: hisilicon/hpre - fix PASID setting on kunpeng 920Hui Tang1-25/+18
We must confirm the PASID is disabled before using no-sva mode. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-02crypto: hisilicon/zip - support new 'sqe' type in Kunpeng930Yang Shen2-0/+26
The Kunpeng930 changes some field meanings in 'sqe'. So add a new 'hisi_zip_sqe_ops' to describe the 'sqe' operations. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-02crypto: hisilicon/zip - initialize operations about 'sqe' in 'acomp_alg.init'Yang Shen1-31/+110
The operations about 'sqe' are different on some hardwares. Add a struct 'hisi_zip_sqe_ops' to describe the operations in a hardware. And choose the 'ops' in 'hisi_zip_acomp_init' according to the hardware. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-02crypto: hisilicon/zip - add comments for 'hisi_zip_sqe'Yang Shen2-15/+34
Some fields of 'hisi_zip_sqe' are unused, and some fields have misc utilities. So add comments for used fields and make others unnamed. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-02crypto: hisilicon/zip - adjust functions locationYang Shen1-276/+276
This patch changes nothing about functions except location in order to make code logic clearly. This adjustment follows three principles: 1.The called functions are listed in order above the calling functions. 2.The paired functions are next to each other. 3.Logically similar functions are placed in the same area. Here, we use the callback of 'acomp_alg' as the basis for dividing areas. Signed-off-by: Yang Shen <shenyang39@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-02crypto: hisilicon - use the correct HiSilicon copyrightHao Fang3-5/+5
s/Hisilicon/HiSilicon/g, according to https://www.hisilicon.com/en/terms-of-use. Signed-off-by: Hao Fang <fanghao11@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/qm - add queue isolation support for Kunpeng930Weili Qian2-48/+117
Kunpeng930 supports doorbell isolation to ensure that each queue has an independent doorbell address space. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/qm - set the number of queues for functionWeili Qian2-26/+78
Kunpeng930 supports queue doorbell isolation. When doorbell isolation is enabled, it supports to obtain the maximum number of queues of one function from hardware register. Otherwise, the 'max_qp_num' is the total number of queues. When assigning queues to VF, it is necessary to ensure that the number of VF queues does not exceed 'max_qp_num'. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/qm - move 'CURRENT_QM' code to qm.cWeili Qian7-200/+76
Since the code related to 'CURRENT_QM' debugfs is exactly same in sec/hpre/zip driver, move 'CURRENT_QM' to qm.c to reduce duplicate code. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/qm - set the total number of queuesWeili Qian4-16/+16
Move the configuration of the total number of queues 'ctrl_qp_num' from sec2/hpre/zip to qm.c. And get the total number of queues from the hardware register for Kunpeng930. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/hpre - fix KconfigHui Tang1-1/+2
hpre select 'CRYPTO_ECDH' and 'CRYPTO_CURVE25519'. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/hpre - fix "hpre_ctx_init" resource leakHui Tang1-1/+12
When calling "hpre_ctx_set" fails, stop and put qp, otherwise will leak qp resource. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon - fix the check on dma addressHui Tang3-19/+1
System may be able to get physical address of zero if not reserved by firmware. The dma address obtained by 'dma_alloc_coherent' is valid, since already checking cpu va before, so do not check again. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/hpre - optimise 'hpre_algs_register' error pathHui Tang1-10/+9
There is redundant code especially when registing new algorithms in the future. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/hpre - delete wrap of 'CONFIG_CRYPTO_DH'Hui Tang1-10/+1
'CRYPTO_DH' has selected in 'Kconfig', so delete 'CONFIG_CRYPTO_DH'. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-26crypto: hisilicon/sec - Supply missing description for 'sec_queue_empty()'s ↵Lee Jones1-0/+1
'queue' param Fixes the following W=1 kernel build warning(s): drivers/crypto/hisilicon/sec/sec_drv.c:843: warning: Function parameter or member 'queue' not described in 'sec_queue_empty' Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "David S. Miller" <davem@davemloft.net> Cc: Zaibo Xu <xuzaibo@huawei.com> Cc: Jonathan Cameron <jonathan.cameron@huawei.com> Cc: linux-crypto@vger.kernel.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-19crypto: hisilicon/sec - fixes some driver coding styleLongfang Liu1-55/+76
cleanup static check errors for SEC Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-19crypto: hisilicon/sec - fixes some coding styleLongfang Liu3-43/+39
1.delete the original complex method of obtaining the current device and replace it with the initialized device pointer. 2.fixes some coding style Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-19crypto: hisilicon/sec - fixes a printing errorLongfang Liu1-1/+1
When the log is output here, the device has not been initialized yet. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-13crypto: hisilicon/hpre - add 'CURVE25519' algorithmMeng Yu3-8/+361
Enable 'CURVE25519' algorithm in Kunpeng 930. Signed-off-by: Meng Yu <yumeng18@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-13crypto: hisilicon/hpre - add 'ECDH' algorithmMeng Yu3-5/+513
1. Enable 'ECDH' algorithm in Kunpeng 930; 2. HPRE ECDH Support: ecdh-nist-p192, ecdh-nist-p256. Signed-off-by: Meng Yu <yumeng18@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-13crypto: hisilicon/hpre - add algorithm typeMeng Yu3-9/+24
Algorithm type is brought in to get hardware HPRE queue to support different algorithms. Signed-off-by: Meng Yu <yumeng18@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-03-13crypto: hisilicon/hpre - add version adapt to new algorithmsMeng Yu9-18/+19
A new generation of accelerator Kunpeng930 has appeared, and the corresponding driver needs to be updated to support some new algorithms of Kunpeng930. To be compatible with Kunpeng920, we add parameter 'struct hisi_qm *qm' to sec_algs_(un)register to identify the chip's version. Signed-off-by: Meng Yu <yumeng18@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - fix printing format issueWeili Qian2-9/+9
This patch fixes inconsistent of printing format with argument type. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - do not reset hardware when CE happensWeili Qian5-7/+24
There is no need to reset hardware when Corrected Error(CE) happens. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - update irqflagSihang Chen1-4/+3
There is no need to share IRQ among several devices, and set 'irqflag' as 0. Signed-off-by: Sihang Chen <chensihang1@hisilicon.com> Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - fix the value of 'QM_SQC_VFT_BASE_MASK_V2'Weili Qian1-1/+1
Since the size of base number is 16 bits, update the value of 'QM_SQC_VFT_BASE_MASK_V2' as 'GENMASK(15, 0)'. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - fix request missing errorWeili Qian1-0/+28
Add 'qp_stop_fail_cb' to ensure it is called as device is resetting. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - removing driver after resetWeili Qian5-20/+36
Add waiting logic for resetting as removing driver, otherwise call trace will occur due to releasing resource. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/hpre - enable Elliptic curve cryptographyHui Tang1-1/+8
Enable x25519/x448/ecdh/ecdsa/sm2 algorithm on Kunpeng 930. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon - PASID fixed on Kunpeng 930Weili Qian5-10/+24
Enable PASID by setting 'sqc' and 'cqc' pasid bits per queue in Kunpeng 930. For Kunpeng 920, PASID is effective for all queues once set in SVA scenarios. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/qm - fix use of 'dma_map_single'Weili Qian1-23/+27
Calling 'dma_map_single' after the data is written to ensure that the cpu cache and dma cache are consistent. Signed-off-by: Weili Qian <qianweili@huawei.com> Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/hpre - tiny fixHui Tang1-5/+8
Update since some special settings only for Kunpeng920. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-02-10crypto: hisilicon/hpre - adapt the number of clustersHui Tang2-27/+52
HPRE of Kunpeng 930 is updated on cluster numbers, so we try to update this driver to make it running okay on Kunpeng920/Kunpeng930 chips. Signed-off-by: Hui Tang <tanghui20@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-01-29crypto: hisilicon/hpre - add ecc algorithm inqury for uacce deviceHui Tang1-1/+4
Uacce SysFS support more algorithms inqury such as 'ecdh/ecdsa/sm2/x25519/x448' Signed-off-by: Hui Tang <tanghui20@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-01-29crypto: hisilicon/hpre - add two RAS correctable errors processingHui Tang1-2/+6
1.One CE error is detecting timeout of generating a random number. 2.Another is detecting timeout of SVA prefetching address. Signed-off-by: Hui Tang <tanghui20@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-01-29crypto: hisilicon/hpre - delete ECC 1bit error reported thresholdHui Tang1-2/+0
Delete 'HPRE_RAS_ECC1BIT_TH' register setting of hpre, since register 'QM_RAS_CE_THRESHOLD' of qm has done this work. Signed-off-by: Hui Tang <tanghui20@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-01-14crypto: hisilicon/sec - register SEC device to uacceKai Ye1-1/+38
Register SEC device to uacce framework for user space. Signed-off-by: Kai Ye <yekai13@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-01-14crypto: hisilicon/hpre - register HPRE device to uacceKai Ye1-0/+54
Register HPRE device to uacce framework for user space. Signed-off-by: Kai Ye <yekai13@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-01-14crypto: hisilicon - add ZIP device using mode parameterKai Ye3-1/+42
Add 'uacce_mode' parameter for ZIP, which can be set as 0(default) or 1. '0' means ZIP is only registered to kernel crypto, and '1' means it's registered to both kernel crypto and UACCE. Signed-off-by: Kai Ye <yekai13@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-01-14crypto: hisilicon/qm - SVA bugfixed on Kunpeng920Kai Ye1-0/+6
Kunpeng920 SEC/HPRE/ZIP cannot support running user space SVA and kernel Crypto at the same time. Therefore, the algorithms should not be registered to Crypto as user space SVA is enabled. Signed-off-by: Kai Ye <yekai13@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-12-11crypto: hisilicon/trng - replace atomic_add_return()Yejune Deng1-4/+4
a set of atomic_inc_return() looks more neater Signed-off-by: Yejune Deng <yejune.deng@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-27crypto: hisilicon/trng - add support for PRNGWeili Qian2-3/+239
This patch adds support for pseudo random number generator(PRNG) in Crypto subsystem. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-27crypto: hisilicon/trng - add HiSilicon TRNG driver supportWeili Qian4-0/+109
Move existing char/hw_random/hisi-trng-v2.c to crypto/hisilicon/trng.c. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-20crypto: hisilicon/zip - add a work_queue for zip irqYang Shen1-3/+23
The patch 'irqchip/gic-v3-its: Balance initial LPI affinity across CPUs' set the IRQ to an uncentain CPU. If an IRQ is bound to the CPU used by the thread which is sending request, the throughput will be just half. So allocate a 'work_queue' and set as 'WQ_UNBOUND' to do the back half work on some different CPUS. Signed-off-by: Yang Shen <shenyang39@huawei.com> Reviewed-by: Zaibo Xu <xuzaibo@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-20crypto: sha - split sha.h into sha1.h and sha2.hEric Biggers1-1/+2
Currently <crypto/sha.h> contains declarations for both SHA-1 and SHA-2, and <crypto/sha3.h> contains declarations for SHA-3. This organization is inconsistent, but more importantly SHA-1 is no longer considered to be cryptographically secure. So to the extent possible, SHA-1 shouldn't be grouped together with any of the other SHA versions, and usage of it should be phased out. Therefore, split <crypto/sha.h> into two headers <crypto/sha1.h> and <crypto/sha2.h>, and make everyone explicitly specify whether they want the declarations for SHA-1, SHA-2, or both. This avoids making the SHA-1 declarations visible to files that don't want anything to do with SHA-1. It also prepares for potentially moving sha1.h into a new insecure/ or dangerous/ directory. Signed-off-by: Eric Biggers <ebiggers@google.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-20crypto: hisilicon/sec2 - Fix aead authentication setting key errorKai Ye1-2/+3
Fix aead auth setting key process error. if use soft shash function, driver need to use digest size replace of the user input key length. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-06crypto: hisilicon/qm - split 'hisi_qm_init' into smaller piecesWeili Qian1-33/+53
'hisi_qm_init' initializes configuration of QM. To improve code readability, split it into two pieces. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-06crypto: hisilicon/qm - split 'qm_eq_ctx_cfg' into smaller piecesWeili Qian1-12/+32
'qm_eq_ctx_cfg' initializes configuration of EQ and AEQ, split it into two pieces to improve code readability. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2020-11-06crypto: hisilicon/qm - split 'qm_qp_ctx_cfg' into smaller piecesWeili Qian1-8/+28
'qm_qp_ctx_cfg' initializes configuration of SQ and CQ, split it into two pieces to improve code readability. Signed-off-by: Weili Qian <qianweili@huawei.com> Reviewed-by: Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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