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path: root/drivers/gpu/drm/amd/amdgpu
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2019-06-21drm/amdgpu: disable concurrent flushes for Navi10 v2Christian König1-2/+5
Navi10 have a bug in the SDMA which can theoretically cause memory corruption with concurrent VMID flushes v2: explicitely check Navi10 Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: refactor ip list traversalXiaojie Yuan1-29/+42
for each ip, check whether it is needed by amdgpu driver, if yes, record its base addresses v2: change some DRM_INFO to DRM_DEBUG v3: remove unused variable (Alex) Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: add module param for ip discovery enablementXiaojie Yuan3-0/+16
to control enablement. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: stop converting the units of base addressesXiaojie Yuan1-3/+3
the unit is already in dword Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: stop taking psp header into accountXiaojie Yuan1-6/+5
psp will write a header to vram, but the value exposed in RCC_CONFIG_MEMSIZE does not include the memory that this header is written to. Therefore, the interpretation of the table does not need to take the psp header into account. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: fix hwid for nbioXiaojie Yuan1-1/+1
Properly set this. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: use hardcoded mmRCC_CONFIG_MEMSIZEXiaojie Yuan1-6/+6
register base offset of nbio is not known before IP Discovery table is parsed, so hardcode this value. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: fix calculations of some gfx infoXiaojie Yuan1-4/+6
fix gfx info table handling. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/discovery: add ip discovery initial supportXiaojie Yuan4-1/+440
The IP discovery table lists is populated by the psp at power on and includes all of the hw details on the board: - List of IPs and MMIO offsets - IP harvest details - IP configuration details v2: prefix struct and function names with 'amdgpu' v3: read table binary from vram using mmMM_INDEX and mmMM_DATA update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR) add 'instance_number' field per ip info consider endianness and replace uint8/16/32_t with u8/16/32 initialize register base addresses initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw get major and minor version using a single api don't expose internal data structures in amdgpu_discovery.h v4: RCC_CONFIG_MEMSIZE is in MB units hold mmio_idx_lock while reading ip discovery binary v5: pick out discovery.h as a cross-OS header do structure pointer cast directly consider endianness while using the member of structure convert base addresses to dword at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the top of the frame buffer (just below the reserved regions for PSP & SMU). ip discovery data table includes the collection of each ip's identification number, base addresses, version number, and harvest setting placeholder. gc data table includes gfx info structure. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: mark the partial job as preempted in mcbp unit testJack Xiao1-12/+32
In mcbp unit test, the test should detect the preempted job which may be a partial execution ib and mark it as preempted; so that the gfx block can correctly generate PM4 frame. Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add mcbp unit test in debugfs (v3)Jack Xiao4-0/+161
The MCBP unit test is used to test the functionality of MCBP. It emualtes to send preemption request and resubmit the unfinished jobs. v2: squash in fixes (Alex) v3: squash in memory leak fix (Jack) Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: program for resuming preempted ibJack Xiao2-0/+2
For new submission ib, CE/DE metadata should be programmed to 0; for partially execution ib, CE/DE metadata should be restored. Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu/sdma: allocate CSA per sdma ringJack Xiao2-1/+28
Allocate CSA for the given sdma ring. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add ib preemption status in amdgpu_job (v2)Jack Xiao2-0/+4
Add ib preemption status in amdgpu_job, so that ring level function can detect preemption and program for resuming it. v2: squash in fix to restore job->preamble_status back to status value (Jack) Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: enable the static csa when mcbp enabledJack Xiao4-9/+11
CSA is the Context Save Area for preemption. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add mcbp driver parameterJack Xiao3-0/+9
Add mcbp driver parameter, so that mcbp feature can be enabled/disabled by driver parameter. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: Add new ring interface preempt_ibRex Zhu1-0/+2
Used to trigger preemtption Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: add the trailing fence per ringJack Xiao3-5/+27
The trailing fence for ring is used to track the completion of preemption. Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: Add helper function amdgpu_ring_set_preempt_cond_execRex Zhu1-0/+6
can preempt the ring by setting cond_exec to false Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-21drm/amdgpu: enable virtual display feature for navi10Le.Ma1-0/+1
Virtual display is a pure sw implementation of KMS for use in virtualization and for bring up and emulation. Signed-off-by: Le.Ma <Le.Ma@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp11: skip ta firmware for navi10Hawking Zhang1-24/+30
Not used on Navi10. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: declare navi10 asd firmwareHawking Zhang1-0/+1
So the dependencies are properly handled. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: load smc ucode at first with psp while rlc auto load is supportedHuang Rui1-7/+28
This patch loades smc ucode at first with psp while rlc auto load is supported on navi10. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: enable psp front door loading by default on navi10Hawking Zhang1-2/+1
Required for production hw and vddgfx. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: skip mec jt when autoload is enabledHawking Zhang1-0/+5
When autoload is enabled, there is no need to load mec jt, RLC will handle it automatically Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amd/amdgpu: add flag to mark whether autoload is supported or notHawking Zhang1-0/+2
rlc autoload is supported since navi10 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: initialize autoload_supported flag in psp_sw_initHawking Zhang1-0/+6
RLC autoload is supported since from Navi10 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: update psp gfx interface to match with psp fw (v2)Hawking Zhang1-30/+66
new psp gfx cmd is introuduced for rlc autoload v2: rebase (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: perform tmr_init and asd_init after loading sysdrv/sosHawking Zhang1-12/+12
Since from navi10, the tmr_size should be decided by psp sos according to toc header. Driver should issue LOAD_TOC to psp sos to get the tmr_size needed. The allocation of tmr_size then should be done only when sos/sysdrv loading completed Accordingly, asd_init also move to psp_hw_start after sos fw loading to make calling sequence consistent. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: switch to use sos_offset_bytes member as sys_bin_sizeHawking Zhang1-2/+1
Navi10 will have toc built-in sos binary so that using header.ucode_size_bytes minus sos_size_bytes actually is not sys_bin_size. Using sos_offset_bytes works for both vega20 (psp_firmware_header_v1_0) and navi10 (psp_firmware_header_v1_1) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: start rlc autoload after psp recieved all gfx firmwareHawking Zhang3-0/+39
RLC handles firmware loading for gfx to support vddgfx feature. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: add support to load TOC to pspHawking Zhang1-4/+53
Add support for the new load TOC command. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: add structure to support load toc in psp (v2)Hawking Zhang1-6/+18
Update the psp interface for the new commands. v2: rebase (Alex) FIXME: GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */ GFX_CMD_ID_LOAD_TOC = 0x0000000B, /* Load TOC and obtain TMR size */ Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: support print out psp firmware header v1_1 infoHawking Zhang1-0/+10
Support version 1.1. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: print out psp v11 ucode hdr in drm debug modeHawking Zhang1-0/+1
Print the psp header data if requested. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add helper function to print psp hdrHawking Zhang2-0/+25
print the psp header data like we do for other firmwares. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: rename rlc autoload to backdoor autoloadHawking Zhang1-1/+1
This is to differentiate rlc backdoor autoload from rlc frontdoor autoload Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: use rlc toc from psp sos binaryHawking Zhang1-0/+93
Instead of putting toc into driver source code, the toc will be part of psp_sos fw. Driver need to get and parse it from psp fw Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu/psp: support init psp sos microcode with build-in tocHawking Zhang2-8/+25
psp_firmware_header_v1_1 is used for psp sos with build-in toc Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add structure to support build-in toc to psp sosHawking Zhang2-0/+11
Table Of Content (TOC) is used by RLC to auto load gc firmwares. PSP need to parse the toc to calculate the tmr size needed and load gc firmwares to tmr for RLC to auto load them finally Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: Add psp 11.0 support for navi10.Tao Zhou2-4/+24
Add psp 11.0 code for navi10. psp 11.0 is not enabled for now. Will enable it when psp 11.0 firmware is available. Signed-off-by: Tao Zhou <Tao.Zhou1@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: set navi10's fw loading type as directHuang Rui1-0/+2
For bring up. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add fw load type flag for rlc autoloadLe.Ma1-0/+1
Add another firmware load type AMDGPU_FW_LOAD_RLC_AUTO to support firmware autoloading new feature in gfx10. This flag can be leveraged for future engines that need autoload fw. Signed-off-by: Le.Ma <Le.Ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add structures for buffer allocate/release for rlc autoloadLe.Ma1-0/+5
Allocate a visible framebuffer to store all gfxip ucodes as the format of TOC. Signed-off-by: Le.Ma <Le.Ma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add navi10 ih ip block (v3)Hawking Zhang3-1/+517
IH is the interrupt handler block. v1: add initial ih support (Ray) v2: add dummy prescreen iv function for navi10 (Hawking) v3: squash in additional updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add gmc v10 ip block for navi10 (v6)Hawking Zhang3-1/+947
GMC in the GPU memory controller. v1: add place holder and initial basic implementation (Ray) v2: retire unused amdgpu_gart_set_defaults (Hawking) v3: re-work get_vm_pde function (Hawking) v4: replace legacy amdgpu_vram/gtt_location with amdgpu_gmc_vram/gtt_location (Hawking) v5: squash in updates (Alex) v6: use get_vbios_fb_size (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add mmhub v2 block for navi10 (v4)Hawking Zhang3-1/+478
mmhub is the memory controller hub for multi-media (VCN). v1: add place holder and initial functions (Ray) v2: replace legacy amdgpu_mc structure with amdgpu_gmc (Hawking) v3: switch to use amdgpu_gmc_pd_addr (Hawking) v4: squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: add gfxhub v2.0 block for navi10 (v4)Hawking Zhang3-1/+389
gfxhub is the memory controller hub for gfx and sdma. v1: add place holder and initial basic functions (Ray) v2: replace the refernce to legacy mc structure with gmc structure remove the direct use of gart.table_addr (Hawking) v3: switch to use amdgpu_gmc_pd_addr (Hawking) v4: squash in updates (Alex) Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amdgpu: refine the PTE encoding of PRT for navi10Jack Xiao2-0/+7
Due to GCR change from navi10, the PTE encoding of PRT needs change VSCTL = 01111 (was 0XX1X). Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-20drm/amd/gmc9: rename AMDGPU_PTE_MTYPE to AMDGPU_PTE_MTYPE_VG10Hawking Zhang4-14/+14
To differentiate the mtypes across asics. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-12-15 21:11:01 +0000