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path: root/drivers/gpu/drm/i915/display/intel_psr.c
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2024-09-16drm/i915/dp: Fix AUX IO power enabling for eDP PSRImre Deak1-0/+19
Panel Self Refresh on eDP requires the AUX IO power to be enabled whenever the output (main link) is enabled. This is required by the AUX_PHY_WAKE/ML_PHY_LOCK signaling initiated by the HW automatically to re-enable the main link after it got disabled in power saving states (see eDP v1.4b, sections 5.1, 6.1.3.3.1.1). The Panel Replay mode on non-eDP outputs on the other hand is only supported by keeping the main link active, thus not requiring the above AUX_PHY_WAKE/ML_PHY_LOCK signaling (eDP v1.4b, section 6.1.3.3.1.2). Thus enabling the AUX IO power for this case is not required either. Based on the above enable the AUX IO power only for eDP/PSR outputs. Bspec: 49274, 53370 v2: - Add a TODO comment to adjust the requirement for AUX IO based on whether the ALPM/main-link off mode gets enabled. (Rodrigo) Cc: Animesh Manna <animesh.manna@intel.com> Fixes: b8cf5b5d266e ("drm/i915/panelreplay: Initializaton and compute config for panel replay") Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240910111847.2995725-1-imre.deak@intel.com (cherry picked from commit f7c2ed9d4ce80a2570c492825de239dc8b500f2e) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2024-09-16drm/i915/psr: Do not wait for PSR being idle on on Panel ReplayJouni Högander1-11/+2
We do not have ALPM on DP Panel Replay. Due to this SRD_STATUS[SRD State] doesn't change from SRDENT_ON after Panel Replay is enabled until it gets disabled. On eDP Panel Replay DEEP_SLEEP is not reached. _psr2_ready_for_pipe_update_locked is waiting DEEP_SLEEP bit getting reset. Take these into account in Panel Replay code by not waiting PSR getting idle after enabling VBI. Fixes: 29fb595d4875 ("drm/i915/psr: Panel replay uses SRD_STATUS to track it's status") Cc: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240906070033.289015-5-jouni.hogander@intel.com (cherry picked from commit a2d98feb4b0013ef4f9db0d8f642a8ac1f5ecbb9) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2024-09-03drm/i915/psr: convert intel_psr.[ch] to struct intel_displayJani Nikula1-404/+444
Going forward, struct intel_display shall replace struct drm_i915_private as the main display device data pointer type. Convert intel_psr.[ch] to struct intel_display. Some stragglers are left behind where needed. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/4399b98b07019a8063adbec1043ff7eabb7c1080.1725012870.git.jani.nikula@intel.com
2024-08-22drm/i915/display: rename IS_DISPLAY_IP_STEP() to IS_DISPLAY_VER_STEP()Jani Nikula1-4/+4
Unify macro naming on VER. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6861e02f3adf15d56e89890000eb195070c33c9b.1724180287.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-08-21drm/i915/psr: Prevent Panel Replay if CRC calculation is enabledJouni Högander1-0/+6
Similarly as for PSR2 CRC calculation seems to timeout when Panel Replay is enabled. Fix this by falling back to PSR if CRC calculation is enabled. Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2266 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240819092549.1298233-1-jouni.hogander@intel.com
2024-06-25drm/i915/psr: Modify dg2_activate_panel_replay to support eDPJouni Högander1-0/+13
There are couple of bits in PSR2_CTL which needs to be written in case of eDP Panel Replay Bspec: 68920 v2: use boolean instead of assuming eDP Panel Replay mean Early Transport Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-12-jouni.hogander@intel.com
2024-06-25drm/i915/psr: Check Early Transport for Panel Replay as wellJouni Högander1-3/+3
Move Early Transport validity check to be performed for Panel Replay as well and use Early Transport for eDP Panel Replay always. v2:set crtc_state->enable_psr2_su_region_et directly (not in if block) Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-11-jouni.hogander@intel.com
2024-06-25drm/i915/psr: Perform scanline indication check for Panel Replay as wellJouni Högander1-6/+6
Scanline indication needs to be checked and configure for both PSR2 and Panel Replay Selective Update. Move this check to intel_sel_update_config_valid. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-10-jouni.hogander@intel.com
2024-06-25drm/i915/psr: Perform psr2 checks related to ALPM for Panel ReplayJouni Högander1-13/+28
eDP1.5 support ALPM with Panel Replay as well. We need to check ALPM related things for Panel Replay as well. Bspec: 68920 v5: - instead of using crtc_state->has_panel_replay provide aux_less flag v4: - do not move _compute_psr2_sdp_prior_scanline_indication - move ALPM related checks to separate function v3: move vblank check as well v2: do not move Vblank >= PSR2_CTL Block Count Number maximum line count check Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-9-jouni.hogander@intel.com
2024-06-25drm/i915/psr: HW will not allow PR on eDP when HDCP enabledJouni Högander1-0/+14
Take into account in Panel Replay compute config that HW will not allow PR on eDP when HDCP enabled. v2: add debug message to print out why Panel Replay is not possible Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-7-jouni.hogander@intel.com
2024-06-25drm/i915/psr: 128b/132b Panel Replay is not supported on eDPJouni Högander1-2/+19
Take into account that 128b/132b Panel Replay is not supported on eDP. Bspec: 68920 v2: - make crtc_state as const - add debug message to print out why Panel Replay is not possible Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-6-jouni.hogander@intel.com
2024-06-25drm/i915/psr: Check panel Early Transport capability for eDP PRJouni Högander1-5/+12
Our HW doesn't support panel replay without Early Transport on eDP. Bspec: 68920 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-5-jouni.hogander@intel.com
2024-06-25drm/i915/psr: enable sink for eDP1.5 Panel ReplayJouni Högander1-6/+30
eDP1.5 allows Panel Replay on eDP as well. Take this into account when enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register accordingly. v3: - set DP_PANEL_REPLAY_CRC_VERIFICATION in PANEL_REPLAY_CONFIG2 - PANEL_REPLAY_CONFIG2 is available in DP2.1 as well v2: do not configure ALPM for DP2.0 Panel Replay Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-4-jouni.hogander@intel.com
2024-06-25drm/i915/psr: Inform Panel Replay source support on eDP as wellJouni Högander1-2/+4
Display version >= 20 support eDP 1.5. Inform Panel Replay source support on eDP for display version >= 20. Bspec: 68920 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-3-jouni.hogander@intel.com
2024-06-25drm/i915/psr: Check panel ALPM capability for eDP Panel ReplayJouni Högander1-0/+7
Our HW doesn't support Panel Replay without AUX_LESS ALPM on eDP. Check panel support for this and prevent eDP panel replay if it doesn't exits. Bspec: 68920 v3: remove excessive parens v2: use intel_alpm_aux_less_wake_supported Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240619062131.4021196-2-jouni.hogander@intel.com
2024-06-24drm/i915/psr: Set DP_PSR_SU_REGION_SCANLINE_CAPTURE bit when neededJouni Högander1-0/+3
Setting DP_PSR_SU_REGION_SCANLINE_CAPTURE (Selective Update Region Scan Line Capture Indication in spec) bit was dropped when psr_enable_sink was split to _psr_enable_sink and _panel_replay_enable_sink. Add setting it back. Fixes: 32f0045f905c ("drm/i915/psr: Split enabling sink for PSR and Panel Replay") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240620103312.903977-1-jouni.hogander@intel.com
2024-06-19Revert "drm/i915/psr: Disable early transport by default"Jouni Högander1-3/+0
This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d. We want to notice possible issues faced with PSR2 Region Early Transport as early as possible -> let's revert patch disabling Region Early Transport by default. Also eDP 1.5 Panel Replay requires Early Transport. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-9-jouni.hogander@intel.com
2024-06-19drm/i915/psr: Add new debug bit to disable Panel ReplayJouni Högander1-3/+8
Add new debug bit to be used with i915_edp_psr_debug debugfs interface. This can be used to disable Panel Replay. v2: ensure that fastset is performed when the bit changes Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-8-jouni.hogander@intel.com
2024-06-19drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR onlyJouni Högander1-6/+6
Enabling/disabling Panel Replay on sink side has to be done before link training. We can't disable it in sink side on PSR disable. Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-7-jouni.hogander@intel.com
2024-06-19drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is setJouni Högander1-1/+12
Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake if panel supports it despite enable_psr module parameter value. This patch makes it possible for user to limit used PSR mode and prevent SU Region Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU Region Early Transport is allowed. v2: fix/improve commit desciption Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-6-jouni.hogander@intel.com
2024-06-19drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameterJouni Högander1-2/+25
If user is specifically limiting PSR mode to PSR1 or PSR2: disable Panel Replay. With default value -1 all modes are allowed including Panel Replay. Disabling PSR using value 0 disables Panel Replay as well. Also own compute config helper is added for Panel Replay. This makes sense because number of Panel Replay specific checks are increasing. v2: Squash adding Panel Replay compute config helper Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-5-jouni.hogander@intel.com
2024-06-19drm/i915/display: Wa 16021440873 is writing wrong registerJouni Högander1-9/+3
Wa 16021440873 is writing wrong register. Instead of PIPE_SRCSZ_ERLY_TPT write CURPOS_ERLY_TPT. v2: use right offset as well Fixes: 29cdef8539c3 ("drm/i915/display: Implement Wa_16021440873") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-3-jouni.hogander@intel.com
2024-06-19drm/i915/psr: Set SU area width as pipe src widthJouni Högander1-1/+1
Currently SU area width is set as MAX_INT. This is causing problems. Instead set it as pipe src width. Fixes: 86b26b6aeac7 ("drm/i915/psr: Carry su area in crtc_state") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-2-jouni.hogander@intel.com
2024-06-12drm/i915: Rename all bigjoiner to joinerStanislav Lisovskiy1-3/+3
Lets unify both bigjoiner and ultrajoiner under simple "joiner" name, because in future we might have multiple configurations, involving multiple bigjoiners, ultrajoiner, however it is possible to use same api for handling both. v2: - Renamed back some bigjoiner specific parts for now(Ville) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> [vsyrjala: Catch a few more cases] Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607075457.15700-1-stanislav.lisovskiy@intel.com
2024-06-11drm/i915/psr: Wake time is aux less wake time for Panel ReplayJouni Högander1-2/+6
When checking vblank length used wake time is aux less wake time for eDP Panel Replay (vblank length is not checked for DP2.0 Panel Replay). Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-14-jouni.hogander@intel.com
2024-06-11drm/i915/psr: Check vblank against IO buffer wake time on LunarlakeJouni Högander1-1/+5
As Lunarlake doesn't have block count configuration vblank should be checked against IO buffer wake time. Bspec: 68920 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-13-jouni.hogander@intel.com
2024-06-11drm/i915/psr: Take into account SU SDP scanline indication in vblank checkJouni Högander1-0/+3
SU SDP scanline indication should be taken into account when checking vblank length. In Bspec we have: PSR2_CTL[ SU SDP scanline indication ] = 0: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start) > PSR2_CTL Block Count Number value in lines PSR2_CTL[ SU SDP scanline indication ] = 1: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start- 1) > PSR2_CTL Block Count Number value in lines Bspec: 49274 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-12-jouni.hogander@intel.com
2024-06-11drm/i915/psr: Move vblank length check to separate functionJouni Högander1-3/+15
We are about to add more complexity to vblank length check. It makes sense to move it to separate function for sake of clarity. v2: change name to wake_lines_fit_into_vblank Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-11-jouni.hogander@intel.com
2024-06-11drm/i915/psr: Print Panel Replay status instead of frame lock statusJouni Högander1-17/+5
Currently Panel Replay status printout is printing frame lock status. It should print Panel Replay status instead. Panel Replay status register field follows PSR status register field. Use existing PSR code for that. Fixes: ef75c25e8fed ("drm/i915/panelreplay: Debugfs support for panel replay") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-10-jouni.hogander@intel.com
2024-06-11drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_validJouni Högander1-7/+8
Early Transport is possible and in our HW mandatory on eDP Panel Replay. Add parameter to intel_psr2_config_et_valid to differentiate validity check for Panel Replay. v2: fix intel_dp->psr_dpcd[0] check Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-9-jouni.hogander@intel.com
2024-06-11drm/i915/alpm: Share alpm support checks with PSR codeJouni Högander1-12/+2
Convert intel_alpm_aux_wake_supported and intel_alpm_aux_less_wake_supported as non-static. Use them in intel_psr.c instead of local variables. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-8-jouni.hogander@intel.com
2024-06-11drm/i915/psr: Split enabling sink for PSR and Panel ReplayJouni Högander1-37/+44
Current intel_psr_enable_sink is a mess due to partly reusing PSR bit definitions for Panel Replay. Even thought PSR and Panel Replay enable registers do have common bits they still have also different bits and same bits with different meaning. For sake of clarity split enabling sink to PSR and Panel Replay specific parts. Also fix issue caused by using psr->panel_replay_enabled to early. Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-7-jouni.hogander@intel.com
2024-06-07drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANSJani Nikula1-2/+3
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the MTL_CLKGATE_DIS_TRANS register macro. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/b330d86c5e3012513daa36dceffd2db45f0d7850.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2024-06-03drm/i915/psr: Add Early Transport into psr debugfs interfaceJouni Högander1-8/+27
We want to have sink Early Transport capability and usage in our psr debugfs status interface. v4: use su_region_et_enabled instead of psr2_su_region_et_valid v3: remove extra space from "PSR mode: disabled" v2: printout "Selective Update enabled (Early Transport)" instead of "Selective Update Early Transport enabled" Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-7-jouni.hogander@intel.com
2024-06-03drm/i915/psr: Allow setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE via debugfsJouni Högander1-3/+10
Currently setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE (0x20) via psr_debug debugfs interface is not allowed. This patch allows it. v3: - ensure psr is disabled/enabled if enable_psr2_su_region_et changes - remove extra space v2: ensure that fastset is performed when the bit changes Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-6-jouni.hogander@intel.com
2024-06-03drm/i915/psr: Use enable boolean from intel_crtc_state for Early TransportJouni Högander1-1/+1
When enabling Early Transport use intel_crtc_state->enable_psr2_su_region_et instead of psr2_su_region_et_valid. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-4-jouni.hogander@intel.com
2024-06-03drm/i915/psr: Get Early Transport status in intel_psr_pipe_get_configJouni Högander1-0/+2
We are currently not getting Early Transport status information in intel_psr_pipe_get_config. Fix this. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-3-jouni.hogander@intel.com
2024-06-03drm/i915/psr: Add Early Transport status boolean into intel_psrJouni Högander1-1/+3
Currently we are purely relying on psr2_su_region_et_valid. Add new boolean value into intel_psr struct indicating whether Early Transport is enabled or not and use it instead of psr2_su_region_et_valid for getting Early Transport status information. Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-2-jouni.hogander@intel.com
2024-05-31drm/i915/alpm: Enable lobf from source in ALPM_CTLAnimesh Manna1-1/+1
Set the Link Off Between Frames Enable bit in ALPM_CTL register. Note: Lobf need to be enabled adaptive sync fixed refresh mode where vmin = vmax = flipline, which will arise after cmmr feature enablement. Will add enabling sequence in a separate patch. v1: Initial version. v2: Condition check modified in alpm_configure(). [Jouni] Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-6-animesh.manna@intel.com
2024-05-31drm/i915/alpm: Move alpm related code to a new fileAnimesh Manna1-280/+3
Move ALPM feature related code as it will be used for non-psr panel also thorugh LOBF feature. v1: Initial version. v2: Correct ordering in makefile. [Jani] Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-3-animesh.manna@intel.com
2024-05-31drm/i915/alpm: Move alpm parameters from intel_psrAnimesh Manna1-23/+21
ALPM can be enabled for non psr panel and currenly aplm-params are encapsulated under intel_psr struct, so moving out to intel_dp struct. Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-2-animesh.manna@intel.com
2024-05-29drm/i915/psr: modify psr status debugfs to support eDP Panel ReplayJouni Högander1-1/+10
Some PSR2_CTL bits are applicable for eDP panel replay as well. Dump this register for eDP Panel Replay as well. Bspec: 68920 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-6-jouni.hogander@intel.com
2024-05-29drm/i915/psr: Move printing PSR mode to own functionJouni Högander1-9/+17
intel_psr_status has grown and is about to grow even. Let's split it a bit and move printing PSR mode to an own function. v2: s/intel_psr_psr_mode/intel_psr_print_mode/ Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-5-jouni.hogander@intel.com
2024-05-29drm/i915/psr: Move printing sink PSR support to own functionJouni Högander1-7/+15
intel_psr_status has grown and is about to grow even. Let's split it a bit and move printing sink psr support to an own function. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-4-jouni.hogander@intel.com
2024-05-29drm/i915/psr: Store pr_dpcd in intel_dpJouni Högander1-13/+6
We need pr_dpcd contents for early transport validity check on eDP Panel Replay and in debugfs interface to dump out panel early transport capability. Also remove unnecessarily printing out "Panel replay is not supported by panel" v2: commit message modified Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-2-jouni.hogander@intel.com
2024-05-22drm/i915: Simplify PIPESRC_ERLY_TPT definitionVille Syrjälä1-1/+1
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range. so using _MMIO_TRANS2() for it is not really correct. Also since this is a pipe register, and not present on CHV, the registers will be equally spaced out, so we can use the simpler _MMIO_PIPE() instead of _MMIO_PIPE2(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2024-05-20drm/i915/psr: PSR2_CTL[Block Count Number] not needed for LunarLakeJouni Högander1-1/+1
PSR2_CTL[Block Count Number] is not used by LunarLake do not configure it. Bspec: 69885 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-4-jouni.hogander@intel.com
2024-05-20drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wideJouni Högander1-0/+2
On LunarLake PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this into account when enabling PSR2_CTL. Bspec: 69885 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-3-jouni.hogander@intel.com
2024-05-20drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are 68Jouni Högander1-2/+3
On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits + 5 lines added by the HW. Take this into account in calculation and when writing the IO Wake lines. v2: maximum line count is 68 (6 bits + 5 lines added by HW) Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-2-jouni.hogander@intel.com
2024-05-16drm/i915: pass dev_priv explicitly to CURSURFLIVEJani Nikula1-4/+9
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURSURFLIVE register macro. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/86aa98ad9f883681f5c2e3aba839d02d8591bfbf.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-09 23:54:23 +0000