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2024-11-01PCI: Hold rescan lock while adding devices during host probeBartosz Golaszewski1-0/+2
[ Upstream commit 1d59d474e1cb7d4fdf87dfaf96f44647f13ea590 ] Since adding the PCI power control code, we may end up with a race between the pwrctl platform device rescanning the bus and host controller probe functions. The latter need to take the rescan lock when adding devices or we may end up in an undefined state having two incompletely added devices and hit the following crash when trying to remove the device over sysfs: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 Internal error: Oops: 0000000096000004 [#1] SMP Call trace: __pi_strlen+0x14/0x150 kernfs_find_ns+0x80/0x13c kernfs_remove_by_name_ns+0x54/0xf0 sysfs_remove_bin_file+0x24/0x34 pci_remove_resource_files+0x3c/0x84 pci_remove_sysfs_dev_files+0x28/0x38 pci_stop_bus_device+0x8c/0xd8 pci_stop_bus_device+0x40/0xd8 pci_stop_and_remove_bus_device_locked+0x28/0x48 remove_store+0x70/0xb0 dev_attr_store+0x20/0x38 sysfs_kf_write+0x58/0x78 kernfs_fop_write_iter+0xe8/0x184 vfs_write+0x2dc/0x308 ksys_write+0x7c/0xec Fixes: 4565d2652a37 ("PCI/pwrctl: Add PCI power control core code") Link: https://lore.kernel.org/r/20241003084342.27501-1-brgl@bgdev.pl Reported-by: Konrad Dybcio <konradybcio@kernel.org> Tested-by: Konrad Dybcio <konradybcio@kernel.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
2024-10-17PCI: Pass domain number to pci_bus_release_domain_nr() explicitlyManivannan Sadhasivam1-1/+1
commit 0cca961a026177af69044f10d6ae76d8ce043764 upstream. The pci_bus_release_domain_nr() API is supposed to free the domain number allocated by pci_bus_find_domain_nr(). Most of the callers of pci_bus_find_domain_nr(), store the domain number in pci_bus::domain_nr. As such, the pci_bus_release_domain_nr() implicitly frees the domain number by dereferencing 'struct pci_bus'. However, one of the callers of this API, the PCI endpoint subsystem, doesn't have 'struct pci_bus', so it only passes NULL. Due to this, the API will end up dereferencing the NULL pointer. To fix this issue, pass the domain number to this API explicitly. Since 'struct pci_bus' is not used for anything else other than extracting the domain number, it makes sense to pass the domain number directly. Fixes: 0328947c5032 ("PCI: endpoint: Assign PCI domain number for endpoint controllers") Closes: https://lore.kernel.org/linux-pci/c0c40ddb-bf64-4b22-9dd1-8dbb18aa2813@stanley.mountain Link: https://lore.kernel.org/linux-pci/20240912053025.25314-1-manivannan.sadhasivam@linaro.org Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> [kwilczynski: commit log] Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-07-19Merge tag 'pci-v6.11-changes' of ↵Linus Torvalds1-11/+23
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Define PCIE_RESET_CONFIG_DEVICE_WAIT_MS for the generic 100ms required after reset before config access (Kevin Xie) - Define PCIE_T_RRS_READY_MS for the generic 100ms required after reset before config access (probably should be unified with PCIE_RESET_CONFIG_DEVICE_WAIT_MS) (Damien Le Moal) Resource management: - Rename find_resource() to find_resource_space() to be more descriptive (Ilpo Järvinen) - Export find_resource_space() for use by PCI core, which needs to learn whether there is available space for a bridge window (Ilpo Järvinen) - Prevent double counting of resources so window size doesn't grow on each remove/rescan cycle (Ilpo Järvinen) - Relax bridge window sizing algorithm so a device doesn't break simply because it was removed and rescanned (Ilpo Järvinen) - Evaluate the ACPI PRESERVE_BOOT_CONFIG _DSM in pci_register_host_bridge() (not acpi_pci_root_create()) so we can unify it with similar DT functionality (Vidya Sagar) - Extend use of DT "linux,pci-probe-only" property so it works per-host bridge as well as globally (Vidya Sagar) - Unify support for ACPI PRESERVE_BOOT_CONFIG _DSM and the DT "linux,pci-probe-only" property in pci_preserve_config() (Vidya Sagar) Driver binding: - Add devres infrastructure for managed request and map of partial BAR resources (Philipp Stanner) - Deprecate pcim_iomap_table() because uses like "pcim_iomap_table()[0]" have no good way to return errors (Philipp Stanner) - Add an always-managed pcim_request_region() for use instead of pci_request_region() and similar, which are sometimes managed depending on whether pcim_enable_device() has been called previously (Philipp Stanner) - Reimplement pcim_set_mwi() so it doesn't need to keep store MWI state (Philipp Stanner) - Add pcim_intx() for use instead of pci_intx(), which is sometimes managed depending on whether pcim_enable_device() has been called previously (Philipp Stanner) - Add managed pcim_iomap_range() to allow mapping of a partial BAR (Philipp Stanner) - Fix a devres mapping leak in drm/vboxvideo (Philipp Stanner) Error handling: - Add missing bridge locking in device reset path and add a warning for other possible lock issues (Dan Williams) - Fix use-after-free on concurrent DPC and hot-removal (Lukas Wunner) Power management: - Disable AER and DPC during suspend to avoid spurious wakeups if they share an interrupt with PME (Kai-Heng Feng) PCIe native device hotplug: - Detect if a device was removed or replaced during system sleep so we don't assume a new device is the one that used to be there (Lukas Wunner) Virtualization: - Add an ACS quirk for Broadcom BCM5760X multi-function NIC; it prevents transactions between functions even though it doesn't advertise ACS, so the functions can be attached individually via VFIO (Ajit Khaparde) Peer-to-peer DMA: - Add a "pci=config_acs=" kernel command-line parameter to relax default ACS settings to enable additional peer-to-peer configurations. Requires expert knowledge of topology and ACS operation (Vidya Sagar) Endpoint framework: - Remove unused struct pci_epf_group.type_group (Christophe JAILLET) - Fix error handling in vpci_scan_bus() and epf_ntb_epc_cleanup() (Dan Carpenter) - Make struct pci_epc_class constant (Greg Kroah-Hartman) - Remove unused pci_endpoint_test_bar_{readl,writel} functions (Jiapeng Chong) - Rename "BME" to "Bus Master Enable" (Manivannan Sadhasivam) - Rename struct pci_epc_event_ops.core_init() callback to epc_init() (Manivannan Sadhasivam) - Move DMA init to MHI .epc_init() callback for uniformity (Manivannan Sadhasivam) - Cancel EPF test delayed work when link goes down (Manivannan Sadhasivam) - Add struct pci_epc_event_ops.epc_deinit() callback for cleanup needed on fundamental reset (Manivannan Sadhasivam) - Add 64KB alignment to endpoint test to support Rockchip rk3588 (Niklas Cassel) - Optimize endpoint test by using memcpy() instead of readl() (Niklas Cassel) Device tree bindings: - Add generic "ats-supported" property to advertise that a PCIe Root Complex supports ATS (Jean-Philippe Brucker) Amazon Annapurna Labs PCIe controller driver: - Validate IORESOURCE_BUS presence to avoid NULL pointer dereference (Aleksandr Mishin) Axis ARTPEC-6 PCIe controller driver: - Rename .cpu_addr_fixup() parameter to reflect that it is a PCI address, not a CPU address (Niklas Cassel) Freescale i.MX6 PCIe controller driver: - Convert to agnostic GPIO API (Andy Shevchenko) Freescale Layerscape PCIe controller driver: - Make struct mobiveil_rp_ops constant (Christophe JAILLET) - Use new generic dw_pcie_ep_linkdown() to handle link-down events (Manivannan Sadhasivam) HiSilicon Kirin PCIe controller driver: - Convert to agnostic GPIO API (Andy Shevchenko) - Use _scoped() iterator for OF children to ensure refcounts are decremented at loop exit (Javier Carrasco) Intel VMD host bridge driver: - Create sysfs "domain" symlink before downstream devices are exposed to userspace by pci_bus_add_devices() (Jiwei Sun) Loongson PCIe controller driver: - Enable MSI when LS7A is used with new CPUs that have integrated PCIe Root Complex, e.g., Loongson-3C6000, so downstream devices can use MSI (Huacai Chen) Microchip AXI PolarFlare PCIe controller driver: - Move pcie-microchip-host.c to a new PLDA directory (Minda Chen) - Factor PLDA generic items out to a common plda,xpressrich3-axi-common.yaml binding (Minda Chen) - Factor PLDA generic data structures and code out to shared pcie-plda.h, pcie-plda-host.c (Minda Chen) - Add PLDA generic interrupt handling with a .request_event_irq() callback for vendor-specific events (Minda Chen) - Add PLDA generic host init/deinit and map bus functions for use by vendor-specific drivers (Minda Chen) - Rework to use PLDA core (Minda Chen) Microsoft Hyper-V host bridge driver: - Return zero, not garbage, when reading PCI_INTERRUPT_PIN (Wei Liu) NVIDIA Tegra194 PCIe controller driver: - Remove unused struct tegra_pcie_soc (Dr. David Alan Gilbert) - Set 64KB inbound ATU alignment restriction (Jon Hunter) Qualcomm PCIe controller driver: - Make the MHI reg region mandatory for X1E80100, since all PCIe controllers have it (Abel Vesa) - Prevent use of uninitialized data and possible error pointer dereference (Dan Carpenter) - Return error, not success, if dev_pm_opp_find_freq_floor() fails (Dan Carpenter) - Add Operating Performance Points (OPP) support to scale performance state based on aggregate link bandwidth to improve SoC power efficiency (Krishna chaitanya chundru) - Vote for the CPU-PCIe ICC (interconnect) path to ensure it stays active even if other drivers don't vote for it (Krishna chaitanya chundru) - Use devm_clk_bulk_get_all() to get all the clocks from DT to avoid writing out all the clock names (Manivannan Sadhasivam) - Add DT binding and driver support for the SA8775P SoC (Mrinmay Sarkar) - Add HDMA support for the SA8775P SoC (Mrinmay Sarkar) - Override the SA8775P NO_SNOOP default to avoid possible memory corruption (Mrinmay Sarkar) - Make sure resources are disabled during PERST# assertion, even if the link is already disabled (Manivannan Sadhasivam) - Use new generic dw_pcie_ep_linkdown() to handle link-down events (Manivannan Sadhasivam) - Add DT and endpoint driver support for the SA8775P SoC (Mrinmay Sarkar) - Add Hyper DMA (HDMA) support for the SA8775P SoC and enable it in the EPF MHI driver (Mrinmay Sarkar) - Set PCIE_PARF_NO_SNOOP_OVERIDE to override the default NO_SNOOP attribute on the SA8775P SoC (both Root Complex and Endpoint mode) to avoid possible memory corruption (Mrinmay Sarkar) Renesas R-Car PCIe controller driver: - Demote WARN() to dev_warn_ratelimited() in rcar_pcie_wakeup() to avoid unnecessary backtrace (Marek Vasut) - Add DT and driver support for R-Car V4H (R8A779G0) host and endpoint. This requires separate proprietary firmware (Yoshihiro Shimoda) Rockchip PCIe controller driver: - Assert PERST# for 100ms after power is stable (Damien Le Moal) - Wait PCIE_T_RRS_READY_MS (100ms) after reset before starting configuration (Damien Le Moal) - Use GPIOD_OUT_LOW flag while requesting ep_gpio to fix a firmware crash on Qcom-based modems with Rockpro64 board (Manivannan Sadhasivam) Rockchip DesignWare PCIe controller driver: - Factor common parts of rockchip-dw-pcie DT binding to be shared by Root Complex and Endpoint mode (Niklas Cassel) - Add missing INTx signals to common DT binding (Niklas Cassel) - Add eDMA items to DT binding for Endpoint controller (Niklas Cassel) - Fix initial dw-rockchip PERST# GPIO value to prevent unnecessary short assert/deassert that causes issues with some WLAN controllers (Niklas Cassel) - Refactor dw-rockchip and add support for Endpoint mode (Niklas Cassel) - Call pci_epc_init_notify() and drop dw_pcie_ep_init_notify() wrapper (Niklas Cassel) - Add error messages in .probe() error paths to improve user experience (Uwe Kleine-König) Samsung Exynos PCIe controller driver: - Use bulk clock APIs to simplify clock setup (Shradha Todi) StarFive PCIe controller driver: - Add DT binding and driver support for the StarFive JH7110 PLDA-based PCIe controller (Minda Chen) Synopsys DesignWare PCIe controller driver: - Add generic support for sending PME_Turn_Off when system suspends (Frank Li) - Fix incorrect interpretation of iATU slot 0 after PERST# assert/deassert (Frank Li) - Use msleep() instead of usleep_range() while waiting for link (Konrad Dybcio) - Refactor dw_pcie_edma_find_chip() to enable adding support for Hyper DMA (HDMA) (Manivannan Sadhasivam) - Enable drivers to supply the eDMA channel count since some can't auto detect this (Manivannan Sadhasivam) - Call pci_epc_init_notify() and drop dw_pcie_ep_init_notify() wrapper (Manivannan Sadhasivam) - Pass the eDMA mapping format directly from drivers instead of maintaining a capability for it (Manivannan Sadhasivam) - Add generic dw_pcie_ep_linkdown() to notify EPF drivers about link-down events and restore non-sticky DWC registers lost on link down (Manivannan Sadhasivam) - Add vendor-specific "apb" reg name, interrupt names, INTx names to generic binding (Niklas Cassel) - Enforce DWC restriction that 64-bit BARs must start with an even-numbered BAR (Niklas Cassel) - Consolidate args of dw_pcie_prog_outbound_atu() into a structure (Yoshihiro Shimoda) - Add support for endpoints to send Message TLPs, e.g., for INTx emulation (Yoshihiro Shimoda) TI DRA7xx PCIe controller driver: - Rename .cpu_addr_fixup() parameter to reflect that it is a PCI address, not a CPU address (Niklas Cassel) TI Keystone PCIe controller driver: - Validate IORESOURCE_BUS presence to avoid NULL pointer dereference (Aleksandr Mishin) - Work around AM65x/DRA80xM Errata #i2037 that corrupts TLPs and causes processor hangs by limiting Max_Read_Request_Size (MRRS) and Max_Payload_Size (MPS) (Kishon Vijay Abraham I) - Leave BAR 0 disabled for AM654x to fix a regression caused by 6ab15b5e7057 ("PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus"), which caused a 45-second boot delay (Siddharth Vadapalli) Xilinx Versal CPM PCIe controller driver: - Fix overlapping bridge registers and 32-bit BAR addresses in DT binding (Thippeswamy Havalige) MicroSemi Switchtec management driver: - Make struct switchtec_class constant (Greg Kroah-Hartman) Miscellaneous: - Remove unused struct acpi_handle_node (Dr. David Alan Gilbert) - Add missing MODULE_DESCRIPTION() macros (Jeff Johnson)" * tag 'pci-v6.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (154 commits) PCI: loongson: Enable MSI in LS7A Root Complex PCI: Extend ACS configurability PCI: Add missing bridge lock to pci_bus_lock() drm/vboxvideo: fix mapping leaks PCI: Add managed pcim_iomap_range() PCI: Remove legacy pcim_release() PCI: Add managed pcim_intx() PCI: vmd: Create domain symlink before pci_bus_add_devices() PCI: qcom: Prevent use of uninitialized data in qcom_pcie_suspend_noirq() PCI: qcom: Prevent potential error pointer dereference PCI: qcom: Fix missing error code in qcom_pcie_probe() PCI: Give pcim_set_mwi() its own devres cleanup callback PCI: Move struct pci_devres.pinned bit to struct pci_dev PCI: Remove struct pci_devres.enabled status bit PCI: Document hybrid devres hazards PCI: Add managed pcim_request_region() PCI: Deprecate pcim_iomap_table(), pcim_iomap_regions_request_all() PCI: Add managed partial-BAR request and map infrastructure PCI: Add devres helpers for iomap table PCI: Add and use devres helper for bit masks ...
2024-06-12PCI: Hold the rescan mutex when scanning for the first timeBartosz Golaszewski1-0/+2
With the introduction of PCI device power control drivers that will be able to trigger the port rescan when probing, we need to hold the rescan mutex during the initial pci_host_probe() too or the two could get in each other's way. Tested-by: Amit Pundir <amit.pundir@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD, SM8650-QRD & SM8650-HDK Tested-by: Caleb Connolly <caleb.connolly@linaro.org> # OnePlus 8T Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20240612082019.19161-2-brgl@bgdev.pl Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2024-06-04PCI: Revert the cfg_access_lock lockdep mechanismDan Williams1-3/+0
While the experiment did reveal that there are additional places that are missing the lock during secondary bus reset, one of the places that needs to take cfg_access_lock (pci_bus_lock()) is not prepared for lockdep annotation. Specifically, pci_bus_lock() takes pci_dev_lock() recursively and is currently dependent on the fact that the device_lock() is marked lockdep_set_novalidate_class(&dev->mutex). Otherwise, without that annotation, pci_bus_lock() would need to use something like a new pci_dev_lock_nested() helper, a scheme to track a PCI device's depth in the topology, and a hope that the depth of a PCI tree never exceeds the max value for a lockdep subclass. The alternative to ripping out the lockdep coverage would be to deploy a dynamic lock key for every PCI device. Unfortunately, there is evidence that increasing the number of keys that lockdep needs to track to be per-PCI-device is prohibitively expensive for something like the cfg_access_lock. The main motivation for adding the annotation in the first place was to catch unlocked secondary bus resets, not necessarily catch lock ordering problems between cfg_access_lock and other locks. Solve that narrower problem with follow-on patches, and just due to targeted revert for now. Link: https://lore.kernel.org/r/171711746402.1628941.14575335981264103013.stgit@dwillia2-xfh.jf.intel.com Fixes: 7e89efc6e9e4 ("PCI: Lock upstream bridge for pci_reset_function()") Reported-by: Imre Deak <imre.deak@intel.com> Closes: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134186v1/shard-dg2-1/igt@device_reset@unbind-reset-rebind.html Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Kalle Valo <kvalo@kernel.org> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Cc: Jani Saarinen <jani.saarinen@intel.com>
2024-06-03PCI: Use preserve_config in place of pci_flagsVidya Sagar1-11/+9
Use preserve_config in place of checking for PCI_PROBE_ONLY flag to enable support for "linux,pci-probe-only" on a per host bridge basis. This also obviates the use of adding PCI_REASSIGN_ALL_BUS flag if !PCI_PROBE_ONLY, as pci_assign_unassigned_root_bus_resources() takes care of reassigning the resources that are not already claimed. Link: https://lore.kernel.org/r/20240508174138.3630283-5-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-06-03PCI: Unify ACPI and DT 'preserve config' supportVidya Sagar1-0/+3
Unify the 'preserve config' support across ACPI and device-tree boot flows. Link: https://lore.kernel.org/r/20240508174138.3630283-4-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-06-03PCI: Move PRESERVE_BOOT_CONFIG _DSM evaluation to pci_register_host_bridge()Vidya Sagar1-0/+11
Move the PRESERVE_BOOT_CONFIG _DSM evaluation from acpi_pci_root_create() to pci_register_host_bridge(). This will help unify the ACPI _DSM path and the DT-based "linux,pci-probe-only" paths. This should be safe because it happens earlier than it used to: acpi_pci_root_create pci_create_root_bus pci_register_host_bridge + bridge->preserve_config = pci_preserve_config(bridge) pci_acpi_preserve_config + acpi_evaluate_dsm_typed(DSM_PCI_PRESERVE_BOOT_CONFIG) - acpi_evaluate_dsm_typed(DSM_PCI_PRESERVE_BOOT_CONFIG) No functional change intended. Link: https://lore.kernel.org/r/20240508174138.3630283-2-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-05-16Merge branch 'pci/misc'Bjorn Helgaas1-1/+1
- Constify pcibus_class (Heiner Kallweit) - Annotate pci_cache_line_size variables as __ro_after_init (Heiner Kallweit) - Clean up formatting of PCI accessor macros (Ilpo Järvinen) - Remove some OLPC dead code (Kunwu Chan) - Make pcie_bandwidth_capable() static (Ilpo Järvinen) * pci/misc: PCI: Make pcie_bandwidth_capable() static x86/pci: Remove OLPC dead code PCI: Clean up accessor macro formatting PCI/ERR: Cleanup misleading indentation inside if conditions PCI: Annotate pci_cache_line_size variables as __ro_after_init PCI: Constify pcibus_class
2024-05-16Merge branch 'pci/enumeration'Bjorn Helgaas1-0/+3
- Clear bridge Secondary Status errors after enumeration since enumeration causes many errors (Vidya Sagar) - Wait for Link Training==0 before starting Link retrain to avoid a race; this was done previously but broken by a faulty merge (Ilpo Järvinen) - Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX to be more specific about what "LEGACY" means (Damien Le Moal) - Update return types of pci_find_capability() stubs to match the extern declarations for the actual implementations (Bjorn Helgaas) - Drop unnecessary pci_enable_device_io() from pata_cs5520 (Heiner Kallweit) - Drop unused pci_enable_device_io() (Heiner Kallweit) - On 2016 and newer BIOSes, skip early E820 check for ECAM regions described in ACPI MCFG; there's no spec requirement for E820 reservations, and some machines don't provide them (Bjorn Helgaas) - If devices were disconnected while suspended, don't wait for them when resuming (Ilpo Järvinen) * pci/enumeration: PCI: Do not wait for disconnected devices when resuming x86/pci: Skip early E820 check for ECAM region PCI: Remove unused pci_enable_device_io() ata: pata_cs5520: Remove unnecessary call to pci_enable_device_io() PCI: Update pci_find_capability() stub return types PCI: Remove PCI_IRQ_LEGACY scsi: vmw_pvscsi: Do not use PCI_IRQ_LEGACY instead of PCI_IRQ_LEGACY scsi: pmcraid: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: mpt3sas: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: megaraid_sas: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: ipr: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: hpsa: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY scsi: arcmsr: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY wifi: rtw89: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY wifi: rtw88: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY wifi: ath10k: Refer to INTX instead of LEGACY net: wangxun: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY r8169: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY net: alx: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY net: atlantic: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY net: amd-xgbe: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY VMCI: Use PCI_IRQ_ALL_TYPES to remove PCI_IRQ_LEGACY use RDMA/vmw_pvrdma: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY IB/qib: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY drm/amdgpu: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY mfd: intel-lpss: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY ntb: idt: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY platform/x86: intel_ips: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY tty: 8250_pci: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY usb: hcd-pci: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY ASoC: Intel: avs: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY Documentation: PCI: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY PCI/portdrv: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY PCI/MSI: Use PCI_IRQ_INTX instead of PCI_IRQ_LEGACY PCI: Clarify intent of LT wait PCI: Wait for Link Training==0 before starting Link retrain PCI: Clear Secondary Status errors after enumeration
2024-05-08PCI: Lock upstream bridge for pci_reset_function()Dave Jiang1-0/+3
Fix a long-standing locking gap for missing pci_cfg_access_lock() while manipulating bridge reset registers and configuration during pci_reset_bus_function(). If there is an upstream bridge, lock it before locking the device itself. pci_dev_lock() calls pci_cfg_access_lock(), which blocks the writing of PCI config space by user space. Add lockdep assertion via pci_dev->cfg_access_lock to verify pci_dev->block_cfg_access is set. Co-developed-by: Dan Williams <dan.j.williams@intel.com> Link: https://lore.kernel.org/r/20240502165851.1948523-3-dave.jiang@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-04-23PCI: Clear Secondary Status errors after enumerationVidya Sagar1-0/+3
We enumerate devices by attempting config reads to the Vendor ID of each possible device. On conventional PCI, if no device responds, the read terminates with a Master Abort (PCI r3.0, sec 6.1). On PCIe, the config read is terminated as an Unsupported Request (PCIe r6.0, sec 2.3.2, 7.5.1.3.7). In either case, if the read addressed a device below a bridge, it is logged by setting "Received Master Abort" in the bridge Secondary Status register. Clear any errors logged in the Secondary Status register after enumeration. Link: https://lore.kernel.org/r/20240116143258.483235-1-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> [bhelgaas: simplify commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-04-17PCI: Constify pcibus_classHeiner Kallweit1-1/+1
Constify pcibus_class. All users take a const struct class * argument. Link: https://lore.kernel.org/r/5e01f46f-266f-4fb3-be8a-8cb9e566cd75@gmail.com Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-03-12Merge branch 'pci/sysfs'Bjorn Helgaas1-0/+4
- Compile pci-sysfs.c only if CONFIG_SYSFS=y, which reduces kernel size by ~120KB when it's disabled (Lukas Wunner) - Remove obsolete pci_cleanup_rom() declaration (Lukas Wunner) - Rework pci_dev_resource_resize_attr(n) macros to call a function instead of duplicating most of the body, which saves about 2.5KB of text (Ilpo Järvinen) * pci/sysfs: PCI/sysfs: Demacrofy pci_dev_resource_resize_attr(n) functions PCI: Remove obsolete pci_cleanup_rom() declaration PCI/sysfs: Compile pci-sysfs.c only if CONFIG_SYSFS=y # Conflicts: # drivers/pci/Makefile
2024-03-12PCI/ASPM: Save L1 PM Substates Capability for suspend/resumeDavid E. Box1-0/+1
4ff116d0d5fd ("PCI/ASPM: Save L1 PM Substates Capability for suspend/resume") restored the L1 PM Substates Capability after resume, which reduced power consumption by making the ASPM L1.x states work after resume. a7152be79b62 ("Revert "PCI/ASPM: Save L1 PM Substates Capability for suspend/resume"") reverted 4ff116d0d5fd because resume failed on some systems, so power consumption after resume increased again. a7152be79b62 mentioned that we restore L1 PM substate configuration even though ASPM L1 may already be enabled. This is due the fact that the pci_restore_aspm_l1ss_state() was called before pci_restore_pcie_state(). Save and restore the L1 PM Substates Capability, following PCIe r6.1, sec 5.5.4 more closely by: 1) Do not restore ASPM configuration in pci_restore_pcie_state() but do that after PCIe capability is restored in pci_restore_aspm_state() following PCIe r6.1, sec 5.5.4. 2) If BIOS reenables L1SS, particularly L1.2, we need to clear the enables in the right order, downstream before upstream. Defer restoring the L1SS config until we are at the downstream component. Then update the config for both ends of the link in the prescribed order. 3) Program ASPM L1 PM substate configuration before L1 enables. 4) Program ASPM L1 PM substate enables last, after rest of the fields in the capability are programmed. [bhelgaas: commit log, squash L1SS-related patches, do both LNKCTL restores in pci_restore_pcie_state()] Link: https://lore.kernel.org/r/20240128233212.1139663-3-david.e.box@linux.intel.com Link: https://lore.kernel.org/r/20240128233212.1139663-4-david.e.box@linux.intel.com Link: https://lore.kernel.org/r/20240223205851.114931-5-helgaas@kernel.org Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217321 Link: https://bugzilla.kernel.org/show_bug.cgi?id=216782 Link: https://bugzilla.kernel.org/show_bug.cgi?id=216877 Co-developed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Co-developed-by: David E. Box <david.e.box@linux.intel.com> Reported-by: Koba Ko <koba.ko@canonical.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: David E. Box <david.e.box@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Tasev Nikola <tasev.stefanoska@skynet.be> # Asus UX305FA Cc: Mark Enriquez <enriquezmark36@gmail.com> Cc: Thomas Witt <kernel@witt.link> Cc: Werner Sembach <wse@tuxedocomputers.com> Cc: Vidya Sagar <vidyas@nvidia.com>
2024-03-07PCI/ASPM: Move pci_configure_ltr() to aspm.cDavid E. Box1-61/+0
The Latency Tolerance Reporting (LTR) mechanism supports the ASPM L1.2 state and is only configured when CONFIG_PCIEASPM is set. Move pci_configure_ltr() and pci_bridge_reconfigure_ltr() into aspm.c since they only build when CONFIG_PCIEASPM is set. No functional change intended. Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20240128233212.1139663-2-david.e.box@linux.intel.com [bhelgaas: commit log, split build change from function moves] Link: https://lore.kernel.org/r/20240223205851.114931-2-helgaas@kernel.org Signed-off-by: David E. Box <david.e.box@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2024-03-05PCI/sysfs: Compile pci-sysfs.c only if CONFIG_SYSFS=yLukas Wunner1-0/+4
It is possible to enable CONFIG_PCI but disable CONFIG_SYSFS and for space-constrained devices such as routers, such a configuration may actually make sense. However pci-sysfs.c is compiled even if CONFIG_SYSFS is disabled, unnecessarily increasing the kernel's size. To rectify that: * Move pci_mmap_fits() to mmap.c. It is not only needed by pci-sysfs.c, but also proc.c. * Move pci_dev_type to probe.c and make it private. It references pci_dev_attr_groups in pci-sysfs.c. Make that public instead for consistency with pci_dev_groups, pcibus_groups and pci_bus_groups, which are likewise public and referenced by struct definitions in pci-driver.c and probe.c. * Define pci_dev_groups, pci_dev_attr_groups, pcibus_groups and pci_bus_groups to NULL if CONFIG_SYSFS is disabled. Provide empty static inlines for pci_{create,remove}_legacy_files() and pci_{create,remove}_sysfs_dev_files(). Result: vmlinux size is reduced by 122996 bytes in my arm 32-bit test build. Link: https://lore.kernel.org/r/85ca95ae8e4d57ccf082c5c069b8b21eb141846e.1698668982.git.lukas@wunner.de Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2023-12-15PCI: Log bridge info when first enumerating bridgeBjorn Helgaas1-4/+19
Log bridge secondary/subordinate bus and window information at the same time we log the bridge BARs, just after discovering the bridge and before scanning the bridge's secondary bus. This logs the bridge and downstream devices in a more logical order: - pci 0000:00:01.0: [8086:1901] type 01 class 0x060400 - pci 0000:01:00.0: [10de:13b6] type 00 class 0x030200 - pci 0000:01:00.0: reg 0x10: [mem 0xec000000-0xecffffff] - pci 0000:00:01.0: PCI bridge to [bus 01] - pci 0000:00:01.0: bridge window [io 0xe000-0xefff] + pci 0000:00:01.0: [8086:1901] type 01 class 0x060400 + pci 0000:00:01.0: PCI bridge to [bus 01] + pci 0000:00:01.0: bridge window [io 0xe000-0xefff] + pci 0000:01:00.0: [10de:13b6] type 00 class 0x030200 + pci 0000:01:00.0: reg 0x10: [mem 0xec000000-0xecffffff] Note that we read the windows into a temporary struct resource that is thrown away, not into the resources in the struct pci_bus. The windows may be adjusted after we know what downstream devices require, and those adjustments are logged as they are made. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-12-15PCI: Log bridge windows conditionallyBjorn Helgaas1-9/+15
Previously pci_read_bridge_io(), pci_read_bridge_mmio(), and pci_read_bridge_mmio_pref() unconditionally logged the bridge window resource. A future change will call these functions earlier and more often. Add a "log" parameter so callers can control whether to generate the log message. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-12-15PCI: Supply bridge device, not secondary bus, to read window detailsBjorn Helgaas1-15/+6
Previously we logged information about devices *below* the bridge before logging information about the bridge itself, e.g., pci 0000:00:01.0: [8086:1901] type 01 class 0x060400 pci 0000:01:00.0: [10de:13b6] type 00 class 0x030200 pci 0000:01:00.0: reg 0x10: [mem 0xec000000-0xecffffff] pci 0000:00:01.0: PCI bridge to [bus 01] pci 0000:00:01.0: bridge window [io 0xe000-0xefff] This is partly because the bridge windows are read in this path: pci_scan_child_bus_extend for (devfn = 0; devfn < 256; devfn += 8) pci_scan_slot(bus, devfn) # scan below bridge pcibios_fixup_bus(bus) pci_read_bridge_bases(bus) # read bridge windows pci_read_bridge_io(bus) Remove the assumption that the secondary (child) pci_bus already exists by passing in the bridge device (instead of the pci_bus) and a resource pointer when reading bridge windows. A future change can use this to log the bridge details before we enumerate the devices below the bridge. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-12-15PCI: Move pci_read_bridge_windows() below individual window accessorsBjorn Helgaas1-51/+51
Move pci_read_bridge_windows() below the functions that read the I/O, memory, and prefetchable memory windows, so pci_read_bridge_windows() can use them in the future. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-12-15PCI: Use resource names in PCI log messagesPuranjay Mohan1-13/+13
Use the pci_resource_name() to get the name of the resource and use it while printing log messages. [bhelgaas: rename to match struct resource * names, also use names in other BAR messages] Link: https://lore.kernel.org/r/20211106112606.192563-3-puranjay12@gmail.com Signed-off-by: Puranjay Mohan <puranjay12@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-12-15PCI: Log device type during enumerationBjorn Helgaas1-2/+40
Log the device type when enumeration a device. Sample output changes: - pci 0000:00:00.0: [8086:1237] type 00 class 0x060000 + pci 0000:00:00.0: [8086:1237] type 00 class 0x060000 conventional PCI endpoint - pci 0000:00:1c.0: [8086:a110] type 01 class 0x060400 + pci 0000:00:1c.0: [8086:a110] type 01 class 0x060400 PCIe Root Port Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-10-28Merge branch 'pci/field-get'Bjorn Helgaas1-4/+4
- Use FIELD_GET()/FIELD_PREP() when possible throughout drivers/pci/ (Ilpo Järvinen, Bjorn Helgaas) - Rework DPC control programming for clarity (Ilpo Järvinen) * pci/field-get: PCI/portdrv: Use FIELD_GET() PCI/VC: Use FIELD_GET() PCI/PTM: Use FIELD_GET() PCI/PME: Use FIELD_GET() PCI/ATS: Use FIELD_GET() PCI/ATS: Show PASID Capability register width in bitmasks PCI: Use FIELD_GET() in Sapphire RX 5600 XT Pulse quirk PCI: Use FIELD_GET() PCI/MSI: Use FIELD_GET/PREP() PCI/DPC: Use defines with DPC reason fields PCI/DPC: Use defined fields with DPC_CTL register PCI/DPC: Use FIELD_GET() PCI: hotplug: Use FIELD_GET/PREP() PCI: dwc: Use FIELD_GET/PREP() PCI: cadence: Use FIELD_GET() PCI: Use FIELD_GET() to extract Link Width PCI: mvebu: Use FIELD_PREP() with Link Width PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields # Conflicts: # drivers/pci/controller/dwc/pcie-tegra194.c
2023-10-24PCI: Use FIELD_GET()Bjorn Helgaas1-4/+4
Use FIELD_GET() and FIELD_PREP() to remove dependences on the field position, i.e., the shift value. No functional change intended. Link: https://lore.kernel.org/r/20231010204436.1000644-2-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
2023-10-10PCI: Do error check on own line to split long "if" conditionsIlpo Järvinen1-3/+3
Placing PCI error code check inside "if" condition usually results in need to split lines. Combined with additional conditions the "if" condition becomes messy. Convert to the usual error handling pattern with an additional variable to improve code readability. In addition, reverse the logic in pci_find_vsec_capability() to get rid of &&. No functional changes intended. Link: https://lore.kernel.org/r/20230911125354.25501-5-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> [bhelgaas: PCI_POSSIBLE_ERROR()] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-09-06PCI: Free released resource after coalescingRoss Lagerwall1-0/+1
release_resource() doesn't actually free the resource or resource list entry so free the resource list entry to avoid a leak. Closes: https://lore.kernel.org/r/878r9sga1t.fsf@kernel.org/ Fixes: e54223275ba1 ("PCI: Release resource invalidated by coalescing") Link: https://lore.kernel.org/r/20230906110846.225369-1-ross.lagerwall@citrix.com Reported-by: Kalle Valo <kvalo@kernel.org> Tested-by: Kalle Valo <kvalo@kernel.org> Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org # v5.16+
2023-08-29Merge branch 'pci/misc'Bjorn Helgaas1-2/+1
- Reorder struct pci_dev to avoid holes and reduce size (Christophe JAILLET) - Change pdev->rom_attr_enabled to single bit since it's only a boolean value (Christophe JAILLET) - Use struct_size() in pirq_convert_irt_table() instead of hand-writing it (Christophe JAILLET) - Explicitly include correct DT includes to untangle headers (Rob Herring) - Fix a DOE race between destroy_work_on_stack() and the stack-allocated task->work struct going out of scope in pci_doe() (Ira Weiny) - Use pci_dev_id() when possible instead of manually composing ID from dev->bus->number and dev->devfn (Xiongfeng Wang, Zheng Zengkai) - Move pci_create_resource_files() declarations to linux/pci.h for alpha build warnings (Arnd Bergmann) - Remove unused hotplug function declarations (Yue Haibing) - Remove unused mvebu struct mvebu_pcie.busn (Pali Rohár) - Unexport pcie_port_bus_type (Bjorn Helgaas) - Remove unnecessary sysfs ID local variable initialization (Bjorn Helgaas) - Fix BAR value printk formatting to accommodate 32-bit values (Bjorn Helgaas) - Use consistent pointer types for config access syscall get_user() and put_user() uses (Bjorn Helgaas) - Simplify AER_RECOVER_RING_SIZE definition (Bjorn Helgaas) - Simplify pci_pio_to_address() (Bjorn Helgaas) - Simplify pci_dev_driver() (Bjorn Helgaas) - Fix pci_bus_resetable(), pci_slot_resetable() name typos (Bjorn Helgaas) - Fix code and doc typos and code formatting (Bjorn Helgaas) - Tidy config space save/restore messages (Bjorn Helgaas) * pci/misc: PCI: Tidy config space save/restore messages PCI: Fix code formatting inconsistencies PCI: Fix typos in docs and comments PCI: Fix pci_bus_resetable(), pci_slot_resetable() name typos PCI: Simplify pci_dev_driver() PCI: Simplify pci_pio_to_address() PCI/AER: Simplify AER_RECOVER_RING_SIZE definition PCI: Use consistent put_user() pointer types PCI: Fix printk field formatting PCI: Remove unnecessary initializations PCI: Unexport pcie_port_bus_type PCI: mvebu: Remove unused busn member PCI: Remove unused function declarations PCI/sysfs: Move declarations to linux/pci.h PCI/P2PDMA: Use pci_dev_id() to simplify the code PCI/IOV: Use pci_dev_id() to simplify the code PCI/AER: Use pci_dev_id() to simplify the code PCI: apple: Use pci_dev_id() to simplify the code PCI/DOE: Fix destroy_work_on_stack() race PCI: Explicitly include correct DT includes x86/PCI: Use struct_size() in pirq_convert_irt_table() PCI: Change pdev->rom_attr_enabled to single bit PCI: Reorder pci_dev fields to reduce holes
2023-08-25PCI: Fix typos in docs and commentsBjorn Helgaas1-1/+1
Fix typos in docs and comments. Link: https://lore.kernel.org/r/20230824193712.542167-11-helgaas@kernel.org Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
2023-08-10PCI: Add locking to RMW PCI Express Capability Register accessorsIlpo Järvinen1-0/+1
Many places in the kernel write the Link Control and Root Control PCI Express Capability Registers without proper concurrency control and this could result in losing the changes one of the writers intended to make. Add pcie_cap_lock spinlock into the struct pci_dev and use it to protect bit changes made in the RMW capability accessors. Protect only a selected set of registers by differentiating the RMW accessor internally to locked/unlocked variants using a wrapper which has the same signature as pcie_capability_clear_and_set_word(). As the Capability Register (pos) given to the wrapper is always a constant, the compiler should be able to simplify all the dead-code away. So far only the Link Control Register (ASPM, hotplug, link retraining, various drivers) and the Root Control Register (AER & PME) seem to require RMW locking. Suggested-by: Lukas Wunner <lukas@wunner.de> Fixes: c7f486567c1d ("PCI PM: PCIe PME root port service driver") Fixes: f12eb72a268b ("PCI/ASPM: Use PCI Express Capability accessors") Fixes: 7d715a6c1ae5 ("PCI: add PCI Express ASPM support") Fixes: affa48de8417 ("staging/rdma/hfi1: Add support for enabling/disabling PCIe ASPM") Fixes: 849a9366cba9 ("misc: rtsx: Add support new chip rts5228 mmc: rtsx: Add support MMC_CAP2_NO_MMC") Fixes: 3d1e7aa80d1c ("misc: rtsx: Use pcie_capability_clear_and_set_word() for PCI_EXP_LNKCTL") Fixes: c0e5f4e73a71 ("misc: rtsx: Add support for RTS5261") Fixes: 3df4fce739e2 ("misc: rtsx: separate aspm mode into MODE_REG and MODE_CFG") Fixes: 121e9c6b5c4c ("misc: rtsx: modify and fix init_hw function") Fixes: 19f3bd548f27 ("mfd: rtsx: Remove LCTLR defination") Fixes: 773ccdfd9cc6 ("mfd: rtsx: Read vendor setting from config space") Fixes: 8275b77a1513 ("mfd: rts5249: Add support for RTS5250S power saving") Fixes: 5da4e04ae480 ("misc: rtsx: Add support for RTS5260") Fixes: 0f49bfbd0f2e ("tg3: Use PCI Express Capability accessors") Fixes: 5e7dfd0fb94a ("tg3: Prevent corruption at 10 / 100Mbps w CLKREQ") Fixes: b726e493e8dc ("r8169: sync existing 8168 device hardware start sequences with vendor driver") Fixes: e6de30d63eb1 ("r8169: more 8168dp support.") Fixes: 8a06127602de ("Bluetooth: hci_bcm4377: Add new driver for BCM4377 PCIe boards") Fixes: 6f461f6c7c96 ("e1000e: enable/disable ASPM L0s and L1 and ERT according to hardware errata") Fixes: 1eae4eb2a1c7 ("e1000e: Disable L1 ASPM power savings for 82573 mobile variants") Fixes: 8060e169e02f ("ath9k: Enable extended synch for AR9485 to fix L0s recovery issue") Fixes: 69ce674bfa69 ("ath9k: do btcoex ASPM disabling at initialization time") Fixes: f37f05503575 ("mt76: mt76x2e: disable pcie_aspm by default") Link: https://lore.kernel.org/r/20230717120503.15276-2-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: "Rafael J. Wysocki" <rafael@kernel.org>
2023-07-18PCI: Explicitly include correct DT includesRob Herring1-1/+0
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Link: https://lore.kernel.org/r/20230714174827.4061572-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2023-06-26Merge branch 'pci/resource'Bjorn Helgaas1-1/+3
- When we coalesce host bridge windows, remove invalidated resources from the resource tree so future allocations work correctly (Ross Lagerwall) * pci/resource: PCI: Release resource invalidated by coalescing
2023-06-20PCI: Work around PCIe link training failuresMaciej W. Rozycki1-0/+2
Attempt to handle cases such as with a downstream port of the ASMedia ASM2824 PCIe switch where link training never completes and the link continues switching between speeds indefinitely with the data link layer never reaching the active state. It has been observed with a downstream port of the ASMedia ASM2824 Gen 3 switch wired to the upstream port of the Pericom PI7C9X2G304 Gen 2 switch, using a Delock Riser Card PCI Express x1 > 2 x PCIe x1 device, P/N 41433, wired to a SiFive HiFive Unmatched board. In this setup the switches should negotiate a link speed of 5.0GT/s, falling back to 2.5GT/s if necessary. Instead the link continues oscillating between the two speeds, at the rate of 34-35 times per second, with link training reported repeatedly active ~84% of the time. Limiting the target link speed to 2.5GT/s with the upstream ASM2824 device makes the two switches communicate correctly. Removing the speed restriction afterwards makes the two devices switch to 5.0GT/s then. Make use of these observations and detect the inability to train the link by checking for the Data Link Layer Link Active status bit being off while the Link Bandwidth Management Status indicating that hardware has changed the link speed or width in an attempt to correct unreliable link operation. Restrict the speed to 2.5GT/s then with the Target Link Speed field, request a retrain and wait 200ms for the data link to go up. If this is successful, lift the restriction, letting the devices negotiate a higher speed. Also check for a 2.5GT/s speed restriction the firmware may have already arranged and lift it too with ports of devices known to continue working afterwards (currently only ASM2824), that already report their data link being up. [bhelgaas: reorder and squash stubs from https://lore.kernel.org/r/alpine.DEB.2.21.2306111619570.64925@angie.orcam.me.uk to avoid adding stubs that do nothing] Link: https://lore.kerne