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path: root/drivers/pinctrl/sh-pfc
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2021-07-14pinctrl: renesas: r8a77990: JTAG pins do not have pull-down capabilitiesGeert Uytterhoeven1-4/+4
[ Upstream commit 702a5fa2fe4d7e7f28fed92a170b540acfff9d34 ] Hence remove the SH_PFC_PIN_CFG_PULL_DOWN flags from their pin descriptions. Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/da4b2d69955840a506412f1e8099607a0da97ecc.1619785375.git.geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-14pinctrl: renesas: r8a7796: Add missing bias for PRESET# pinGeert Uytterhoeven1-1/+2
[ Upstream commit 2cee31cd49733e89dfedf4f68a56839fc2e42040 ] R-Car Gen3 Hardware Manual Errata for Rev. 0.52 of Nov 30, 2016, added the configuration bit for bias pull-down control for the PRESET# pin on R-Car M3-W. Add driver support for controlling pull-down on this pin. Fixes: 2d40bd24274d2577 ("pinctrl: sh-pfc: r8a7796: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/c479de5b3f235c2f7d5faea9e7e08e6fccb135df.1619785375.git.geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-02-24pinctrl: sh-pfc: sh7269: Fix CAN function GPIOsGeert Uytterhoeven1-12/+27
[ Upstream commit 02aeb2f21530c98fc3ca51028eda742a3fafbd9f ] pinmux_func_gpios[] contains a hole due to the missing function GPIO definition for the "CTX0&CTX1" signal, which is the logical "AND" of the first two CAN outputs. A closer look reveals other issues: - Some functionality is available on alternative pins, but the PINMUX_DATA() entries is using the wrong marks, - Several configurations are missing. Fix this by: - Renaming CTX0CTX1CTX2_MARK, CRX0CRX1_PJ22_MARK, and CRX0CRX1CRX2_PJ20_MARK to CTX0_CTX1_CTX2_MARK, CRX0_CRX1_PJ22_MARK, resp. CRX0_CRX1_CRX2_PJ20_MARK for consistency with the corresponding enum IDs, - Adding all missing enum IDs and marks, - Use the right (*_PJ2x) variants for alternative pins, - Adding all missing configurations to pinmux_data[], - Adding all missing function GPIO definitions to pinmux_func_gpios[]. See SH7268 Group, SH7269 Group User’s Manual: Hardware, Rev. 2.00: [1] Table 1.4 List of Pins [2] Figure 23.29 Connection Example when Using Channels 0 and 1 as One Channel (64 Mailboxes × 1 Channel) and Channel 2 as One Channel (32 Mailboxes × 1 Channel), [3] Figure 23.30 Connection Example when Using Channels 0, 1, and 2 as One Channel (96 Mailboxes × 1 Channel), [4] Table 48.3 Multiplexed Pins (Port B), [5] Table 48.4 Multiplexed Pins (Port C), [6] Table 48.10 Multiplexed Pins (Port J), [7] Section 48.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191218194812.12741-5-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-02-24pinctrl: sh-pfc: sh7264: Fix CAN function GPIOsGeert Uytterhoeven1-5/+4
[ Upstream commit 55b1cb1f03ad5eea39897d0c74035e02deddcff2 ] pinmux_func_gpios[] contains a hole due to the missing function GPIO definition for the "CTX0&CTX1" signal, which is the logical "AND" of the two CAN outputs. Fix this by: - Renaming CRX0_CRX1_MARK to CTX0_CTX1_MARK, as PJ2MD[2:0]=010 configures the combined "CTX0&CTX1" output signal, - Renaming CRX0X1_MARK to CRX0_CRX1_MARK, as PJ3MD[1:0]=10 configures the shared "CRX0/CRX1" input signal, which is fed to both CAN inputs, - Adding the missing function GPIO definition for "CTX0&CTX1" to pinmux_func_gpios[], - Moving all CAN enums next to each other. See SH7262 Group, SH7264 Group User's Manual: Hardware, Rev. 4.00: [1] Figure 1.2 (3) (Pin Assignment for the SH7264 Group (1-Mbyte Version), [2] Figure 1.2 (4) Pin Assignment for the SH7264 Group (640-Kbyte Version, [3] Table 1.4 List of Pins, [4] Figure 20.29 Connection Example when Using This Module as 1-Channel Module (64 Mailboxes x 1 Channel), [5] Table 32.10 Multiplexed Pins (Port J), [6] Section 32.2.30 (3) Port J Control Register 0 (PJCR0). Note that the last 2 disagree about PJ2MD[2:0], which is probably the root cause of this bug. But considering [4], "CTx0&CTx1" in [5] must be correct, and "CRx0&CRx1" in [6] must be wrong. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191218194812.12741-4-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-02-14pinctrl: sh-pfc: r8a7778: Fix duplicate SDSELF_B and SD1_CLK_BGeert Uytterhoeven1-2/+2
commit 805f635703b2562b5ddd822c62fc9124087e5dd5 upstream. The FN_SDSELF_B and FN_SD1_CLK_B enum IDs are used twice, which means one set of users must be wrong. Replace them by the correct enum IDs. Fixes: 87f8c988636db0d4 ("sh-pfc: Add r8a7778 pinmux support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191218194812.12741-2-geert+renesas@glider.be Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-02-14pinctrl: sh-pfc: r8a77965: Fix DU_DOTCLKIN3 drive/bias controlGeert Uytterhoeven1-3/+3
commit a34cd9dfd03fa9ec380405969f1d638bc63b8d63 upstream. R-Car Gen3 Hardware Manual Errata for Rev. 2.00 of October 24, 2019 changed the configuration bits for drive and bias control for the DU_DOTCLKIN3 pin on R-Car M3-N, to match the same pin on R-Car H3. Update the driver to reflect this. After this, the handling of drive and bias control for the various DU_DOTCLKINx pins is consistent across all of the R-Car H3, M3-W, M3-W+, and M3-N SoCs. Fixes: 86c045c2e4201e94 ("pinctrl: sh-pfc: r8a77965: Replace DU_DOTCLKIN2 by DU_DOTCLKIN3") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191113101653.28428-1-geert+renesas@glider.be Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-17pinctrl: sh-pfc: Do not use platform_get_irq() to count interruptsGeert Uytterhoeven1-10/+6
commit ad7fe1a1a35994a201497443b5140bf54b074cca upstream. As platform_get_irq() now prints an error when the interrupt does not exist, counting interrupts by looping until failure causes the printing of scary messages like: sh-pfc e6060000.pin-controller: IRQ index 0 not found Fix this by using the platform_irq_count() helper instead. Fixes: 7723f4c5ecdb8d83 ("driver core: platform: Add an error message to platform_get_irq*()") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191016142601.28255-1-geert+renesas@glider.be Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-01-17pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set GPSRKeiya Nobuta1-2/+2
commit d30710b8cce3a581c170d69002e311cc18ed47d3 upstream. This patch allows PINMUX_IPSR_PHYS() to set bits in GPSR. When assigning function to pin, GPSR should be set to peripheral function. For example when using SCL3, GPSR2 bit7 (PWM1_A pin) should be set to peripheral function. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060112.29819-1-nobuta.keiya@fujitsu.com Fixes: 50d1ba1764b3e00a ("pinctrl: sh-pfc: Add physical pin multiplexing helper macros") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-12-31pinctrl: sh-pfc: sh7734: Fix duplicate TCLK1_BGeert Uytterhoeven1-2/+2
[ Upstream commit 884caadad128efad8e00c1cdc3177bc8912ee8ec ] The definitions for bit field [19:18] of the Peripheral Function Select Register 3 were accidentally copied from bit field [20], leading to duplicates for the TCLK1_B function, and missing TCLK0, CAN_CLK_B, and ET0_ETXD4 functions. Fix this by adding the missing GPIO_FN_CAN_CLK_B and GPIO_FN_ET0_ETXD4 enum values, and correcting the functions. Reported-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191024131308.16659-1-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-31Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D"Geert Uytterhoeven1-4/+5
[ Upstream commit 7666dfd533d4c55733037775d47a8e3551b341a2 ] This reverts commit e167d723e1a472d252e5c4baf823b77ce5543b05. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the SEL_SIMCARD_{0,1} definition was to be deleted. However, this errata merely fixed an accidental double definition in the Hardware User's Manual Rev. 1.00. The real definition is still present in later revisions of the manual (Rev. 1.50 and Rev. 2.00). Hence revert the commit to recover the definition. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-4-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-12-31Revert "pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 ↵Geert Uytterhoeven1-9/+11
and SSI_WS2" [ Upstream commit 3672bc7093434621c83299ef27ea3b3225a67600 ] This reverts commit e87882eb9be10b2b9e28156922c2a47d877f5db4. According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug 24, 2018, the SEL_SSI2_{0,1} definition was to be deleted. However, this errata merely fixed an accidental double definition in the Hardware User's Manual Rev. 1.00. The real definition is still present in later revisions of the manual (Rev. 1.50 and Rev. 2.00). Hence revert the commit to recover the definition. Based on a patch in the BSP by Takeshi Kihara <takeshi.kihara.df@renesas.com>. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Link: https://lore.kernel.org/r/20190904121658.2617-3-geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
2019-09-12pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()Dan Carpenter1-2/+4
We need to unlock and enable IRQs before we return on this error path. Fixes: 8a0cc47ccc7c ("pinctrl: sh-pfc: Rollback to mux if required when the gpio is freed") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20190827093927.GB8443@mwanda Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-08-23pinctrl: sh-pfc: Include the right headerLinus Walleij1-1/+1
This is a GPIO driver, use the appropriate header <linux/gpio/driver.h> rather than the legacy <linux/gpio.h> header. Cc: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-23pinctrl: sh-pfc: Rollback to mux if required when the gpio is freedYoshihiro Shimoda1-0/+15
Some drivers require switching between function and gpio at run-time. Allow to roll back from gpio to mux when the gpio is freed. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-12pinctrl: sh-pfc: Remove incomplete flag "cfg->type"Yoshihiro Shimoda1-26/+0
The old commit c58d9c1b26e3 ("sh-pfc: Implement generic pinconf support") broke the cfg->type flag to PINMUX_TYPE_FUNCTION because sh_pfc_pinconf_set() didn't call sh_pfc_reconfig_pin(). Now if we fix the cfg->type condition, it gets worse because: - Some drivers might be deferred so that .set_mux() will be called multiple times. - In such the case, the sh-pfc driver returns -EBUSY even if the group is the same, and then that driver fails to probe. Since the pinctrl subsystem already has such conditions according to @set_mux and @gpio_request_enable, this patch just remove the incomplete flag from sh-pfc/pinctrl.c. Fixes: c58d9c1b26e3 ("sh-pfc: Implement generic pinconf support") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-12pinctrl: sh-pfc: Add new flags into struct sh_pfc_pin_configYoshihiro Shimoda1-1/+13
To clean/modify the code up later, this patch just adds new flags "mux_set" and "gpio_enabled" into the struct sh_pfc_pin_config. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-08pinctrl: sh-pfc: Use dev_notice_once() instead of open-codingGeert Uytterhoeven1-7/+2
At the time of commit 9a643c9a11259955 ("sh-pfc: Convert message printing from pr_* to dev_*"), the dev_*_once() variants didn't exist yet, so the once behavior was open-coded. Since commit e135303bd5bebcd2 ("device: Add dev_<level>_once variants") they do, so "revert" to the good practice of using a helper. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-07-13Merge tag 'pinctrl-v5.3-1' of ↵Linus Torvalds23-1059/+1245
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ...
2019-06-04pinctrl: sh-pfc: Remove obsolete SH_PFC_PIN_NAMED*() macrosGeert Uytterhoeven1-16/+0
Now all Renesas pin control drivers have been converted to use the new non-GPIO helper macros, SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() are no longer used. Remove them. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: sh73a0: Use new macros for non-GPIO pinsGeert Uytterhoeven1-7/+12
Update the SH-Mobile AG5 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the SH-Mobile AG5 SoC (in 34x34 BGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pinsGeert Uytterhoeven1-46/+41
Update the R-Car E3 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car E3 SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pinsGeert Uytterhoeven1-156/+151
Update the R-Car M3-N pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-N SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pinsGeert Uytterhoeven1-156/+151
Update the R-Car M3-W pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M3-W SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pinsGeert Uytterhoeven1-159/+154
Update the R-Car H3 ES2.0 and later pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES2.0 SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pinsGeert Uytterhoeven1-170/+163
Update the R-Car H3 ES1.x pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H3 ES1.x SiP (in 39x39 BGA package) by symbolic enum values, referring to signal names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7790: Use new macros for non-GPIO pinsGeert Uytterhoeven1-15/+19
Update the R-Car H2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car H2 SoC (in 31x31 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: r8a7778: Use new macros for non-GPIO pinsGeert Uytterhoeven1-13/+16
Update the R-Car M1A pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the R-Car M1A SoC (in 25x25 FCBGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: emev2: Use new macros for non-GPIO pinsGeert Uytterhoeven1-36/+34
Update the EMMA Mobile EV2 pin control driver to use the new macros for describing pins without GPIO functionality. This replaces the use of physical pin numbers on the EMMA Mobile EV2 SoC (in 23x23 BGA package) by symbolic enum values, referring to signal names. Note that the user-visible names of these pins are still based on pin numbers instead of signal names, to preserve DT backwards compatibility. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04pinctrl: sh-pfc: Add new non-GPIO helper macrosGeert Uytterhoeven1-0/+56
Add new macros for describing pins without GPIO functionality: - NOGP_ALL() expands to a list of PIN_id values, to be used for generating symbolic enum values, - PINMUX_NOGP_ALL() expands to a list of sh_pfc_pin entries, to list all pins and their capabilities. Both macros depend on an SoC-specific CPU_ALL_NOGP() macro, to be provided by each individual SoC pin control driver. The new macros offer two advantages over the existing SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG() macros: 1. They do not rely on PIN_NUMBER() macros and physical pin numbering, hence do not suffer from pin numbering confusion among different SoC/SiP packages. 2. They are similar in spirit to the existing scheme for handling pins with GPIO functionality. Note that internal to the driver, non-GPIO pins use a sequential numbering scheme which starts after the highest GPIO pin number in use. This value is calculated automatically, using two new helper macros, for systems with either 32-port bank (GP port style) or linear (PORT style) pin space. Sample expansion: GP_LAST = sizeof(union { char dummy[0] __attribute__((deprecated, deprecated)); char GP_0_0[(0 * 32) + 0] __attribute__((deprecated, deprecated)); char GP_0_1[(0 * 32) + 1] __attribute__((deprecated, deprecated)); ... char GP_7_3[(7 * 32) + 3] __attribute__((deprecated, deprecated)); }) Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-01treewide: fix typos of SPDX-License-IdentifierMasahiro Yamada1-1/+1
Prior to the adoption of SPDX, it was difficult for tools to determine the correct license due to incomplete or badly formatted license text. The SPDX solves this issue, assuming people can correctly spell "SPDX-License-Identifier" although this assumption is broken in some places. Since scripts/spdxcheck.py parses only lines that exactly matches to the correct tag, it cannot (should not) detect this kind of error. If the correct tag is missing, scripts/checkpatch.pl warns like this: WARNING: Missing or malformed SPDX-License-Identifier tag in line * So, people should notice it before the patch submission, but in reality broken tags sometimes slip in. The checkpatch warning is not useful for checking the committed files globally since large number of files still have no SPDX tag. Also, I am not sure about the legal effect when the SPDX tag is broken. Anyway, these typos are absolutely worth fixing. It is pretty easy to find suspicious lines by grep. $ git grep --not -e SPDX-License-Identifier --and -e SPDX- -- \ :^LICENSES :^scripts/spdxcheck.py :^*/license-rules.rst arch/arm/kernel/bugs.c:// SPDX-Identifier: GPL-2.0 drivers/phy/st/phy-stm32-usbphyc.c:// SPDX-Licence-Identifier: GPL-2.0 drivers/pinctrl/sh-pfc/pfc-r8a77980.c:// SPDX-Lincense-Identifier: GPL 2.0 lib/test_stackinit.c:// SPDX-Licenses: GPLv2 sound/soc/codecs/max9759.c:// SPDX-Licence-Identifier: GPL-2.0 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-05-21pinctrl: sh-pfc: r8a7778: Use common PORT_GP_CFG_27() macroGeert Uytterhoeven1-17/+1
Get rid of the custom PORT_GP_PUP_27() macro by using the common PORT_GP_CFG_27() macro instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Add PORT_GP_27 helper macroGeert Uytterhoeven1-2/+6
This follows the style of the existing PORT_GP_X macros, and will be used by a follow-up patch for the r8a7778 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: r8a77965: Add TPU pins, groups and functionsGeert Uytterhoeven1-0/+42
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car M3-N SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functionsGeert Uytterhoeven1-2/+44
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on the R-Car M3-W and RZ/G2M SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functionsGeert Uytterhoeven1-0/+42
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revisions ES2.x and later of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functionsGeert Uytterhoeven1-0/+42
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs on revision ES1.x of the R-Car H3 SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: r8a77970: Remove MMC_{CD,WP}Geert Uytterhoeven1-22/+2
Hardware Manual Errata for rev. 1.50 of March 26, 2019 removed the bit definitions for MMC_CD and MMC_WP in the documentation for the IPSR6 and IPSR7 registers, as these pin functionalities do not exist on R-Car V3M. Remove the definitions, and the corrresponding pins and groups. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
2019-05-21pinctrl: sh-pfc: Move PIN_NONE to shared header fileGeert Uytterhoeven7-194/+189
Several drivers have identical definitions for PIN_NONE. Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h, and convert all drivers over to use it. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthandGeert Uytterhoeven10-35/+27
It is very common for a pin to support both pull-up and pull-down functionality. Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN. This not only reduces typing, but also avoids the need for several line breaks, and makes many overly long lines shorter, improving readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variantGeert Uytterhoeven17-19/+19
There are two variants of the CPU_ALL_PORT() macro in use: 1. A three-parameter variant, to be provided for SoCs with a linear GPIO pin space ("PORT style"), 2. A two-parameter variant, to be provided for SoCs with 32-port GPIO banks ("GP port style"). Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and to increase naming consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Validate pin tables at runtimeGeert Uytterhoeven1-0/+29
Extend the run-time debug code with checks to ensure there are no conflicting pin names, numbers, or enumeration values. This helps catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Add check for empty pinmux groups/functionsGeert Uytterhoeven1-1/+12
The pinmux groups and functions arrays may contain two parts, to ease supporting SoCs that expose pin subsets of other related SoCs. Both parts need to be declared with explicit sizes, which thus need to be updated when adding support for more groups and functions. If a size is too small, the compiler will detect this at build time ("excess elements in array initializer"). If a size is too large, this may go undetected (for pin groups), lead to pin controller registration failures (for pin functions: "pinmux ops has no name for functionN"), or crash the optional run-time debug code (for pin groups). Extend the run-time debug code with checks to detect this, to help catching bugs early. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Mark run-time debug code __initGeert Uytterhoeven1-7/+7
All run-time debug code is called from sh_pfc_init(), which is __init. Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21pinctrl: sh-pfc: Correct printk level of group reference warningGeert Uytterhoeven1-2/+2
Improve wording while at it. Fixes: 6161b39a14380815 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-04pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functionsTakeshi Kihara1-24/+87
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC. These pins are physically muxed with other pins. Therefore, setup of MOD_SEL is needed for exclusive control with other pins. [takeshi.kihara.df: add blank lines after function declarations] Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: use standard macros PINMUX_IPSR_PHYS and PINMUX_IPSR_PHYS_MSEL] Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-04pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin dataUlrich Hecht1-5/+0
Pin data for I2C controllers 0, 3 and 5 is properly defined already. Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-04pinctrl: sh-pfc: r8a77970: Fix spacingGeert Uytterhoeven1-6/+6
Replace "F_(0,0)" by "F_(0, 0)". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDFTakeshi Kihara3-35/+35
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car E3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}Takeshi Kihara3-33/+33
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of Dec 22, 2017, and the Errata for Rev 1.50 of Dec 25, 2018, MOD_SEL0 register bits 3, 4, 17, and 18 are renamed from SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}. Update the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitionsTakeshi Kihara5-76/+76
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and IPSR registers are renamed to RTS{0,1,3,4}_#. This patch updates the pin control drivers to reflect this. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Update R-Car H3 ES1.x, V3M, V3H, and D3] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
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