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2024-10-09spi: intel: Add protected and locked attributesAlexander Usyskin4-5/+63
The manufacturing access to the PCH/SoC SPI device is traditionally performed via userspace driver accessing registers via /dev/mem but due to security concerns /dev/mem access is being much restricted, hence the reason for utilizing dedicated Intel PCH/SoC SPI controller driver, which is already implemented in the Linux kernel. Intel PCH/SoC SPI controller protects the flash storage via two mechanisms one is the via region protection registers and second via BIOS lock. The BIOS locks only the BIOS regions usually 0 and/or 6. The device always boots with BIOS lock set, but during manufacturing the BIOS lock has to be lifted in order to enable the write access. This can be done by passing "writeable=1" in the command line when the driver is loaded. This "locked" state is exposed through new sysfs attributes (intel_spi_locked, intel_spi_bios_locked). Second, also the region protection status is exposed via sysfs attribute (intel_spi_protected) as the manufacturing will need the both files in order to validate that the device is properly sealed. Includes code written by Tamar Mashiah. Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Co-developed-by: Tomas Winkler <tomasw@gmail.com> Signed-off-by: Tomas Winkler <tomasw@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://patch.msgid.link/20241009062244.2436793-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-08spi: rockchip: Use dev_{err,warn}_probe() in the probe pathDragan Simic1-15/+13
Use function dev_err_probe() in the probe path instead of dev_err() where appropriate, to make the code a bit more uniform and compact. Use the new function dev_warn_probe() to improve error handling for the TX and RX DMA channel requests, which are actually optional, and tweak the logged warnings a bit to additionally describe their optional nature. Previously, deferred requests for the TX and RX DMA channels produced no debug messages, and the final error messages didn't include the error codes, which are all highly useful when debugging permanently failed DMA channel requests, such as when the required drivers aren't enabled. Suggested-by: Hélene Vulquin <oss@helene.moe> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Tested-by: Hélène Vulquin <oss@helene.moe> Link: https://patch.msgid.link/5b6bd142dab3ab93d7039db3e2fdcfea6bee2217.1727601608.git.dsimic@manjaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-08spi: rockchip-sfc: Use dev_err_probe() in the probe pathDragan Simic1-8/+6
Use function dev_err_probe() in the probe path instead of dev_err() where appropriate, to make the code a bit more uniform and compact. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://patch.msgid.link/398229ef316e64dc0c27944ea793dcddef1ead4e.1727601608.git.dsimic@manjaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-08spi: rockchip-sfc: Perform trivial code cleanupsDragan Simic1-5/+2
Perform a couple of trivial code cleanups, to avoid unnecessary line wrapping by using the 100-column width a bit better, and to drop a stray empty line. No intended functional changes are introduced by these code cleanups. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://patch.msgid.link/4dcd5d9cc4a20c9c6ad504d945475b767399b32f.1727601608.git.dsimic@manjaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-08spi: rockchip: Perform trivial code cleanupsDragan Simic1-15/+12
Perform a few trivial code cleanups, to obey the reverse Christmas tree rule, to avoid unnecessary line wrapping by using the 100-column width better, to actually obey the 100-column width in one case, and to make the way a couple of wrapped function arguments are indented a bit more readable. No intended functional changes are introduced by these code cleanups. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Dragan Simic <dsimic@manjaro.org> Link: https://patch.msgid.link/1b55380a0b9f0e8fe1a09611636b30e232b95d08.1727601608.git.dsimic@manjaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-08spi: spi-imx: Fix casting warningsHardevsinh Palaniya1-3/+2
Sparse warnings: drivers/spi/spi-imx.c:410:19: warning: cast to restricted __be32 drivers/spi/spi-imx.c:410:19: warning: cast to restricted __be32 drivers/spi/spi-imx.c:410:19: warning: cast to restricted __be32 drivers/spi/spi-imx.c:410:19: warning: cast to restricted __be32 drivers/spi/spi-imx.c:410:19: warning: cast to restricted __be32 drivers/spi/spi-imx.c:410:19: warning: cast to restricted __be32 drivers/spi/spi-imx.c:439:21: warning: incorrect type in assignment (different base types) drivers/spi/spi-imx.c:439:21: expected unsigned int [addressable] [usertype] val drivers/spi/spi-imx.c:439:21: got restricted __be32 [usertype] Signed-off-by: Hardevsinh Palaniya <hardevsinh.palaniya@siliconsignals.io> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20241008055644.4900-3-hardevsinh.palaniya@siliconsignals.io Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-08spi: spi-fsl-dspi: Fix casting warningsHardevsinh Palaniya1-4/+4
Sparse warnings: drivers/spi/spi-fsl-dspi.c:283:17: warning: incorrect type in assignment (different base types) drivers/spi/spi-fsl-dspi.c:283:17: expected unsigned int [usertype] drivers/spi/spi-fsl-dspi.c:283:17: got restricted __be32 [usertype] drivers/spi/spi-fsl-dspi.c:289:28: warning: cast to restricted __be32 drivers/spi/spi-fsl-dspi.c:289:28: warning: cast to restricted __be32 drivers/spi/spi-fsl-dspi.c:289:28: warning: cast to restricted __be32 drivers/spi/spi-fsl-dspi.c:289:28: warning: cast to restricted __be32 drivers/spi/spi-fsl-dspi.c:289:28: warning: cast to restricted __be32 drivers/spi/spi-fsl-dspi.c:289:28: warning: cast to restricted __be32 drivers/spi/spi-fsl-dspi.c:295:17: warning: incorrect type in assignment (different base types) drivers/spi/spi-fsl-dspi.c:295:17: expected unsigned int [usertype] drivers/spi/spi-fsl-dspi.c:295:17: got restricted __be16 [usertype] drivers/spi/spi-fsl-dspi.c:301:28: warning: cast to restricted __be16 drivers/spi/spi-fsl-dspi.c:301:28: warning: cast to restricted __be16 drivers/spi/spi-fsl-dspi.c:301:28: warning: cast to restricted __be16 drivers/spi/spi-fsl-dspi.c:301:28: warning: cast to restricted __be16 Signed-off-by: Hardevsinh Palaniya <hardevsinh.palaniya@siliconsignals.io> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Link: https://patch.msgid.link/20241008055644.4900-2-hardevsinh.palaniya@siliconsignals.io Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-07spi: Merge up v6.12Mark Brown12-15/+17
Fixes build issues with the KVM selftests.
2024-10-05Merge tag 'spi-fix-v6.12-rc1' of ↵Linus Torvalds4-7/+9
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A small set of driver specific fixes that came in since the merge window, about half of which is fixes for correctness in the use of the runtime PM APIs done as part of a broader cleanup" * tag 'spi-fix-v6.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: s3c64xx: fix timeout counters in flush_fifo spi: atmel-quadspi: Fix wrong register value written to MR spi: spi-cadence: Fix missing spi_controller_is_target() check spi: spi-cadence: Fix pm_runtime_set_suspended() with runtime pm enabled spi: spi-imx: Fix pm_runtime_set_suspended() with runtime pm enabled
2024-10-04spi: Provide defer reason if getting irq during probe failsUwe Kleine-König1-1/+1
Using dev_err_probe() in spi_probe() improves the kernel output from spi spi0.0: deferred probe pending: (reason unknown) to spi spi0.0: deferred probe pending: ad7124: Failed to get irq... for my current quest to make a certain spi device work. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20241004094234.268301-2-u.kleine-koenig@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-02move asm/unaligned.h to linux/unaligned.hAl Viro8-8/+8
asm/unaligned.h is always an include of asm-generic/unaligned.h; might as well move that thing to linux/unaligned.h and include that - there's nothing arch-specific in that header. auto-generated by the following: for i in `git grep -l -w asm/unaligned.h`; do sed -i -e "s/asm\/unaligned.h/linux\/unaligned.h/" $i done for i in `git grep -l -w asm-generic/unaligned.h`; do sed -i -e "s/asm-generic\/unaligned.h/linux\/unaligned.h/" $i done git mv include/asm-generic/unaligned.h include/linux/unaligned.h git mv tools/include/asm-generic/unaligned.h tools/include/linux/unaligned.h sed -i -e "/unaligned.h/d" include/asm-generic/Kbuild sed -i -e "s/__ASM_GENERIC/__LINUX/" include/linux/unaligned.h tools/include/linux/unaligned.h
2024-10-02spi: spi-ti-qspi: remove redundant assignment to variable retColin Ian King1-1/+0
Variable ret is being assigned a value but it is never read, instead the variable is being reassigned later in the exit path via label no_dma. Remove the redundant assignment. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://patch.msgid.link/20241002162652.957102-1-colin.i.king@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-02spi: mxic: Add support for swapping byteAlvinZhou1-4/+13
Some SPI-NOR flash swap the bytes on a 16-bit boundary when configured in Octal DTR mode. It means data format D0 D1 D2 D3 would be swapped to D1 D0 D3 D2. So that whether controller support swapping bytes should be checked before enable Octal DTR mode. Add swap byte support on a 16-bit boundary when configured in Octal DTR mode for Macronix xSPI host controller driver. According dtr_swab in operation to enable/disable Macronix xSPI host controller swap byte feature. To make sure swap byte feature is working well, program data in 1S-1S-1S mode then read back and compare read data in 8D-8D-8D mode. This feature have been validated on byte-swap flash and non-byte-swap flash. Macronix xSPI host controller bit "HC_CFG_DATA_PASS" determine the byte swap feature disabled/enabled and swap byte feature is working on 8D-8D-8D mode only. Suggested-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Acked-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20240926141956.2386374-6-alvinzhou.tw@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-02spi: spi-mem: Allow specifying the byte order in Octal DTR modeTudor Ambarus1-0/+3
There are NOR flashes (Macronix) that swap the bytes on a 16-bit boundary when configured in Octal DTR mode. The byte order of 16-bit words is swapped when read or written in Octal Double Transfer Rate (DTR) mode compared to Single Transfer Rate (STR) modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2. Swapping the bytes may introduce some endianness problems. It can affect the boot sequence if the entire boot sequence is not handled in either 8D-8D-8D mode or 1-1-1 mode. Therefore, it is necessary to swap the bytes back to ensure the same byte order as in STR modes. Fortunately there are controllers that could swap the bytes back at runtime, addressing the flash's endianness requirements. Provide a way for the upper layers to specify the byte order in Octal DTR mode. Merge Tudor's patch and add modifications for suiting newer version of Linux kernel. Suggested-by: Michael Walle <mwalle@kernel.org> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw> Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw> Acked-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20240926141956.2386374-3-alvinzhou.tw@gmail.com Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
2024-10-02spi: Fix pm_runtime_set_suspended() with runtime pmMark Brown2-4/+6
Merge series from Jinjie Ruan <ruanjinjie@huawei.com>: Fix pm_runtime_set_suspended() with runtime pm enabled, and fix the missing check for spi-cadence. Jinjie Ruan (3): spi: spi-imx: Fix pm_runtime_set_suspended() with runtime pm enabled spi: spi-cadence: Fix pm_runtime_set_suspended() with runtime pm enabled spi: spi-cadence: Fix missing spi_controller_is_target() check drivers/spi/spi-cadence.c | 8 +++++--- drivers/spi/spi-imx.c | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) -- 2.34.1
2024-10-01spi: s3c64xx: fix timeout counters in flush_fifoBen Dooks1-2/+2
In the s3c64xx_flush_fifo() code, the loops counter is post-decremented in the do { } while(test && loops--) condition. This means the loops is left at the unsigned equivalent of -1 if the loop times out. The test after will never pass as if tests for loops == 0. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Fixes: 230d42d422e7 ("spi: Add s3c64xx SPI Controller driver") Reviewed-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20240924134009.116247-2-ben.dooks@codethink.co.uk Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-01spi: spi-fsl-lpspi: Some calculation improvementsMark Brown1-4/+11
Merge series from Stefan Wahren <wahrenst@gmx.net>: This series contains some improvements for spi-fsl-lpspi which are related to the calculations within fsl_lpspi_set_bitrate.
2024-10-01spi: atmel-quadspi: Fix wrong register value written to MRAlexander Dahl1-1/+1
aq->mr should go to MR, nothing else. Fixes: 329ca3eed4a9 ("spi: atmel-quadspi: Avoid overwriting delay register settings") Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/linux-spi/20240926-macarena-wincing-7c4995487a29@thorsis.com/T/#u Link: https://patch.msgid.link/20240926090356.105789-1-ada@thorsis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30Improve error handling in Rockchip SPI driversMark Brown2-28/+20
Merge series from Dragan Simic <dsimic@manjaro.org>: This is a small series that improves error handling in the probe path of the Rockchip SPI drivers, by using dev_err_probe() properly in multiple places. It also performs a bunch of small, rather trivial code cleanups, to make the code neater and a bit easier to read.
2024-09-30spi: replace and removeMark Brown3-10/+10
Merge series from Yang Yingliang <yangyingliang@huaweicloud.com>: Switch to use {devm_}spi_alloc_host/target() in drivers and remove {devm_}spi_alloc_master/slave() in spi driver.
2024-09-30spi: spi_amd: Performance Optimization Patch SeriesMark Brown1-30/+295
Merge series from Raju Rangoju <Raju.Rangoju@amd.com>: AMD SPI controller’s index mode performance is constrained by the hardware limitation of the FIFO queue length. This patch series introduces optimizations to the spi_amd driver, aiming to maximize throughput and enhance overall performance. The changes includes, - Enable SPI dual and quad I/O modes and update SPI-MEM support function to reflect AMD SPI0 hardware capabilities. - Utilize efficient kernel APIs to streamline SPI I/O operations for enhanced performance. - Refine the set tx/rx count functions to optimize SPI I/O throughput. - Minimize the number of data read calls by efficiently retrieving data from FIFO queues, improving SPI I/O efficiency. - Add changes to support AMD HID2 SPI controller and update SPI-MEM support function to reflect AMD HID2 hardware capabilities. - Add changes to set SPI controller address mode before initiating the commands - Add changes to implement HIDDMA read operation support for HID2 SPI controller
2024-09-30spi: spi-fsl-lpspi: support effective_speed_hzStefan Wahren1-0/+6
Setting spi_transfer->effective_speed_hz in transfer_one so that SPI client driver can use it. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20240930093056.93418-4-wahrenst@gmx.net Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi-fsl-lpspi: Fix specifiers in fsl_lpspi_set_bitrateStefan Wahren1-1/+1
Most of the parameters are unsigned, so fix the used format specifiers in the debug message in fsl_lpspi_set_bitrate. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20240930093056.93418-3-wahrenst@gmx.net Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi-fsl-lpspi: Adjust type of scldivStefan Wahren1-3/+4
The target value of scldiv is just a byte, but its calculation in fsl_lpspi_set_bitrate could be negative. So use an adequate type to store the result and avoid overflows. After that this needs range check adjustments, but this should make the code less opaque. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20240930093056.93418-2-wahrenst@gmx.net Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi-cadence: Fix missing spi_controller_is_target() checkJinjie Ruan1-2/+4
The spi_controller_is_target() check is missing for pm_runtime_disable() in cdns_spi_remove(), add it. Fixes: b1b90514eaa3 ("spi: spi-cadence: Add support for Slave mode") Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20240923040015.3009329-4-ruanjinjie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi-cadence: Fix pm_runtime_set_suspended() with runtime pm enabledJinjie Ruan1-2/+2
It is not valid to call pm_runtime_set_suspended() for devices with runtime PM enabled because it returns -EAGAIN if it is enabled already and working. So, call pm_runtime_disable() before to fix it. Fixes: d36ccd9f7ea4 ("spi: cadence: Runtime pm adaptation") Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20240923040015.3009329-3-ruanjinjie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi-imx: Fix pm_runtime_set_suspended() with runtime pm enabledJinjie Ruan1-1/+1
It is not valid to call pm_runtime_set_suspended() for devices with runtime PM enabled because it returns -EAGAIN if it is enabled already and working. So, call pm_runtime_disable() before to fix it. Fixes: 43b6bf406cd0 ("spi: imx: fix runtime pm support for !CONFIG_PM") Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20240923040015.3009329-2-ruanjinjie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: atmel-quadspi: Add cs_hold and cs_inactive setting supportAlexander Dahl1-4/+32
spi-cs-inactive-delay-ns in dts is cs_inactive in spi core, and it maps to DLYCS (Minimum Inactive QCS Delay) in QSPI Mode Register (QSPI_MR). spi-cs-hold-delay-ns in dts is cs_hold in spi core, and it maps to DLYBCT (Delay Between Consecutive Transfers) in QSPI_MR. That one can be set to other values than 0 only if the chip is not in Serial Memory Mode (SMM), it must be written to '0' however when in SMM. Tested on SAM9X60 based board with FPGA implementing custom SPI Memory protocol. Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://patch.msgid.link/20240918082744.379610-3-ada@thorsis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: airoha: do not keep {tx,rx} dma buffer always mappedLorenzo Bianconi1-83/+71
DMA map txrx_buf on demand in airoha_snand_dirmap_read and airoha_snand_dirmap_write routines and do not keep it always mapped. This patch is not fixing any bug or introducing any functional change to the driver, it just simplifies the code and improve code readability without introducing any performance degradation according to the results obtained from the mtd_speedtest kernel module test. root@OpenWrt:# insmod mtd_test.ko root@OpenWrt:# insmod mtd_speedtest.ko dev=5 [ 49.849869] ================================================= [ 49.855659] mtd_speedtest: MTD device: 5 [ 49.859583] mtd_speedtest: MTD device size 8388608, eraseblock size 131072, page size 2048, count of eraseblocks 64, pages per eraseblock 64, OOB size 128 [ 49.874622] mtd_test: scanning for bad eraseblocks [ 49.879433] mtd_test: scanned 64 eraseblocks, 0 are bad [ 50.106372] mtd_speedtest: testing eraseblock write speed [ 53.083380] mtd_speedtest: eraseblock write speed is 2756 KiB/s [ 53.089322] mtd_speedtest: testing eraseblock read speed [ 54.143360] mtd_speedtest: eraseblock read speed is 7811 KiB/s [ 54.370365] mtd_speedtest: testing page write speed [ 57.349480] mtd_speedtest: page write speed is 2754 KiB/s [ 57.354895] mtd_speedtest: testing page read speed [ 58.410431] mtd_speedtest: page read speed is 7796 KiB/s [ 58.636805] mtd_speedtest: testing 2 page write speed [ 61.612427] mtd_speedtest: 2 page write speed is 2757 KiB/s [ 61.618021] mtd_speedtest: testing 2 page read speed [ 62.672653] mtd_speedtest: 2 page read speed is 7804 KiB/s [ 62.678159] mtd_speedtest: Testing erase speed [ 62.903617] mtd_speedtest: erase speed is 37063 KiB/s [ 62.908678] mtd_speedtest: Testing 2x multi-block erase speed [ 63.134083] mtd_speedtest: 2x multi-block erase speed is 37292 KiB/s [ 63.140442] mtd_speedtest: Testing 4x multi-block erase speed [ 63.364262] mtd_speedtest: 4x multi-block erase speed is 37566 KiB/s [ 63.370632] mtd_speedtest: Testing 8x multi-block erase speed [ 63.595740] mtd_speedtest: 8x multi-block erase speed is 37344 KiB/s [ 63.602089] mtd_speedtest: Testing 16x multi-block erase speed [ 63.827426] mtd_speedtest: 16x multi-block erase speed is 37320 KiB/s [ 63.833860] mtd_speedtest: Testing 32x multi-block erase speed [ 64.059389] mtd_speedtest: 32x multi-block erase speed is 37288 KiB/s [ 64.065833] mtd_speedtest: Testing 64x multi-block erase speed [ 64.290609] mtd_speedtest: 64x multi-block erase speed is 37415 KiB/s [ 64.297063] mtd_speedtest: finished [ 64.300555] ================================================= Tested-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://patch.msgid.link/20240922-airoha-spi-fixes-v3-1-f958802b3d68@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: Switch back to struct platform_driver::remove()Uwe Kleine-König88-92/+92
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/spi to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. The change for the spi-npcm-fiu stands out in the diffstat because the inconsistent formatting style of the platform_driver initializer is fixed to match the other struct initializer in the file. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20240925113501.25208-2-u.kleine-koenig@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: slave-mt27xx: Call clk_disable_unprepare() only once in ↵Markus Elfring1-3/+1
mtk_spi_slave_probe() A clk_disable_unprepare(mdata->spi_clk) call was immediately used after a return value check for a devm_spi_register_controller() call in this function implementation. Thus call such a function only once instead directly before the check. This issue was transformed by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Link: https://patch.msgid.link/9e736d33-b07f-40a0-8fb6-8c3212593b77@web.de Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi-fsl-lpspi: Use IRQF_NO_AUTOEN flag in request_irq()Jinjie Ruan1-8/+4
disable_irq() after request_irq() still has a time gap in which interrupts can come. request_irq() with IRQF_NO_AUTOEN flag will disable IRQ auto-enable when request IRQ. Fixes: 9728fb3ce117 ("spi: lpspi: disable lpspi module irq in DMA mode") Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20240906022828.891812-1-ruanjinjie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: fix typo in the commentYan Zhen10-11/+11
Correctly spelled comments make it easier for the reader to understand the code. Replace 'progrom' with 'program' in the comment & replace 'Recevie' with 'Receive' in the comment & replace 'receieved' with 'received' in the comment & replace 'ajacent' with 'adjacent' in the comment & replace 'trasaction' with 'transaction' in the comment & replace 'pecularity' with 'peculiarity' in the comment & replace 'resiter' with 'register' in the comment & replace 'tansmition' with 'transmission' in the comment & replace 'Deufult' with 'Default' in the comment & replace 'tansfer' with 'transfer' in the comment & replace 'settign' with 'setting' in the comment. Signed-off-by: Yan Zhen <yanzhen@vivo.com> Reviewed-by: Andi Shyti <andi.shyti@kernel.org> Link: https://patch.msgid.link/20240914095213.298256-1-yanzhen@vivo.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: rockchip-sfc: Use dev_err_probe() in the probe pathDragan Simic1-8/+6
Use function dev_err_probe() in the probe path instead of dev_err() where appropriate, to make the code a bit more uniform and compact. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/8f65c1ec7737af7f2a538fcae3618756a53ba3fa.1727337732.git.dsimic@manjaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: rockchip-sfc: Perform trivial code cleanupsDragan Simic1-5/+2
Perform a couple of trivial code cleanups, to avoid unnecessary line wrapping by using the 100-column width a bit better, and to drop a stray empty line. No intended functional changes are introduced by these code cleanups. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/251242bfc9c4fdc01d930f093022ce0c9481d58e.1727337732.git.dsimic@manjaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: rockchip: Perform trivial code cleanupsDragan Simic1-15/+12
Perform a few trivial code cleanups, to obey the reverse Christmas tree rule, to avoid unnecessary line wrapping by using the 100-column width better, to actually obey the 100-column width in one case, and to make the way a couple of wrapped function arguments are indented a bit more readable. No intended functional changes are introduced by these code cleanups. Signed-off-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://patch.msgid.link/663ec6bb472ab83bb5824a09d11b36ef20a43fc7.1727337732.git.dsimic@manjaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: remove {devm_}spi_alloc_master/slave()Yang Yingliang1-7/+7
All the {devm_}spi_alloc_master/slave() have been replaced, so they can be removed and replaced in doc and comment. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://patch.msgid.link/20240902125947.1368-8-yangyingliang@huaweicloud.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: slave-mt27xx: switch to use spi_alloc_target()Yang Yingliang1-2/+2
Switch to use modern name function spi_alloc_target(). No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://patch.msgid.link/20240902125947.1368-5-yangyingliang@huaweicloud.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: ch341: switch to use devm_spi_alloc_host()Yang Yingliang1-1/+1
Switch to use modern name function devm_spi_alloc_host(). No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://patch.msgid.link/20240902125947.1368-4-yangyingliang@huaweicloud.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi_amd: Add HIDDMA basic read supportRaju Rangoju1-20/+156
SPI index mode has hardware limitation of reading only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading data from NAND/NOR flash devices, as the controller must issue multiple requests to read 64-byte chunks, even if the slave can send up to 2 or 4 KB in single transaction. The AMD HID2 SPI controller supports DMA mode, which allows reading up to 4 KB of data in single transaction. This patch introduces changes to implement HID2 DMA read support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-9-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi_amd: Set controller address modeRaju Rangoju1-0/+15
Add changes to set the controller address mode before initiating commands. The AMD SPI0 controller(AMDI0062) supports both 24-bit and 32-bit address modes, while the HID2 SPI controller(AMDI0063) supports only the 24-bit address mode. So this change is applicable only for SPI0 controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-8-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi_amd: Add support for HID2 SPI controllerRaju Rangoju1-4/+38
AMD SoC has HID2 SPI controller in addition to the existing SPI0 controller(AMDI0062). Add HID2 SPI controller's ACPI ID AMDI0063 with its version ID to the list of supported devices. Use the version ID to differentiate the register offsets. And, the AMD HID2 SPI controller supports DMA read, allowing for up to 4 KB of data to be read in single transaction. Update the SPI-MEM support function to reflect this capability. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-7-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi_amd: Optimize IO operationsRaju Rangoju1-12/+41
Read and write the maximum number of data bytes at once, rather than byte by byte. This improves AMD SPI controller driver performance by reducing the time required to access FIFO registers. For example, with the new changes, 64 bytes of data from the FIFO queue can be read in 8 read calls (8 bytes per call) instead of 64 read calls(1 byte per call). Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-6-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi_amd: Updates to set tx/rx count functionsRaju Rangoju1-2/+2
AMD SPI TX and RX counter registers are 1-byte length registers. The existing value will be overwritten during register write, so masking is not required. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-5-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi_amd: Replace ioread/iowrite callsRaju Rangoju1-4/+4
All `ioread*` and `iowrite*` functions are better suited for architecture independent code to ensure portability across different architectures. Since AMD SoCs support only the x86 architecture, replacing all `ioread*` and `iowrite*` calls with `read*` and `write*` calls can reduce the overhead of ensuring portability and increase the speed of I/O operations. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-4-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi_amd: Enable dual and quad I/O modesRaju Rangoju1-3/+54
The current spi_amd driver only supports single I/O mode, despite the AMD SPI controller's capability for dual and quad I/O modes for read operations. And AMD SPI0 controller has limited support for quad mode write operations. Update the SPI-MEM support function to reflect these hardware capabilities. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: spi_amd: Sort headers alphabeticallyRaju Rangoju1-2/+2
Sorting headers alphabetically helps locating duplicates, and makes it easier to figure out where to insert new headers. Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20240925133644.2922359-2-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-27[tree-wide] finally take no_llseek outAl Viro1-1/+0
no_llseek had been defined to NULL two years ago, in commit 868941b14441 ("fs: remove no_llseek") To quote that commit, At -rc1 we'll need do a mechanical removal of no_llseek - git grep -l -w no_llseek | grep -v porting.rst | while read i; do sed -i '/\<no_llseek\>/d' $i done would do it. Unfortunately, that hadn't been done. Linus, could you do that now, so that we could finally put that thing to rest? All instances are of the form .llseek = no_llseek, so it's obviously safe. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-09-26Merge tag 'soc-ep93xx-dt-6.12' of ↵Linus Torvalds1-45/+23
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC update from Arnd Bergmann: "Convert ep93xx to devicetree This concludes a long journey towards replacing the old board files with devictree description on the Cirrus Logic EP93xx platform. Nikita Shubin has been working on this for a long time, for details see the last post on https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/" * tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits) dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config net: cirrus: use u8 for addr to calm down sparse dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0 dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe() pinctrl: ep93xx: Fix raster pins typo spi: ep93xx: update kerneldoc comments for ep93xx_spi clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate() clk: ep93xx: add module license dmaengine: cirrus: remove platform code ASoC: cirrus: edb93xx: Delete driver ARM: ep93xx: soc: drop defines ARM: ep93xx: delete all boardfiles ata: pata_ep93xx: remove legacy pinctrl use pwm: ep93xx: drop legacy pinctrl ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms ARM: dts: ep93xx: Add EDB9302 DT ARM: dts: ep93xx: add ts7250 board ARM: dts: add Cirrus EP93XX SoC .dtsi ...
2024-09-25Merge tag 'spi-fix-v6.12-merge-window' of ↵Linus Torvalds3-33/+26
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "Some driver specific fixes that came in during the merge window. Lorenzo Bianconi did some extra testing on the recently added arioha driver and found some issues, Alexander Dahl fixed some issues with signal delays in the Atmel QSPI driver and Jinjie Ruan has been fixing some nits with runtime PM cleanup" * tag 'spi-fix-v6.12-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: atmel-quadspi: Avoid overwriting delay register settings spi: airoha: remove read cache in airoha_snand_dirmap_read() spi: spi-fsl-lpspi: Undo runtime PM changes at driver exit time spi: atmel-quadspi: Undo runtime PM changes at driver exit time spi: airoha: fix airoha_snand_{write,read}_data data_len estimation spi: airoha: fix dirmap_{read,write} operations
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-18 22:23:02 +0000