From 344b215b0db62b551c46e1feab1ddb10f99004ca Mon Sep 17 00:00:00 2001 From: Komal Shah Date: Sat, 1 Apr 2006 12:13:30 +0100 Subject: [ARM] 3437/1: Kill duplicate exports of string library functions Patch from Komal Shah This patch fixes the duplicate exports of string library functions. Signed-off-by: Komal Shah Signed-off-by: Russell King --- arch/arm/kernel/armksyms.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c index 1574941ebfe1..ee083b3f0522 100644 --- a/arch/arm/kernel/armksyms.c +++ b/arch/arm/kernel/armksyms.c @@ -100,23 +100,12 @@ EXPORT_SYMBOL(__raw_writesl); #endif /* string / mem functions */ -EXPORT_SYMBOL(strcpy); -EXPORT_SYMBOL(strncpy); -EXPORT_SYMBOL(strcat); -EXPORT_SYMBOL(strncat); -EXPORT_SYMBOL(strcmp); -EXPORT_SYMBOL(strncmp); EXPORT_SYMBOL(strchr); -EXPORT_SYMBOL(strlen); -EXPORT_SYMBOL(strnlen); EXPORT_SYMBOL(strpbrk); EXPORT_SYMBOL(strrchr); -EXPORT_SYMBOL(strstr); EXPORT_SYMBOL(memset); EXPORT_SYMBOL(memcpy); EXPORT_SYMBOL(memmove); -EXPORT_SYMBOL(memcmp); -EXPORT_SYMBOL(memscan); EXPORT_SYMBOL(memchr); EXPORT_SYMBOL(__memzero); @@ -190,8 +179,6 @@ EXPORT_SYMBOL(_find_next_bit_be); /* syscalls */ EXPORT_SYMBOL(sys_write); -EXPORT_SYMBOL(sys_read); EXPORT_SYMBOL(sys_lseek); -EXPORT_SYMBOL(sys_open); EXPORT_SYMBOL(sys_exit); EXPORT_SYMBOL(sys_wait4); -- cgit v1.2.3 From 50c37e216132d2185a15d5cf6b966adf6ecea535 Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Sat, 1 Apr 2006 12:13:31 +0100 Subject: [ARM] 3436/1: 2.6.16-git18: collie_defconfig broken Patch from Pavel Machek > The kautobuild found the following error while trying to build 2.6.16-git18 > using collie_defconfig: > > arch/arm/mach-sa1100/collie.c:92: error: 'collie_uart_set_mctrl' undeclared here (not in a function) > arch/arm/mach-sa1100/collie.c:93: error: 'collie_uart_get_mctrl' undeclared here (not in a function) > make[1]: *** [arch/arm/mach-sa1100/collie.o] Error 1 > make: *** [arch/arm/mach-sa1100] Error 2 > make: Leaving directory `/var/tmp/kernel-orig' This fixes above compile error by adding missing pieces of uart support, and fixes compilation. Signed-off-by: Pavel Machek Signed-off-by: Russell King --- arch/arm/mach-sa1100/collie.c | 72 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 71 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 102454082474..676b5c5b75bb 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -11,7 +11,8 @@ * published by the Free Software Foundation. * * ChangeLog: - * 03-06-2004 John Lenz + * 2006 Pavel Machek + * 03-06-2004 John Lenz * 06-04-2002 Chris Larson * 04-16-2001 Lineo Japan,Inc. ... */ @@ -87,12 +88,75 @@ static struct mcp_plat_data collie_mcp_data = { .sclk_rate = 11981000, }; +#ifdef CONFIG_SHARP_LOCOMO +/* + * low-level UART features. + */ +static struct locomo_dev *uart_dev = NULL; + +static void collie_uart_set_mctrl(struct uart_port *port, u_int mctrl) +{ + if (!uart_dev) return; + + if (mctrl & TIOCM_RTS) + locomo_gpio_write(uart_dev, LOCOMO_GPIO_RTS, 0); + else + locomo_gpio_write(uart_dev, LOCOMO_GPIO_RTS, 1); + + if (mctrl & TIOCM_DTR) + locomo_gpio_write(uart_dev, LOCOMO_GPIO_DTR, 0); + else + locomo_gpio_write(uart_dev, LOCOMO_GPIO_DTR, 1); +} + +static u_int collie_uart_get_mctrl(struct uart_port *port) +{ + int ret = TIOCM_CD; + unsigned int r; + if (!uart_dev) return ret; + + r = locomo_gpio_read_output(uart_dev, LOCOMO_GPIO_CTS & LOCOMO_GPIO_DSR); + if (r & LOCOMO_GPIO_CTS) + ret |= TIOCM_CTS; + if (r & LOCOMO_GPIO_DSR) + ret |= TIOCM_DSR; + + return ret; +} static struct sa1100_port_fns collie_port_fns __initdata = { .set_mctrl = collie_uart_set_mctrl, .get_mctrl = collie_uart_get_mctrl, }; +static int collie_uart_probe(struct locomo_dev *dev) +{ + uart_dev = dev; + return 0; +} + +static int collie_uart_remove(struct locomo_dev *dev) +{ + uart_dev = NULL; + return 0; +} + +static struct locomo_driver collie_uart_driver = { + .drv = { + .name = "collie_uart", + }, + .devid = LOCOMO_DEVID_UART, + .probe = collie_uart_probe, + .remove = collie_uart_remove, +}; + +static int __init collie_uart_init(void) { + return locomo_driver_register(&collie_uart_driver); +} +device_initcall(collie_uart_init); + +#endif + static struct resource locomo_resources[] = { [0] = { @@ -218,6 +282,12 @@ static void __init collie_map_io(void) { sa1100_map_io(); iotable_init(collie_io_desc, ARRAY_SIZE(collie_io_desc)); + +#ifdef CONFIG_SHARP_LOCOMO + sa1100_register_uart_fns(&collie_port_fns); +#endif + sa1100_register_uart(0, 3); + sa1100_register_uart(1, 1); } MACHINE_START(COLLIE, "Sharp-Collie") -- cgit v1.2.3 From 532bda5d9cd2f94a9e374765c23858c7d8641f66 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sat, 1 Apr 2006 18:33:35 +0100 Subject: [ARM] 3438/1: ixp23xx: add pci slave support Patch from Lennert Buytenhek On the Double Espresso board, the IXP2350s are PCI slave devices and we skip calling pci_common_init() as that enumerates the bus. But even though we are a PCI slave device, there is still some PCI-related setup that has to be done. Create ixp23xx_pci_common_init(), move the common initialisation bits there, and have this function called from both the PCI master and the PCI slave init path. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ixp23xx/espresso.c | 9 +++++++++ arch/arm/mach-ixp23xx/pci.c | 12 +++++++++++- include/asm-arm/arch-ixp23xx/platform.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c index 2327c9790416..bf688c128630 100644 --- a/arch/arm/mach-ixp23xx/espresso.c +++ b/arch/arm/mach-ixp23xx/espresso.c @@ -44,6 +44,15 @@ #include #include +static int __init espresso_pci_init(void) +{ + if (machine_is_espresso()) + ixp23xx_pci_slave_init(); + + return 0; +}; +subsys_initcall(espresso_pci_init); + static void __init espresso_init(void) { physmap_configure(0x90000000, 0x02000000, 2, NULL); diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c index 5330ad78c1bb..ba6b4367a1d5 100644 --- a/arch/arm/mach-ixp23xx/pci.c +++ b/arch/arm/mach-ixp23xx/pci.c @@ -201,7 +201,7 @@ int clear_master_aborts(void) return 0; } -void __init ixp23xx_pci_preinit(void) +static void __init ixp23xx_pci_common_init(void) { #ifdef __ARMEB__ *IXP23XX_PCI_CONTROL |= 0x20000; /* set I/O swapping */ @@ -220,6 +220,11 @@ void __init ixp23xx_pci_preinit(void) } else { *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1); } +} + +void __init ixp23xx_pci_preinit(void) +{ + ixp23xx_pci_common_init(); hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, "PCI config cycle to non-existent device"); @@ -273,3 +278,8 @@ int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys) return 1; } + +void ixp23xx_pci_slave_init(void) +{ + ixp23xx_pci_common_init(); +} diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h index f85b4685a491..e4d99060a049 100644 --- a/include/asm-arm/arch-ixp23xx/platform.h +++ b/include/asm-arm/arch-ixp23xx/platform.h @@ -22,6 +22,7 @@ void ixp23xx_sys_init(void); int ixp23xx_pci_setup(int, struct pci_sys_data *); void ixp23xx_pci_preinit(void); struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*); +void ixp23xx_pci_slave_init(void); extern struct sys_timer ixp23xx_timer; -- cgit v1.2.3 From d3f4c571b6e596f9d39c596426269006a309d3b8 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sat, 1 Apr 2006 18:33:42 +0100 Subject: [ARM] 3440/1: [S3C2410] make SMDK2410 and SMDK2440 similarities common Patch from Ben Dooks The SMDK2410 and SMDK2440 boards have a number of items in common, including the LEDs, Ethernet, PCMCIA. Make a common SMDK support file. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/Kconfig | 7 +++++ arch/arm/mach-s3c2410/Makefile | 2 ++ arch/arm/mach-s3c2410/common-smdk.c | 51 +++++++++++++++++++++++++++++++++++ arch/arm/mach-s3c2410/common-smdk.h | 15 +++++++++++ arch/arm/mach-s3c2410/mach-smdk2410.c | 13 +++++---- arch/arm/mach-s3c2410/mach-smdk2440.c | 17 +++--------- 6 files changed, 84 insertions(+), 21 deletions(-) create mode 100644 arch/arm/mach-s3c2410/common-smdk.c create mode 100644 arch/arm/mach-s3c2410/common-smdk.h diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index ed07c4149d82..ce7d81000695 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig @@ -50,9 +50,15 @@ config MACH_N30 . +config MACH_SMDK + bool + help + Common machine code for SMDK2410 and SMDK2440 + config ARCH_SMDK2410 bool "SMDK2410/A9M2410" select CPU_S3C2410 + select MACH_SMDK help Say Y here if you are using the SMDK2410 or the derived module A9M2410 @@ -60,6 +66,7 @@ config ARCH_SMDK2410 config ARCH_S3C2440 bool "SMDK2440" select CPU_S3C2440 + select MACH_SMDK help Say Y here if you are using the SMDK2440. diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 1b3b476e5637..3e5712db6b52 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile @@ -48,3 +48,5 @@ obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o obj-$(CONFIG_MACH_OTOM) += mach-otom.o obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o + +obj-$(CONFIG_MACH_SMDK) += common-smdk.o \ No newline at end of file diff --git a/arch/arm/mach-s3c2410/common-smdk.c b/arch/arm/mach-s3c2410/common-smdk.c new file mode 100644 index 000000000000..b054f8ff53f7 --- /dev/null +++ b/arch/arm/mach-s3c2410/common-smdk.c @@ -0,0 +1,51 @@ +/* linux/arch/arm/mach-s3c2410/common-smdk.c + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * Common code for SMDK2410 and SMDK2440 boards + * + * http://www.fluff.org/ben/smdk2440/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "pm.h" + +void __init smdk_machine_init(void) +{ + /* Configure the LEDs (even if we have no LED support)*/ + + s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP); + s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP); + s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP); + s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP); + + s3c2410_gpio_setpin(S3C2410_GPF4, 0); + s3c2410_gpio_setpin(S3C2410_GPF5, 0); + s3c2410_gpio_setpin(S3C2410_GPF6, 0); + s3c2410_gpio_setpin(S3C2410_GPF7, 0); + + s3c2410_pm_init(); +} diff --git a/arch/arm/mach-s3c2410/common-smdk.h b/arch/arm/mach-s3c2410/common-smdk.h new file mode 100644 index 000000000000..0e3a3be330a3 --- /dev/null +++ b/arch/arm/mach-s3c2410/common-smdk.h @@ -0,0 +1,15 @@ +/* linux/arch/arm/mach-s3c2410/common-smdk.h + * + * Copyright (c) 2006 Simtec Electronics + * Ben Dooks + * + * Common code for SMDK2410 and SMDK2440 boards + * + * http://www.fluff.org/ben/smdk2440/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +extern void smdk_machine_init(void); diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index 1e76e1fdfcea..2db932d72c5a 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c @@ -28,7 +28,8 @@ * Ben Dooks * * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA - * 20-Sep-2005 BJD Added static to non-exported items + * 20-Sep-2005 BJD Added static to non-exported items + * 01-Apr-2006 BJD Moved init code to common smdk * ***********************************************************************/ @@ -54,6 +55,8 @@ #include "devs.h" #include "cpu.h" +#include "common-smdk.h" + static struct map_desc smdk2410_iodesc[] __initdata = { /* nothing here yet */ }; @@ -107,11 +110,6 @@ static void __init smdk2410_map_io(void) s3c24xx_set_board(&smdk2410_board); } -static void __init smdk2410_init_irq(void) -{ - s3c24xx_init_irq(); -} - MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch * to SMDK2410 */ /* Maintainer: Jonas Dietsche */ @@ -119,7 +117,8 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .boot_params = S3C2410_SDRAM_PA + 0x100, .map_io = smdk2410_map_io, - .init_irq = smdk2410_init_irq, + .init_irq = s3c24xx_init_irq, + .init_machine = smdk_machine_init, .timer = &s3c24xx_timer, MACHINE_END diff --git a/arch/arm/mach-s3c2410/mach-smdk2440.c b/arch/arm/mach-s3c2410/mach-smdk2440.c index f4315721c3b8..5fffd1d51047 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2440.c +++ b/arch/arm/mach-s3c2410/mach-smdk2440.c @@ -53,7 +53,8 @@ #include "clock.h" #include "devs.h" #include "cpu.h" -#include "pm.h" + +#include "common-smdk.h" static struct map_desc smdk2440_iodesc[] __initdata = { /* ISA IO Space map (memory space selected by A24) */ @@ -197,21 +198,9 @@ static void __init smdk2440_map_io(void) static void __init smdk2440_machine_init(void) { - /* Configure the LEDs (even if we have no LED support)*/ - - s3c2410_gpio_cfgpin(S3C2410_GPF4, S3C2410_GPF4_OUTP); - s3c2410_gpio_cfgpin(S3C2410_GPF5, S3C2410_GPF5_OUTP); - s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP); - s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP); - - s3c2410_gpio_setpin(S3C2410_GPF4, 0); - s3c2410_gpio_setpin(S3C2410_GPF5, 0); - s3c2410_gpio_setpin(S3C2410_GPF6, 0); - s3c2410_gpio_setpin(S3C2410_GPF7, 0); - s3c24xx_fb_set_platdata(&smdk2440_lcd_cfg); - s3c2410_pm_init(); + smdk_machine_init(); } MACHINE_START(S3C2440, "SMDK2440") -- cgit v1.2.3 From 23759dc6430428897a36c4d493f611eca55c9481 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sun, 2 Apr 2006 00:07:39 +0100 Subject: [ARM] 3439/2: xsc3: add I/O coherency support Patch from Lennert Buytenhek This patch adds support for the I/O coherent cache available on the xsc3. The approach is to provide a simple API to determine whether the chipset supports coherency by calling arch_is_coherent() and then setting the appropriate system memory PTE and PMD bits. In addition, we call this API on dma_alloc_coherent() and dma_map_single() calls. A generic version exists that will compile out all the coherency-related code that is not needed on the majority of ARM systems. Note that we do not check for coherency in the dma_alloc_writecombine() function as that still requires a special PTE setting. We also don't touch dma_mmap_coherent() as that is a special ARM-only API that is by definition only used on non-coherent system. Signed-off-by: Deepak Saxena Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/kernel/setup.c | 3 +++ arch/arm/mach-ixp23xx/pci.c | 6 ++++++ arch/arm/mm/consistent.c | 17 +++++++++++++++++ arch/arm/mm/mm-armv.c | 11 +++++++++++ arch/arm/mm/proc-xsc3.S | 2 +- include/asm-arm/arch-ixp23xx/memory.h | 17 +++++++++++++++++ include/asm-arm/dma-mapping.h | 22 +++++++++++++++------- include/asm-arm/memory.h | 8 ++++++++ include/asm-arm/pgtable-hwdef.h | 1 + include/asm-arm/pgtable.h | 1 + 10 files changed, 80 insertions(+), 8 deletions(-) diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index b7cd280bfd63..437528403959 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -252,6 +252,9 @@ static void __init dump_cpu_info(int cpu) dump_cache("cache", cpu, CACHE_ISIZE(info)); } } + + if (arch_is_coherent()) + printk("Cache coherency enabled\n"); } int cpu_architecture(void) diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c index ba6b4367a1d5..ac72f94c5b4d 100644 --- a/arch/arm/mach-ixp23xx/pci.c +++ b/arch/arm/mach-ixp23xx/pci.c @@ -219,6 +219,12 @@ static void __init ixp23xx_pci_common_init(void) *IXP23XX_PCI_CPP_ADDR_BITS &= ~(1 << 1); } else { *IXP23XX_PCI_CPP_ADDR_BITS |= (1 << 1); + + /* + * Enable coherency on A2 silicon. + */ + if (arch_is_coherent()) + *IXP23XX_CPP2XSI_CURR_XFER_REG3 &= ~IXP23XX_CPP2XSI_COH_OFF; } } diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c index 8a1bfcd50087..50e6b6bfb2e2 100644 --- a/arch/arm/mm/consistent.c +++ b/arch/arm/mm/consistent.c @@ -18,6 +18,7 @@ #include #include +#include #include #include #include @@ -272,6 +273,17 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, void * dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) { + if (arch_is_coherent()) { + void *virt; + + virt = kmalloc(size, gfp); + if (!virt) + return NULL; + *handle = virt_to_dma(dev, virt); + + return virt; + } + return __dma_alloc(dev, size, handle, gfp, pgprot_noncached(pgprot_kernel)); } @@ -350,6 +362,11 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr WARN_ON(irqs_disabled()); + if (arch_is_coherent()) { + kfree(cpu_addr); + return; + } + size = PAGE_ALIGN(size); spin_lock_irqsave(&consistent_lock, flags); diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c index 5e5d05bcad50..f14b2d0f3690 100644 --- a/arch/arm/mm/mm-armv.c +++ b/arch/arm/mm/mm-armv.c @@ -388,6 +388,17 @@ void __init build_mem_type_table(void) cp = &cache_policies[cachepolicy]; kern_pgprot = user_pgprot = cp->pte; + /* + * Enable CPU-specific coherency if supported. + * (Only available on XSC3 at the moment.) + */ + if (arch_is_coherent()) { + if (cpu_is_xsc3()) { + mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; + mem_types[MT_MEMORY].prot_pte |= L_PTE_COHERENT; + } + } + /* * ARMv6 and above have extended page tables. */ diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index b9dfce57c272..80873b36c3f7 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -371,7 +371,7 @@ ENTRY(cpu_xsc3_switch_mm) ENTRY(cpu_xsc3_set_pte) str r1, [r0], #-2048 @ linux version - bic r2, r1, #0xff0 + bic r2, r1, #0xdf0 @ Keep C, B, coherency bits orr r2, r2, #PTE_TYPE_EXT @ extended page eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY diff --git a/include/asm-arm/arch-ixp23xx/memory.h b/include/asm-arm/arch-ixp23xx/memory.h index bebcf0aa0d72..6e19f46d54d1 100644 --- a/include/asm-arm/arch-ixp23xx/memory.h +++ b/include/asm-arm/arch-ixp23xx/memory.h @@ -28,6 +28,7 @@ * to an address that the kernel can use. */ #ifndef __ASSEMBLY__ +#include #define __virt_to_bus(v) \ ({ unsigned int ret; \ @@ -40,6 +41,22 @@ data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR); \ __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); }) +/* + * Coherency support. Only supported on A2 CPUs or on A1 + * systems that have the cache coherency workaround. + */ +static inline int __ixp23xx_arch_is_coherent(void) +{ + extern unsigned int processor_id; + + if (((processor_id & 15) >= 2) || machine_is_roadrunner()) + return 1; + + return 0; +} + +#define arch_is_coherent() __ixp23xx_arch_is_coherent() + #endif diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h index e3e8541ee63b..63ca7412a462 100644 --- a/include/asm-arm/dma-mapping.h +++ b/include/asm-arm/dma-mapping.h @@ -47,7 +47,7 @@ static inline int dma_get_cache_alignment(void) static inline int dma_is_consistent(dma_addr_t handle) { - return 0; + return !!arch_is_coherent(); } /* @@ -145,7 +145,9 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction dir) { - consistent_sync(cpu_addr, size, dir); + if (!arch_is_coherent()) + consistent_sync(cpu_addr, size, dir); + return virt_to_dma(dev, (unsigned long)cpu_addr); } #else @@ -255,7 +257,9 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, sg->dma_address = page_to_dma(dev, sg->page) + sg->offset; virt = page_address(sg->page) + sg->offset; - consistent_sync(virt, sg->length, dir); + + if (!arch_is_coherent()) + consistent_sync(virt, sg->length, dir); } return nents; @@ -310,14 +314,16 @@ static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, enum dma_data_direction dir) { - consistent_sync((void *)dma_to_virt(dev, handle), size, dir); + if (!arch_is_coherent()) + consistent_sync((void *)dma_to_virt(dev, handle), size, dir); } static inline void dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, enum dma_data_direction dir) { - consistent_sync((void *)dma_to_virt(dev, handle), size, dir); + if (!arch_is_coherent()) + consistent_sync((void *)dma_to_virt(dev, handle), size, dir); } #else extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); @@ -347,7 +353,8 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { char *virt = page_address(sg->page) + sg->offset; - consistent_sync(virt, sg->length, dir); + if (!arch_is_coherent()) + consistent_sync(virt, sg->length, dir); } } @@ -359,7 +366,8 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { char *virt = page_address(sg->page) + sg->offset; - consistent_sync(virt, sg->length, dir); + if (!arch_is_coherent()) + consistent_sync(virt, sg->length, dir); } } #else diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h index afa5c3ea077c..2b3cf69b3ed9 100644 --- a/include/asm-arm/memory.h +++ b/include/asm-arm/memory.h @@ -234,6 +234,14 @@ static inline __deprecated void *bus_to_virt(unsigned long x) #define virt_to_dma(dev, addr) (__arch_virt_to_dma(dev, addr)) #endif +/* + * Optional coherency support. Currently used only by selected + * Intel XSC3-based systems. + */ +#ifndef arch_is_coherent +#define arch_is_coherent() 0 +#endif + #endif #include diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h index 1d033495cc75..1bc1f997bda2 100644 --- a/include/asm-arm/pgtable-hwdef.h +++ b/include/asm-arm/pgtable-hwdef.h @@ -73,6 +73,7 @@ #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) #define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ #define PTE_EXT_APX (1 << 9) /* v6 */ +#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */ #define PTE_EXT_SHARED (1 << 10) /* v6 */ #define PTE_EXT_NG (1 << 11) /* v6 */ diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h index e595ae24efe2..e85c08d78dda 100644 --- a/include/asm-arm/pgtable.h +++ b/include/asm-arm/pgtable.h @@ -156,6 +156,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val); #define L_PTE_WRITE (1 << 5) #define L_PTE_EXEC (1 << 6) #define L_PTE_DIRTY (1 << 7) +#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */ #define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */ #define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */ -- cgit v1.2.3 From 26f91fd54dba57a9bfe2373242ad71792d7af610 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 2 Apr 2006 00:09:26 +0100 Subject: [ARM] 3443/1: [S3C2410] Improve IRQ entry code Patch from Ben Dooks Remove the old debug from the IRQ entry code, update the comments on the handling of the IRQ registers. The message "bad interrupt offset" is removed as it is only helpful for debugging, and can cause printk() flooding when under load. Make the code to deal with GPIO interrupts faster, and use the same path to deal with unexplained results from the IRQ registers. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/entry-macro.S | 167 ++++++++++++----------------- 1 file changed, 67 insertions(+), 100 deletions(-) diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S index cc06b1bd37b2..894c35cf3b1e 100644 --- a/include/asm-arm/arch-s3c2410/entry-macro.S +++ b/include/asm-arm/arch-s3c2410/entry-macro.S @@ -6,116 +6,83 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. +*/ + +/* We have a problem that the INTOFFSET register does not always + * show one interrupt. Occasionally we get two interrupts through + * the prioritiser, and this causes the INTOFFSET register to show + * what looks like the logical-or of the two interrupt numbers. + * + * Thanks to Klaus, Shannon, et al for helping to debug this problem +*/ + +#define INTPND (0x10) +#define INTOFFSET (0x14) +#define EXTINTPEND (0xa8) +#define EXTINTMASK (0xa4) - * Modifications: - * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA - */ #include #include - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp - mov \tmp, #S3C24XX_VA_IRQ - ldr \irqnr, [ \tmp, #0x14 ] @ get irq no -30000: - teq \irqnr, #4 - teqne \irqnr, #5 - beq 1002f @ external irq reg - - @ debug check to see if interrupt reported is the same - @ as the offset.... - - teq \irqnr, #0 - beq 20002f - ldr \irqstat, [ \tmp, #0x10 ] @ INTPND - mov \irqstat, \irqstat, lsr \irqnr - tst \irqstat, #1 - bne 20002f - - /* debug/warning if we get an invalud response from the - * INTOFFSET register */ -#if 1 - stmfd r13!, { r0 - r4 , r8-r12, r14 } - ldr r1, [ \tmp, #0x14 ] @ INTOFFSET - ldr r2, [ \tmp, #0x10 ] @ INTPND - ldr r3, [ \tmp, #0x00 ] @ SRCPND - adr r0, 20003f - bl printk - b 20004f - -20003: - .ascii "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n" - .byte 0 - .align 4 -20004: - mov r1, #1 - mov \tmp, #S3C24XX_VA_IRQ - ldmfd r13!, { r0 - r4 , r8-r12, r14 } -#endif - - @ try working out interrupt number for ourselves - mov \irqnr, #0 - ldr \irqstat, [ \tmp, #0x10 ] @ INTPND -10021: - movs \irqstat, \irqstat, lsr#1 - bcs 30000b @ try and re-start the proccess - add \irqnr, \irqnr, #1 - cmp \irqnr, #32 - ble 10021b - - @ found no interrupt, set Z flag and leave - movs \irqnr, #0 - b 1001f - -20005: -20002: @ exit - @ we base the s3c2410x interrupts at 16 and above to allow - @ isa peripherals to have their standard interrupts, also - @ ensure that Z flag is un-set on exit - - @ note, we cannot be sure if we get IRQ_EINT0 (0) that - @ there is simply no interrupt pending, so in all other - @ cases we jump to say we have found something, otherwise - @ we check to see if the interrupt really is assrted - adds \irqnr, \irqnr, #IRQ_EINT0 - teq \irqnr, #IRQ_EINT0 - bne 1001f @ exit - ldr \irqstat, [ \tmp, #0x10 ] @ INTPND - teq \irqstat, #0 - moveq \irqnr, #0 - b 1001f - - @ we get here from no main or external interrupts pending -1002: - add \tmp, \tmp, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ - ldr \irqstat, [ \tmp, # 0xa8 ] @ EXTINTPEND - ldr \irqnr, [ \tmp, # 0xa4 ] @ EXTINTMASK - - bic \irqstat, \irqstat, \irqnr @ clear masked irqs - - mov \irqnr, #IRQ_EINT4 @ start extint nos - mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits -10021: - movs \irqstat, \irqstat, lsr#1 - bcs 1004f - add \irqnr, \irqnr, #1 - cmp \irqnr, #IRQ_EINT23 - ble 10021b - - @ found no interrupt, set Z flag and leave - movs \irqnr, #0 - -1004: @ ensure Z flag clear in case our MOVS shifted out the last bit - teq \irqnr, #0 + mov \base, #S3C24XX_VA_IRQ + + ldr \irqstat, [ \base, #INTPND] + bics \irqnr, \irqstat, #3<<4 @@ only an GPIO IRQ + beq 2000f + + @@ try the interrupt offset register, since it is there + + ldr \irqnr, [ \base, #INTOFFSET ] + mov \tmp, #1 + tst \irqstat, \tmp, lsl \irqnr + addne \irqnr, \irqnr, #IRQ_EINT0 + bne 1001f + + @@ the number specified is not a valid irq, so try + @@ and work it out for ourselves + + mov \irqnr, #IRQ_EINT0 @@ start here + b 3000f + +2000: + @@ load the GPIO interrupt register, and check it + + add \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ + ldr \irqstat, [ \tmp, # EXTINTPEND ] + ldr \irqnr, [ \tmp, # EXTINTMASK ] + bics \irqstat, \irqstat, \irqnr + beq 1001f + + mov \irqnr, #(IRQ_EINT4 - 4) + + @@ work out which irq (if any) we got +3000: + movs \tmp, \irqstat, lsl#16 + addeq \irqnr, \irqnr, #16 + moveq \irqstat, \irqstat, lsr#16 + tst \irqstat, #0xff + addeq \irqnr, \irqnr, #8 + moveq \irqstat, \irqstat, lsr#8 + tst \irqstat, #0xf + addeq \irqnr, \irqnr, #4 + moveq \irqstat, \irqstat, lsr#4 + tst \irqstat, #0x3 + addeq \irqnr, \irqnr, #2 + moveq \irqstat, \irqstat, lsr#2 + tst \irqstat, #0x1 + addeq \irqnr, \irqnr, #1 + + @@ we have the value + movs \irqnr, \irqnr + 1001: - @ exit irq routine - .endm + @@ exit here, Z flag unset if IRQ + .endm /* currently don't need an disable_fiq macro */ .macro disable_fiq .endm - - -- cgit v1.2.3 From 66ce229fe057e35275a5f5176b29ed70795506a1 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 2 Apr 2006 10:00:08 +0100 Subject: [ARM] 3447/1: [S3C2410] SMDK - default LEDs to off Patch from Ben Dooks Set default state of LEDs to off Fixes context of Patch #3442/1 Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/common-smdk.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-s3c2410/common-smdk.c b/arch/arm/mach-s3c2410/common-smdk.c index b054f8ff53f7..f903dc2ab29b 100644 --- a/arch/arm/mach-s3c2410/common-smdk.c +++ b/arch/arm/mach-s3c2410/common-smdk.c @@ -42,10 +42,10 @@ void __init smdk_machine_init(void) s3c2410_gpio_cfgpin(S3C2410_GPF6, S3C2410_GPF6_OUTP); s3c2410_gpio_cfgpin(S3C2410_GPF7, S3C2410_GPF7_OUTP); - s3c2410_gpio_setpin(S3C2410_GPF4, 0); - s3c2410_gpio_setpin(S3C2410_GPF5, 0); - s3c2410_gpio_setpin(S3C2410_GPF6, 0); - s3c2410_gpio_setpin(S3C2410_GPF7, 0); + s3c2410_gpio_setpin(S3C2410_GPF4, 1); + s3c2410_gpio_setpin(S3C2410_GPF5, 1); + s3c2410_gpio_setpin(S3C2410_GPF6, 1); + s3c2410_gpio_setpin(S3C2410_GPF7, 1); s3c2410_pm_init(); } -- cgit v1.2.3 From dee9b2e932ef7c8f19540ad67e425fae30f33421 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 2 Apr 2006 10:00:09 +0100 Subject: [ARM] 3442/1: [S3C2410] SMDK: NAND device setup Patch from Ben Dooks Add SMDK2410/SMDK2440 NAND device information and default partition table. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/common-smdk.c | 85 ++++++++++++++++++++++++++++++++++++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-s3c2410/common-smdk.c b/arch/arm/mach-s3c2410/common-smdk.c index f903dc2ab29b..36b8291b5e03 100644 --- a/arch/arm/mach-s3c2410/common-smdk.c +++ b/arch/arm/mach-s3c2410/common-smdk.c @@ -20,6 +20,11 @@ #include #include +#include +#include +#include +#include + #include #include #include @@ -27,12 +32,86 @@ #include #include #include -#include #include +#include + +#include "devs.h" #include "pm.h" +/* NAND parititon from 2.4.18-swl5 */ + +static struct mtd_partition smdk_default_nand_part[] = { + [0] = { + .name = "Boot Agent", + .size = SZ_16K, + .offset = 0, + }, + [1] = { + .name = "S3C2410 flash parition 1", + .offset = 0, + .size = SZ_2M, + }, + [2] = { + .name = "S3C2410 flash partition 2", + .offset = SZ_4M, + .size = SZ_4M, + }, + [3] = { + .name = "S3C2410 flash partition 3", + .offset = SZ_8M, + .size = SZ_2M, + }, + [4] = { + .name = "S3C2410 flash partition 4", + .offset = SZ_1M * 10, + .size = SZ_4M, + }, + [5] = { + .name = "S3C2410 flash partition 5", + .offset = SZ_1M * 14, + .size = SZ_1M * 10, + }, + [6] = { + .name = "S3C2410 flash partition 6", + .offset = SZ_1M * 24, + .size = SZ_1M * 24, + }, + [7] = { + .name = "S3C2410 flash partition 7", + .offset = SZ_1M * 48, + .size = SZ_16M, + } +}; + +static struct s3c2410_nand_set smdk_nand_sets[] = { + [0] = { + .name = "NAND", + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(smdk_default_nand_part), + .partitions = smdk_default_nand_part, + }, +}; + +/* choose a set of timings which should suit most 512Mbit + * chips and beyond. +*/ + +static struct s3c2410_platform_nand smdk_nand_info = { + .tacls = 20, + .twrph0 = 60, + .twrph1 = 20, + .nr_sets = ARRAY_SIZE(smdk_nand_sets), + .sets = smdk_nand_sets, +}; + +/* devices we initialise */ + +static struct platform_device __initdata *smdk_devs[] = { + &s3c_device_nand, +}; + void __init smdk_machine_init(void) { /* Configure the LEDs (even if we have no LED support)*/ @@ -47,5 +126,9 @@ void __init smdk_machine_init(void) s3c2410_gpio_setpin(S3C2410_GPF6, 1); s3c2410_gpio_setpin(S3C2410_GPF7, 1); + s3c_device_nand.dev.platform_data = &smdk_nand_info; + + platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); + s3c2410_pm_init(); } -- cgit v1.2.3 From 2b2ee1585a98be250f86c61e6ec70159b30e48e5 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 2 Apr 2006 10:00:10 +0100 Subject: [ARM] 3448/1: [S3C2410] Settle delay when _enabling_ USB PLL Patch from Ben Dooks Fix the bug in the UPLL enable code which should have put a 200uS delay in if enabling the USB PLL from the state where it is off. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c index fec02c92f95f..b7f85e6d6b76 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/mach-s3c2410/clock.c @@ -249,7 +249,7 @@ static int s3c24xx_upll_enable(struct clk *clk, int enable) /* if we started the UPLL, then allow to settle */ - if (enable && !(orig & S3C2410_CLKSLOW_UCLK_OFF)) + if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF)) udelay(200); return 0; -- cgit v1.2.3 From 661e6acf7b882e5a886845dca5d1559e987464b4 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 2 Apr 2006 10:32:46 +0100 Subject: [ARM] 3449/1: [S3C2410] Anubis - fix NAND timings Patch from Ben Dooks The NAND timings on the Anubis are too large to be selected when running at 133MHz memory clock. Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/mach-anubis.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c index 3e327b8e46be..cc97fbf66291 100644 --- a/arch/arm/mach-s3c2410/mach-anubis.c +++ b/arch/arm/mach-s3c2410/mach-anubis.c @@ -232,8 +232,8 @@ static void anubis_nand_select(struct s3c2410_nand_set *set, int slot) static struct s3c2410_platform_nand anubis_nand_info = { .tacls = 25, - .twrph0 = 80, - .twrph1 = 80, + .twrph0 = 55, + .twrph1 = 40, .nr_sets = ARRAY_SIZE(anubis_nand_sets), .sets = anubis_nand_sets, .select_chip = anubis_nand_select, -- cgit v1.2.3 From 272eb575eb3d5348fe0f0a97a22b5e603bd51d11 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Sun, 2 Apr 2006 16:16:15 +0100 Subject: [ARM] 3452/1: [S3C2410] RX3715 - add nand information Patch from Ben Dooks NAND definitions for the HP iPAQ RX3715's internal NAND flash Signed-off-by: Ben Dooks Signed-off-by: Russell King --- arch/arm/mach-s3c2410/mach-rx3715.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c index 0260ed5ab946..306afc1d7cd3 100644 --- a/arch/arm/mach-s3c2410/mach-rx3715.c +++ b/arch/arm/mach-s3c2410/mach-rx3715.c @@ -32,6 +32,11 @@ #include #include +#include +#include +#include +#include + #include #include #include @@ -46,6 +51,7 @@ #include #include +#include #include #include "clock.h" @@ -170,12 +176,39 @@ static struct s3c2410fb_mach_info rx3715_lcdcfg __initdata = { }, }; +static struct mtd_partition rx3715_nand_part[] = { + [0] = { + .name = "Whole Flash", + .offset = 0, + .size = MTDPART_SIZ_FULL, + .mask_flags = MTD_WRITEABLE, + } +}; + +static struct s3c2410_nand_set rx3715_nand_sets[] = { + [0] = { + .name = "Internal", + .nr_chips = 1, + .nr_partitions = ARRAY_SIZE(rx3715_nand_part), + .partitions = rx3715_nand_part, + }, +}; + +static struct s3c2410_platform_nand rx3715_nand_info = { + .tacls = 25, + .twrph0 = 50, + .twrph1 = 15, + .nr_sets = ARRAY_SIZE(rx3715_nand_sets), + .sets = rx3715_nand_sets, +}; + static struct platform_device *rx3715_devices[] __initdata = { &s3c_device_usb, &s3c_device_lcd, &s3c_device_wdt, &s3c_device_i2c, &s3c_device_iis, + &s3c_device_nand, }; static struct s3c24xx_board rx3715_board __initdata = { @@ -185,6 +218,8 @@ static struct s3c24xx_board rx3715_board __initdata = { static void __init rx3715_map_io(void) { + s3c_device_nand.dev.platform_data = &rx3715_nand_info; + s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc)); s3c24xx_init_clocks(16934000); s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs)); -- cgit v1.2.3 From 41658132e650c01529dd5cc5cea8b0055def1165 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sun, 2 Apr 2006 16:17:34 +0100 Subject: [ARM] 3450/1: ep93xx: use the ep93xx rtc driver Patch from Lennert Buytenhek Instantiate the recently merged ep93xx rtc driver in the ep93xx code. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ep93xx/core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 2d892e4daa07..dcd417625389 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c @@ -424,6 +424,14 @@ static struct amba_device uart3_device = { .periphid = 0x00041010, }; + +static struct platform_device ep93xx_rtc_device = { + .name = "ep93xx-rtc", + .id = -1, + .num_resources = 0, +}; + + void __init ep93xx_init_devices(void) { unsigned int v; @@ -439,4 +447,6 @@ void __init ep93xx_init_devices(void) amba_device_register(&uart1_device, &iomem_resource); amba_device_register(&uart2_device, &iomem_resource); amba_device_register(&uart3_device, &iomem_resource); + + platform_device_register(&ep93xx_rtc_device); } -- cgit v1.2.3 From 7ba01f9728a9f1cd1a3e1e2d5206f76061182675 Mon Sep 17 00:00:00 2001 From: Lennert Buytenhek Date: Sun, 2 Apr 2006 16:17:40 +0100 Subject: [ARM] 3451/1: ep93xx: use the m48t86 rtc driver on the ts72xx platform Patch from Lennert Buytenhek Instantiate the recently merged m48t86 rtc driver in the ts72xx code. Signed-off-by: Lennert Buytenhek Signed-off-by: Russell King --- arch/arm/mach-ep93xx/ts72xx.c | 39 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-ep93xx/ts72xx.h | 11 ++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index 777e75daa8a5..9be01b0c3f48 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c @@ -17,6 +17,8 @@ #include #include #include +#include +#include #include #include #include @@ -39,6 +41,16 @@ static struct map_desc ts72xx_io_desc[] __initdata = { .pfn = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE), .length = TS72XX_OPTIONS2_SIZE, .type = MT_DEVICE, + }, { + .virtual = TS72XX_RTC_INDEX_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_RTC_INDEX_PHYS_BASE), + .length = TS72XX_RTC_INDEX_SIZE, + .type = MT_DEVICE, + }, { + .virtual = TS72XX_RTC_DATA_VIRT_BASE, + .pfn = __phys_to_pfn(TS72XX_RTC_DATA_PHYS_BASE), + .length = TS72XX_RTC_DATA_SIZE, + .type = MT_DEVICE, } }; @@ -99,11 +111,38 @@ static void __init ts72xx_map_io(void) } } +static unsigned char ts72xx_rtc_readb(unsigned long addr) +{ + __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE); + return __raw_readb(TS72XX_RTC_DATA_VIRT_BASE); +} + +static void ts72xx_rtc_writeb(unsigned char value, unsigned long addr) +{ + __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE); + __raw_writeb(value, TS72XX_RTC_DATA_VIRT_BASE); +} + +static struct m48t86_ops ts72xx_rtc_ops = { + .readb = ts72xx_rtc_readb, + .writeb = ts72xx_rtc_writeb, +}; + +static struct platform_device ts72xx_rtc_device = { + .name = "rtc-m48t86", + .id = -1, + .dev = { + .platform_data = &ts72xx_rtc_ops, + }, + .num_resources = 0, +}; + static void __init ts72xx_init_machine(void) { ep93xx_init_devices(); if (board_is_ts7200()) physmap_configure(TS72XX_NOR_PHYS_BASE, 0x01000000, 1, NULL); + platform_device_register(&ts72xx_rtc_device); } MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") diff --git a/include/asm-arm/arch-ep93xx/ts72xx.h b/include/asm-arm/arch-ep93xx/ts72xx.h index 412215e77f44..a94f63ff0535 100644 --- a/include/asm-arm/arch-ep93xx/ts72xx.h +++ b/include/asm-arm/arch-ep93xx/ts72xx.h @@ -12,6 +12,8 @@ * febfc000 [67]0000000 4K NAND data register * febfb000 [67]0400000 4K NAND control register * febfa000 [67]0800000 4K NAND busy register + * febf9000 10800000 4K TS-5620 RTC index register + * febf8000 11700000 4K TS-5620 RTC data register */ #define TS72XX_MODEL_PHYS_BASE 0x22000000 @@ -58,6 +60,15 @@ #define TS72XX_NAND_BUSY_SIZE 0x00001000 +#define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000 +#define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000 +#define TS72XX_RTC_INDEX_SIZE 0x00001000 + +#define TS72XX_RTC_DATA_VIRT_BASE 0xfebf8000 +#define TS72XX_RTC_DATA_PHYS_BASE 0x11700000 +#define TS72XX_RTC_DATA_SIZE 0x00001000 + + #ifndef __ASSEMBLY__ #include -- cgit v1.2.3 From 999331af456bf6fc1520ea7b68b6a3dbb4af8ff6 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 2 Apr 2006 16:58:37 +0100 Subject: [ARM] 3444/1: i.MX: Scatter-gather DMA emulation for i.MX/MX1 Patch from Pavel Pisa This patch contains simplified set of changes to add scatter-gather emulation capability into MX1 DMA support. The result should be still usable for next combination of DMA transfers Statter-Gather/linear/2D/FIFO to linear/2D/FIFO and linear/2D/FIFO to Statter-Gather/2D/FIFO The patch corrects channel priority allocation to be compatible with MX1 hardware implementation. Previous code has not been adapted from its PXA original. Signed-off-by: Pavel Pisa Acked-by: Sascha Hauer Signed-off-by: Russell King --- arch/arm/mach-imx/dma.c | 511 ++++++++++++++++++++++++++++++++----- include/asm-arm/arch-imx/dma.h | 17 +- include/asm-arm/arch-imx/imx-dma.h | 90 +++++++ 3 files changed, 541 insertions(+), 77 deletions(-) create mode 100644 include/asm-arm/arch-imx/imx-dma.h diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c index 71a59e196166..4ca51dcf13ac 100644 --- a/arch/arm/mach-imx/dma.c +++ b/arch/arm/mach-imx/dma.c @@ -7,11 +7,18 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * 03/03/2004 Sascha Hauer + * 2004-03-03 Sascha Hauer * initial version heavily inspired by * linux/arch/arm/mach-pxa/dma.c + * + * 2005-04-17 Pavel Pisa + * Changed to support scatter gather DMA + * by taking Russell's code from RiscPC + * */ +#undef DEBUG + #include #include #include @@ -22,69 +29,368 @@ #include #include #include +#include + +struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS]; + +/* + * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation + * @dma_ch: i.MX DMA channel number + * @lastcount: number of bytes transferred during last transfer + * + * Functions prepares DMA controller for next sg data chunk transfer. + * The @lastcount argument informs function about number of bytes transferred + * during last block. Zero value can be used for @lastcount to setup DMA + * for the first chunk. + */ +static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + unsigned int nextcount; + unsigned int nextaddr; + + if (!imxdma->name) { + printk(KERN_CRIT "%s: called for not allocated channel %d\n", + __FUNCTION__, dma_ch); + return 0; + } + + imxdma->resbytes -= lastcount; + + if (!imxdma->sg) { + pr_debug("imxdma%d: no sg data\n", dma_ch); + return 0; + } + + imxdma->sgbc += lastcount; + if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) { + if ((imxdma->sgcount <= 1) || !imxdma->resbytes) { + pr_debug("imxdma%d: sg transfer limit reached\n", + dma_ch); + imxdma->sgcount=0; + imxdma->sg = NULL; + return 0; + } else { + imxdma->sgcount--; + imxdma->sg++; + imxdma->sgbc = 0; + } + } + nextcount = imxdma->sg->length - imxdma->sgbc; + nextaddr = imxdma->sg->dma_address + imxdma->sgbc; -static struct dma_channel { - char *name; - void (*irq_handler) (int, void *, struct pt_regs *); - void (*err_handler) (int, void *, struct pt_regs *); - void *data; -} dma_channels[11]; + if(imxdma->resbytes < nextcount) + nextcount = imxdma->resbytes; -/* set err_handler to NULL to have the standard info-only error handler */ + if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ) + DAR(dma_ch) = nextaddr; + else + SAR(dma_ch) = nextaddr; + + CNTR(dma_ch) = nextcount; + pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n", + dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch)); + + return nextcount; +} + +/* + * imx_dma_setup_sg_base - scatter-gather DMA emulation + * @dma_ch: i.MX DMA channel number + * @sg: pointer to the scatter-gather list/vector + * @sgcount: scatter-gather list hungs count + * + * Functions sets up i.MX DMA state for emulated scatter-gather transfer + * and sets up channel registers to be ready for the first chunk + */ +static int +imx_dma_setup_sg_base(imx_dmach_t dma_ch, + struct scatterlist *sg, unsigned int sgcount) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + + imxdma->sg = sg; + imxdma->sgcount = sgcount; + imxdma->sgbc = 0; + return imx_dma_sg_next(dma_ch, 0); +} + +/** + * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer + * @dma_ch: i.MX DMA channel number + * @dma_address: the DMA/physical memory address of the linear data block + * to transfer + * @dma_length: length of the data block in bytes + * @dev_addr: physical device port address + * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory + * or %DMA_MODE_WRITE from memory to the device + * + * The function setups DMA channel source and destination addresses for transfer + * specified by provided parameters. The scatter-gather emulation is disabled, + * because linear data block + * form the physical address range is transfered. + * Return value: if incorrect parameters are provided -%EINVAL. + * Zero indicates success. + */ int -imx_request_dma(char *name, imx_dma_prio prio, - void (*irq_handler) (int, void *, struct pt_regs *), - void (*err_handler) (int, void *, struct pt_regs *), void *data) +imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address, + unsigned int dma_length, unsigned int dev_addr, + dmamode_t dmamode) { - unsigned long flags; - int i, found = 0; + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - /* basic sanity checks */ - if (!name || !irq_handler) + imxdma->sg = NULL; + imxdma->sgcount = 0; + imxdma->dma_mode = dmamode; + imxdma->resbytes = dma_length; + + if (!dma_address) { + printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n", + dma_ch); return -EINVAL; + } - local_irq_save(flags); + if (!dma_length) { + printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n", + dma_ch); + return -EINVAL; + } - /* try grabbing a DMA channel with the requested priority */ - for (i = prio; i < prio + (prio == DMA_PRIO_LOW) ? 8 : 4; i++) { - if (!dma_channels[i].name) { - found = 1; - break; - } + if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { + pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n", + dma_ch, (unsigned int)dma_address, dma_length, + dev_addr); + SAR(dma_ch) = dev_addr; + DAR(dma_ch) = (unsigned int)dma_address; + } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { + pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n", + dma_ch, (unsigned int)dma_address, dma_length, + dev_addr); + SAR(dma_ch) = (unsigned int)dma_address; + DAR(dma_ch) = dev_addr; + } else { + printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n", + dma_ch); + return -EINVAL; } - if (!found) { - /* requested prio group is full, try hier priorities */ - for (i = prio - 1; i >= 0; i--) { - if (!dma_channels[i].name) { - found = 1; - break; - } - } + CNTR(dma_ch) = dma_length; + + return 0; +} + +/** + * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer + * @dma_ch: i.MX DMA channel number + * @sg: pointer to the scatter-gather list/vector + * @sgcount: scatter-gather list hungs count + * @dma_length: total length of the transfer request in bytes + * @dev_addr: physical device port address + * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory + * or %DMA_MODE_WRITE from memory to the device + * + * The function setups DMA channel state and registers to be ready for transfer + * specified by provided parameters. The scatter-gather emulation is set up + * according to the parameters. + * + * The full preparation of the transfer requires setup of more register + * by the caller before imx_dma_enable() can be called. + * + * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes + * + * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx + * + * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical + * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified + * + * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x + * + * The typical setup for %DMA_MODE_WRITE is specified by next options combination + * + * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x + * + * Be carefull there and do not mistakenly mix source and target device + * port sizes constants, they are really different: + * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32, + * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32 + * + * Return value: if incorrect parameters are provided -%EINVAL. + * Zero indicates success. + */ +int +imx_dma_setup_sg(imx_dmach_t dma_ch, + struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length, + unsigned int dev_addr, dmamode_t dmamode) +{ + int res; + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + + imxdma->sg = NULL; + imxdma->sgcount = 0; + imxdma->dma_mode = dmamode; + imxdma->resbytes = dma_length; + + if (!sg || !sgcount) { + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n", + dma_ch); + return -EINVAL; + } + + if (!sg->length) { + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n", + dma_ch); + return -EINVAL; } - if (found) { - DIMR &= ~(1 << i); - dma_channels[i].name = name; - dma_channels[i].irq_handler = irq_handler; - dma_channels[i].err_handler = err_handler; - dma_channels[i].data = data; + if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) { + pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n", + dma_ch, sg, sgcount, dma_length, dev_addr); + SAR(dma_ch) = dev_addr; + } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) { + pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n", + dma_ch, sg, sgcount, dma_length, dev_addr); + DAR(dma_ch) = dev_addr; } else { - printk(KERN_WARNING "No more available DMA channels for %s\n", - name); - i = -ENODEV; + printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n", + dma_ch); + return -EINVAL; + } + + res = imx_dma_setup_sg_base(dma_ch, sg, sgcount); + if (res <= 0) { + printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch); + return -EINVAL; + } + + return 0; +} + +/** + * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers + * @dma_ch: i.MX DMA channel number + * @irq_handler: the pointer to the function called if the transfer + * ends successfully + * @err_handler: the pointer to the function called if the premature + * end caused by error occurs + * @data: user specified value to be passed to the handlers + */ +int +imx_dma_setup_handlers(imx_dmach_t dma_ch, + void (*irq_handler) (int, void *, struct pt_regs *), + void (*err_handler) (int, void *, struct pt_regs *), + void *data) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + unsigned long flags; + + if (!imxdma->name) { + printk(KERN_CRIT "%s: called for not allocated channel %d\n", + __FUNCTION__, dma_ch); + return -ENODEV; + } + + local_irq_save(flags); + DISR = (1 << dma_ch); + imxdma->irq_handler = irq_handler; + imxdma->err_handler = err_handler; + imxdma->data = data; + local_irq_restore(flags); + return 0; +} + +/** + * imx_dma_enable - function to start i.MX DMA channel operation + * @dma_ch: i.MX DMA channel number + * + * The channel has to be allocated by driver through imx_dma_request() + * or imx_dma_request_by_prio() function. + * The transfer parameters has to be set to the channel registers through + * call of the imx_dma_setup_single() or imx_dma_setup_sg() function + * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to + * be set prior this function call by the channel user. + */ +void imx_dma_enable(imx_dmach_t dma_ch) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + unsigned long flags; + + pr_debug("imxdma%d: imx_dma_enable\n", dma_ch); + + if (!imxdma->name) { + printk(KERN_CRIT "%s: called for not allocated channel %d\n", + __FUNCTION__, dma_ch); + return; + } + + local_irq_save(flags); + DISR = (1 << dma_ch); + DIMR &= ~(1 << dma_ch); + CCR(dma_ch) |= CCR_CEN; + local_irq_restore(flags); +} + +/** + * imx_dma_disable - stop, finish i.MX DMA channel operatin + * @dma_ch: i.MX DMA channel number + */ +void imx_dma_disable(imx_dmach_t dma_ch) +{ + unsigned long flags; + + pr_debug("imxdma%d: imx_dma_disable\n", dma_ch); + + local_irq_save(flags); + DIMR |= (1 << dma_ch); + CCR(dma_ch) &= ~CCR_CEN; + DISR = (1 << dma_ch); + local_irq_restore(flags); +} + +/** + * imx_dma_request - request/allocate specified channel number + * @dma_ch: i.MX DMA channel number + * @name: the driver/caller own non-%NULL identification + */ +int imx_dma_request(imx_dmach_t dma_ch, const char *name) +{ + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; + unsigned long flags; + + /* basic sanity checks */ + if (!name) + return -EINVAL; + + if (dma_ch >= IMX_DMA_CHANNELS) { + printk(KERN_CRIT "%s: called for non-existed channel %d\n", + __FUNCTION__, dma_ch); + return -EINVAL; } + local_irq_save(flags); + if (imxdma->name) { + local_irq_restore(flags); + return -ENODEV; + } + + imxdma->name = name; + imxdma->irq_handler = NULL; + imxdma->err_handler = NULL; + imxdma->data = NULL; + imxdma->sg = NULL; local_irq_restore(flags); - return i; + return 0; } -void -imx_free_dma(int dma_ch) +/** + * imx_dma_free - release previously acquired channel + * @dma_ch: i.MX DMA channel number + */ +void imx_dma_free(imx_dmach_t dma_ch) { unsigned long flags; + struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch]; - if (!dma_channels[dma_ch].name) { + if (!imxdma->name) { printk(KERN_CRIT "%s: trying to free channel %d which is already freed\n", __FUNCTION__, dma_ch); @@ -92,27 +398,84 @@ imx_free_dma(int dma_ch) } local_irq_save(flags); - DIMR &= ~(1 << dma_ch); - dma_channels[dma_ch].name = NULL; + /* Disable interrupts */ + DIMR |= (1 << dma_ch); + CCR(dma_ch) &= ~CCR_CEN; + imxdma->name = NULL; local_irq_restore(flags); } -static irqreturn_t -dma_err_handler(int irq, void *dev_id, struct pt_regs *regs) +/** + * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority + * @dma_ch: i.MX DMA channel number + * @name: the driver/caller own non-%NULL identification + * @prio: one of the hardware distinguished priority level: + * %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW + * + * This function tries to find free channel in the specified priority group + * if the priority cannot be achieved it tries to look for free channel + * in the higher and then even lower priority groups. + * + * Return value: If there is no free channel to allocate, -%ENODEV is returned. + * Zero value indicates successful channel allocation. + */ +int +imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name, + imx_dma_prio prio) +{ + int i; + int best; + + switch (prio) { + case (DMA_PRIO_HIGH): + best = 8; + break; + case (DMA_PRIO_MEDIUM): + best = 4; + break; + case (DMA_PRIO_LOW): + default: + best = 0; + break; + } + + for (i = best; i < IMX_DMA_CHANNELS; i++) { + if (!imx_dma_request(i, name)) { + *pdma_ch = i; + return 0; + } + } + + for (i = best - 1; i >= 0; i--) { + if (!imx_dma_request(i, name)) { + *pdma_ch = i; + return 0; + } + } + + printk(KERN_ERR "%s: no free DMA channel found\n", __FUNCTION__); + + return -ENODEV; +} + +static irqreturn_t dma_err_handler(int irq, void *dev_id, struct pt_regs *regs) { int i, disr = DISR; - struct dma_channel *channel; + struct imx_dma_channel *channel; unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR; DISR = disr; - for (i = 0; i < 11; i++) { - channel = &dma_channels[i]; + for (i = 0; i < IMX_DMA_CHANNELS; i++) { + channel = &imx_dma_channels[i]; - if ( (err_mask & 1<name && channel->err_handler) { + if ((err_mask & 1 << i) && channel->name + && channel->err_handler) { channel->err_handler(i, channel->data, regs); continue; } + imx_dma_channels[i].sg = NULL; + if (DBTOSR & (1 << i)) { printk(KERN_WARNING "Burst timeout on channel %d (%s)\n", @@ -141,17 +504,27 @@ dma_err_handler(int irq, void *dev_id, struct pt_regs *regs) return IRQ_HANDLED; } -static irqreturn_t -dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) +static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) { int i, disr = DISR; + pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n", + disr); + DISR = disr; - for (i = 0; i < 11; i++) { + for (i = 0; i < IMX_DMA_CHANNELS; i++) { if (disr & (1 << i)) { - struct dma_channel *channel = &dma_channels[i]; - if (channel->name && channel->irq_handler) { - channel->irq_handler(i, channel->data, regs); + struct imx_dma_channel *channel = &imx_dma_channels[i]; + if (channel->name) { + if (imx_dma_sg_next(i, CNTR(i))) { + CCR(i) &= ~CCR_CEN; + mb(); + CCR(i) |= CCR_CEN; + } else { + if (channel->irq_handler) + channel->irq_handler(i, + channel->data, regs); + } } else { /* * IRQ for an unregistered DMA channel: @@ -165,10 +538,10 @@ dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs) return IRQ_HANDLED; } -static int __init -imx_dma_init(void) +static int __init imx_dma_init(void) { int ret; + int i; /* reset DMA module */ DCR = DCR_DRST; @@ -189,15 +562,27 @@ imx_dma_init(void) DCR = DCR_DEN; /* clear all interrupts */ - DISR = 0x3ff; + DISR = (1 << IMX_DMA_CHANNELS) - 1; /* enable interrupts */ - DIMR = 0; + DIMR = (1 << IMX_DMA_CHANNELS) - 1; + + for (i = 0; i < IMX_DMA_CHANNELS; i++) { + imx_dma_channels[i].sg = NULL; + imx_dma_channels[i].dma_num = i; + } return ret; } arch_initcall(imx_dma_init); -EXPORT_SYMBOL(imx_request_dma); -EXPORT_SYMBOL(imx_free_dma); +EXPORT_SYMBOL(imx_dma_setup_single); +EXPORT_SYMBOL(imx_dma_setup_sg); +EXPORT_SYMBOL(imx_dma_setup_handlers); +EXPORT_SYMBOL(imx_dma_enable); +EXPORT_SYMBOL(imx_dma_disable); +EXPORT_SYMBOL(imx_dma_request); +EXPORT_SYMBOL(imx_dma_free); +EXPORT_SYMBOL(imx_dma_request_by_prio); +EXPORT_SYMBOL(imx_dma_channels); diff --git a/include/asm-arm/arch-imx/dma.h b/include/asm-arm/arch-imx/dma.h index b45fa367d71e..621ff2c730f2 100644 --- a/include/asm-arm/arch-imx/dma.h +++ b/include/asm-arm/arch-imx/dma.h @@ -17,27 +17,16 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + #ifndef __ASM_ARCH_DMA_H #define __ASM_ARCH_DMA_H -/* - * DMA registration - */ - typedef enum { DMA_PRIO_HIGH = 0, - DMA_PRIO_MEDIUM = 3, - DMA_PRIO_LOW = 6 + DMA_PRIO_MEDIUM = 1, + DMA_PRIO_LOW = 2 } imx_dma_prio; -int imx_request_dma(char *name, imx_dma_prio prio, - void (*irq_handler) (int, void *, struct pt_regs *), - void (*err_handler) (int, void *, struct pt_regs *), - void *data); - -void imx_free_dma(int dma_ch); - - #define DMA_REQ_UART3_T 2 #define DMA_REQ_UART3_R 3 #define DMA_REQ_SSI2_T 4 diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h new file mode 100644 index 000000000000..f2063c1d610d --- /dev/null +++ b/include/asm-arm/arch-imx/imx-dma.h @@ -0,0 +1,90 @@ +/* + * linux/include/asm-arm/imxads/dma.h + * + * Copyright (C) 1997,1998 Russell King + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330