From 26571eb692f47dd0a99470565da64f95a7b07d8b Mon Sep 17 00:00:00 2001 From: Michal Wajdeczko Date: Tue, 2 Jul 2024 20:37:02 +0200 Subject: drm/xe: Fix register definition order in xe_regs.h [ Upstream commit 9dae9751c7b0086963f5cbb82424b5e4cf58f123 ] Swap XEHP_CLOCK_GATE_DIS(0x101014) with GU_DEBUG(x101018). Signed-off-by: Michal Wajdeczko Reviewed-by: Matt Roper Reviewed-by: Himal Prasad Ghimiray Link: https://patchwork.freedesktop.org/patch/msgid/20240702183704.1022-2-michal.wajdeczko@intel.com Stable-dep-of: 993ca0eccec6 ("drm/xe: Add mmio read before GGTT invalidate") Signed-off-by: Sasha Levin --- drivers/gpu/drm/xe/regs/xe_regs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h index 23e33ec84902..23ecba38ed41 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -24,12 +24,12 @@ #define LMEM_INIT REG_BIT(7) #define DRIVERFLR REG_BIT(31) -#define GU_DEBUG XE_REG(0x101018) -#define DRIVERFLR_STATUS REG_BIT(31) - #define XEHP_CLOCK_GATE_DIS XE_REG(0x101014) #define SGSI_SIDECLK_DIS REG_BIT(17) +#define GU_DEBUG XE_REG(0x101018) +#define DRIVERFLR_STATUS REG_BIT(31) + #define XEHP_MTCFG_ADDR XE_REG(0x101800) #define TILE_COUNT REG_GENMASK(15, 8) -- cgit v1.2.3