From 47b06fc2d97a0d98d6053357561f2953d6547d25 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 13 Sep 2014 00:34:31 +0200 Subject: ARM: rockchip: add a cpufreq-cpu0 device Rockchip SoCs can sucessfully use the generic cpufreq-cpu0 driver to do frequency scaling. Therefore add a platform device in the machine init code. Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/rockchip.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index 8ab9e0e7ff04..eea1f06366e6 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -24,6 +24,12 @@ #include #include "core.h" +static void __init rockchip_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + platform_device_register_simple("cpufreq-cpu0", 0, NULL, 0); +} + static const char * const rockchip_board_dt_compat[] = { "rockchip,rk2928", "rockchip,rk3066a", @@ -37,4 +43,5 @@ DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)") .l2c_aux_val = 0, .l2c_aux_mask = ~0, .dt_compat = rockchip_board_dt_compat, + .init_machine = rockchip_dt_init, MACHINE_END -- cgit v1.2.3 From 3eb79a5a9d46b32f63f6b9cd86f9b2bba43e127a Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Tue, 30 Sep 2014 10:33:27 +0200 Subject: ARM: rockchip: honor renaming of cpufreq-cpu0 to cpufreq-dt cpufreq-cpu0 got renamed to a more generic name cpufreq-dt, so adapt the created platform-device to this. Reported-by: Viresh Kumar Signed-off-by: Heiko Stuebner --- arch/arm/mach-rockchip/rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c index eea1f06366e6..d226b71d21d5 100644 --- a/arch/arm/mach-rockchip/rockchip.c +++ b/arch/arm/mach-rockchip/rockchip.c @@ -27,7 +27,7 @@ static void __init rockchip_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); - platform_device_register_simple("cpufreq-cpu0", 0, NULL, 0); + platform_device_register_simple("cpufreq-dt", 0, NULL, 0); } static const char * const rockchip_board_dt_compat[] = { -- cgit v1.2.3 From af7e9069543aabd415d7c543f3f89b143ac1a932 Mon Sep 17 00:00:00 2001 From: Jacob Pan Date: Mon, 6 Oct 2014 21:17:14 -0700 Subject: mfd: axp20x: Extend axp20x to support axp288 pmic X-Powers AXP288 is a customized PMIC for Intel Baytrail-CR platforms. Similar to AXP202/209, AXP288 comes with USB charger, more LDO and BUCK channels, and AD converters. It also provides extended status and interrupt reporting capabilities than the devices currently supported in axp20x.c. In addition to feature extension, this patch also adds ACPI binding for enumeration. This consolidated driver should support more X-Powers' PMICs in both device tree and ACPI enumerated platforms. Signed-off-by: Jacob Pan Reviewed-by: Maxime Ripard Reviewed-by: Jonathan Cameron Signed-off-by: Lee Jones --- drivers/mfd/Kconfig | 3 +- drivers/mfd/axp20x.c | 361 ++++++++++++++++++++++++++++++++++++++------- include/linux/mfd/axp20x.h | 59 ++++++++ 3 files changed, 367 insertions(+), 56 deletions(-) diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index de5abf244746..c183edb45b52 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -74,7 +74,8 @@ config MFD_AXP20X select REGMAP_IRQ depends on I2C=y help - If you say Y here you get support for the X-Powers AXP202 and AXP209. + If you say Y here you get support for the X-Powers AXP202, AXP209 and + AXP288 power management IC (PMIC). This driver include only the core APIs. You have to select individual components like regulators or the PEK (Power Enable Key) under the corresponding menus. diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index dee653989e3a..b2fb7f492c86 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -1,9 +1,9 @@ /* - * axp20x.c - MFD core driver for the X-Powers AXP202 and AXP209 + * axp20x.c - MFD core driver for the X-Powers' Power Management ICs * - * AXP20x comprises an adaptive USB-Compatible PWM charger, 2 BUCK DC-DC - * converters, 5 LDOs, multiple 12-bit ADCs of voltage, current and temperature - * as well as 4 configurable GPIOs. + * AXP20x typically comprises an adaptive USB-Compatible PWM charger, BUCK DC-DC + * converters, LDOs, multiple 12-bit ADCs of voltage, current and temperature + * as well as configurable GPIOs. * * Author: Carlo Caione * @@ -25,9 +25,16 @@ #include #include #include +#include #define AXP20X_OFF 0x80 +static const char const *axp20x_model_names[] = { + "AXP202", + "AXP209", + "AXP288", +}; + static const struct regmap_range axp20x_writeable_ranges[] = { regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), regmap_reg_range(AXP20X_DCDC_MODE, AXP20X_FG_RES), @@ -47,6 +54,25 @@ static const struct regmap_access_table axp20x_volatile_table = { .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges), }; +static const struct regmap_range axp288_writeable_ranges[] = { + regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ6_STATE), + regmap_reg_range(AXP20X_DCDC_MODE, AXP288_FG_TUNE5), +}; + +static const struct regmap_range axp288_volatile_ranges[] = { + regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IPSOUT_V_HIGH_L), +}; + +static const struct regmap_access_table axp288_writeable_table = { + .yes_ranges = axp288_writeable_ranges, + .n_yes_ranges = ARRAY_SIZE(axp288_writeable_ranges), +}; + +static const struct regmap_access_table axp288_volatile_table = { + .yes_ranges = axp288_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(axp288_volatile_ranges), +}; + static struct resource axp20x_pek_resources[] = { { .name = "PEK_DBR", @@ -61,6 +87,39 @@ static struct resource axp20x_pek_resources[] = { }, }; +static struct resource axp288_battery_resources[] = { + { + .start = AXP288_IRQ_QWBTU, + .end = AXP288_IRQ_QWBTU, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_WBTU, + .end = AXP288_IRQ_WBTU, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_QWBTO, + .end = AXP288_IRQ_QWBTO, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_WBTO, + .end = AXP288_IRQ_WBTO, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_WL2, + .end = AXP288_IRQ_WL2, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_WL1, + .end = AXP288_IRQ_WL1, + .flags = IORESOURCE_IRQ, + }, +}; + static const struct regmap_config axp20x_regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -70,47 +129,96 @@ static const struct regmap_config axp20x_regmap_config = { .cache_type = REGCACHE_RBTREE, }; -#define AXP20X_IRQ(_irq, _off, _mask) \ - [AXP20X_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) } +static const struct regmap_config axp288_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .wr_table = &axp288_writeable_table, + .volatile_table = &axp288_volatile_table, + .max_register = AXP288_FG_TUNE5, + .cache_type = REGCACHE_RBTREE, +}; + +#define INIT_REGMAP_IRQ(_variant, _irq, _off, _mask) \ + [_variant##_IRQ_##_irq] = { .reg_offset = (_off), .mask = BIT(_mask) } static const struct regmap_irq axp20x_regmap_irqs[] = { - AXP20X_IRQ(ACIN_OVER_V, 0, 7), - AXP20X_IRQ(ACIN_PLUGIN, 0, 6), - AXP20X_IRQ(ACIN_REMOVAL, 0, 5), - AXP20X_IRQ(VBUS_OVER_V, 0, 4), - AXP20X_IRQ(VBUS_PLUGIN, 0, 3), - AXP20X_IRQ(VBUS_REMOVAL, 0, 2), - AXP20X_IRQ(VBUS_V_LOW, 0, 1), - AXP20X_IRQ(BATT_PLUGIN, 1, 7), - AXP20X_IRQ(BATT_REMOVAL, 1, 6), - AXP20X_IRQ(BATT_ENT_ACT_MODE, 1, 5), - AXP20X_IRQ(BATT_EXIT_ACT_MODE, 1, 4), - AXP20X_IRQ(CHARG, 1, 3), - AXP20X_IRQ(CHARG_DONE, 1, 2), - AXP20X_IRQ(BATT_TEMP_HIGH, 1, 1), - AXP20X_IRQ(BATT_TEMP_LOW, 1, 0), - AXP20X_IRQ(DIE_TEMP_HIGH, 2, 7), - AXP20X_IRQ(CHARG_I_LOW, 2, 6), - AXP20X_IRQ(DCDC1_V_LONG, 2, 5), - AXP20X_IRQ(DCDC2_V_LONG, 2, 4), - AXP20X_IRQ(DCDC3_V_LONG, 2, 3), - AXP20X_IRQ(PEK_SHORT, 2, 1), - AXP20X_IRQ(PEK_LONG, 2, 0), - AXP20X_IRQ(N_OE_PWR_ON, 3, 7), - AXP20X_IRQ(N_OE_PWR_OFF, 3, 6), - AXP20X_IRQ(VBUS_VALID, 3, 5), - AXP20X_IRQ(VBUS_NOT_VALID, 3, 4), - AXP20X_IRQ(VBUS_SESS_VALID, 3, 3), - AXP20X_IRQ(VBUS_SESS_END, 3, 2), - AXP20X_IRQ(LOW_PWR_LVL1, 3, 1), - AXP20X_IRQ(LOW_PWR_LVL2, 3, 0), - AXP20X_IRQ(TIMER, 4, 7), - AXP20X_IRQ(PEK_RIS_EDGE, 4, 6), - AXP20X_IRQ(PEK_FAL_EDGE, 4, 5), - AXP20X_IRQ(GPIO3_INPUT, 4, 3), - AXP20X_IRQ(GPIO2_INPUT, 4, 2), - AXP20X_IRQ(GPIO1_INPUT, 4, 1), - AXP20X_IRQ(GPIO0_INPUT, 4, 0), + INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7), + INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6), + INIT_REGMAP_IRQ(AXP20X, ACIN_REMOVAL, 0, 5), + INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4), + INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3), + INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2), + INIT_REGMAP_IRQ(AXP20X, VBUS_V_LOW, 0, 1), + INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7), + INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6), + INIT_REGMAP_IRQ(AXP20X, BATT_ENT_ACT_MODE, 1, 5), + INIT_REGMAP_IRQ(AXP20X, BATT_EXIT_ACT_MODE, 1, 4), + INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3), + INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2), + INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_HIGH, 1, 1), + INIT_REGMAP_IRQ(AXP20X, BATT_TEMP_LOW, 1, 0), + INIT_REGMAP_IRQ(AXP20X, DIE_TEMP_HIGH, 2, 7), + INIT_REGMAP_IRQ(AXP20X, CHARG_I_LOW, 2, 6), + INIT_REGMAP_IRQ(AXP20X, DCDC1_V_LONG, 2, 5), + INIT_REGMAP_IRQ(AXP20X, DCDC2_V_LONG, 2, 4), + INIT_REGMAP_IRQ(AXP20X, DCDC3_V_LONG, 2, 3), + INIT_REGMAP_IRQ(AXP20X, PEK_SHORT, 2, 1), + INIT_REGMAP_IRQ(AXP20X, PEK_LONG, 2, 0), + INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_ON, 3, 7), + INIT_REGMAP_IRQ(AXP20X, N_OE_PWR_OFF, 3, 6), + INIT_REGMAP_IRQ(AXP20X, VBUS_VALID, 3, 5), + INIT_REGMAP_IRQ(AXP20X, VBUS_NOT_VALID, 3, 4), + INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_VALID, 3, 3), + INIT_REGMAP_IRQ(AXP20X, VBUS_SESS_END, 3, 2), + INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL1, 3, 1), + INIT_REGMAP_IRQ(AXP20X, LOW_PWR_LVL2, 3, 0), + INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7), + INIT_REGMAP_IRQ(AXP20X, PEK_RIS_EDGE, 4, 6), + INIT_REGMAP_IRQ(AXP20X, PEK_FAL_EDGE, 4, 5), + INIT_REGMAP_IRQ(AXP20X, GPIO3_INPUT, 4, 3), + INIT_REGMAP_IRQ(AXP20X, GPIO2_INPUT, 4, 2), + INIT_REGMAP_IRQ(AXP20X, GPIO1_INPUT, 4, 1), + INIT_REGMAP_IRQ(AXP20X, GPIO0_INPUT, 4, 0), +}; + +/* some IRQs are compatible with axp20x models */ +static const struct regmap_irq axp288_regmap_irqs[] = { + INIT_REGMAP_IRQ(AXP20X, VBUS_REMOVAL, 0, 2), + INIT_REGMAP_IRQ(AXP20X, VBUS_PLUGIN, 0, 3), + INIT_REGMAP_IRQ(AXP20X, VBUS_OVER_V, 0, 4), + + INIT_REGMAP_IRQ(AXP20X, CHARG_DONE, 1, 2), + INIT_REGMAP_IRQ(AXP20X, CHARG, 1, 3), + INIT_REGMAP_IRQ(AXP288, SAFE_QUIT, 1, 4), + INIT_REGMAP_IRQ(AXP288, SAFE_ENTER, 1, 5), + INIT_REGMAP_IRQ(AXP20X, BATT_REMOVAL, 1, 6), + INIT_REGMAP_IRQ(AXP20X, BATT_PLUGIN, 1, 7), + + INIT_REGMAP_IRQ(AXP288, QWBTU, 2, 0), + INIT_REGMAP_IRQ(AXP288, WBTU, 2, 1), + INIT_REGMAP_IRQ(AXP288, QWBTO, 2, 2), + INIT_REGMAP_IRQ(AXP288, WBTU, 2, 3), + INIT_REGMAP_IRQ(AXP288, QCBTU, 2, 4), + INIT_REGMAP_IRQ(AXP288, CBTU, 2, 5), + INIT_REGMAP_IRQ(AXP288, QCBTO, 2, 6), + INIT_REGMAP_IRQ(AXP288, CBTO, 2, 7), + + INIT_REGMAP_IRQ(AXP288, WL2, 3, 0), + INIT_REGMAP_IRQ(AXP288, WL1, 3, 1), + INIT_REGMAP_IRQ(AXP288, GPADC, 3, 2), + INIT_REGMAP_IRQ(AXP288, OT, 3, 7), + + INIT_REGMAP_IRQ(AXP288, GPIO0, 4, 0), + INIT_REGMAP_IRQ(AXP288, GPIO1, 4, 1), + INIT_REGMAP_IRQ(AXP288, POKO, 4, 2), + INIT_REGMAP_IRQ(AXP288, POKL, 4, 3), + INIT_REGMAP_IRQ(AXP288, POKS, 4, 4), + INIT_REGMAP_IRQ(AXP288, POKN, 4, 5), + INIT_REGMAP_IRQ(AXP288, POKP, 4, 6), + INIT_REGMAP_IRQ(AXP20X, TIMER, 4, 7), + + INIT_REGMAP_IRQ(AXP288, MV_CHNG, 5, 0), + INIT_REGMAP_IRQ(AXP288, BC_USB_CHNG, 5, 1), }; static const struct of_device_id axp20x_of_match[] = { @@ -128,16 +236,39 @@ static const struct i2c_device_id axp20x_i2c_id[] = { }; MODULE_DEVICE_TABLE(i2c, axp20x_i2c_id); +static struct acpi_device_id axp20x_acpi_match[] = { + { + .id = "INT33F4", + .driver_data = AXP288_ID, + }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, axp20x_acpi_match); + static const struct regmap_irq_chip axp20x_regmap_irq_chip = { .name = "axp20x_irq_chip", .status_base = AXP20X_IRQ1_STATE, .ack_base = AXP20X_IRQ1_STATE, .mask_base = AXP20X_IRQ1_EN, - .num_regs = 5, + .mask_invert = true, + .init_ack_masked = true, .irqs = axp20x_regmap_irqs, .num_irqs = ARRAY_SIZE(axp20x_regmap_irqs), + .num_regs = 5, + +}; + +static const struct regmap_irq_chip axp288_regmap_irq_chip = { + .name = "axp288_irq_chip", + .status_base = AXP20X_IRQ1_STATE, + .ack_base = AXP20X_IRQ1_STATE, + .mask_base = AXP20X_IRQ1_EN, .mask_invert = true, .init_ack_masked = true, + .irqs = axp288_regmap_irqs, + .num_irqs = ARRAY_SIZE(axp288_regmap_irqs), + .num_regs = 6, + }; static const char * const axp20x_supplies[] = { @@ -161,36 +292,155 @@ static struct mfd_cell axp20x_cells[] = { }, }; +static struct resource axp288_adc_resources[] = { + { + .name = "GPADC", + .start = AXP288_IRQ_GPADC, + .end = AXP288_IRQ_GPADC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource axp288_charger_resources[] = { + { + .start = AXP288_IRQ_OV, + .end = AXP288_IRQ_OV, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_DONE, + .end = AXP288_IRQ_DONE, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_CHARGING, + .end = AXP288_IRQ_CHARGING, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_SAFE_QUIT, + .end = AXP288_IRQ_SAFE_QUIT, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_SAFE_ENTER, + .end = AXP288_IRQ_SAFE_ENTER, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_QCBTU, + .end = AXP288_IRQ_QCBTU, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_CBTU, + .end = AXP288_IRQ_CBTU, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_QCBTO, + .end = AXP288_IRQ_QCBTO, + .flags = IORESOURCE_IRQ, + }, + { + .start = AXP288_IRQ_CBTO, + .end = AXP288_IRQ_CBTO, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct mfd_cell axp288_cells[] = { + { + .name = "axp288_adc", + .num_resources = ARRAY_SIZE(axp288_adc_resources), + .resources = axp288_adc_resources, + }, + { + .name = "axp288_charger", + .num_resources = ARRAY_SIZE(axp288_charger_resources), + .resources = axp288_charger_resources, + }, + { + .name = "axp288_battery", + .num_resources = ARRAY_SIZE(axp288_battery_resources), + .resources = axp288_battery_resources, + }, +}; + static struct axp20x_dev *axp20x_pm_power_off; static void axp20x_power_off(void) { + if (axp20x_pm_power_off->variant == AXP288_ID) + return; + regmap_write(axp20x_pm_power_off->regmap, AXP20X_OFF_CTRL, AXP20X_OFF); } +static int axp20x_match_device(struct axp20x_dev *axp20x, struct device *dev) +{ + const struct acpi_device_id *acpi_id; + const struct of_device_id *of_id; + + if (dev->of_node) { + of_id = of_match_device(axp20x_of_match, dev); + if (!of_id) { + dev_err(dev, "Unable to match OF ID\n"); + return -ENODEV; + } + axp20x->variant = (long) of_id->data; + } else { + acpi_id = acpi_match_device(dev->driver->acpi_match_table, dev); + if (!acpi_id || !acpi_id->driver_data) { + dev_err(dev, "Unable to match ACPI ID and data\n"); + return -ENODEV; + } + axp20x->variant = (long) acpi_id->driver_data; + } + + switch (axp20x->variant) { + case AXP202_ID: + case AXP209_ID: + axp20x->nr_cells = ARRAY_SIZE(axp20x_cells); + axp20x->cells = axp20x_cells; + axp20x->regmap_cfg = &axp20x_regmap_config; + axp20x->regmap_irq_chip = &axp20x_regmap_irq_chip; + break; + case AXP288_ID: + axp20x->cells = axp288_cells; + axp20x->nr_cells = ARRAY_SIZE(axp288_cells); + axp20x->regmap_cfg = &axp288_regmap_config; + axp20x->regmap_irq_chip = &axp288_regmap_irq_chip; + break; + default: + dev_err(dev, "unsupported AXP20X ID %lu\n", axp20x->variant); + return -EINVAL; + } + dev_info(dev, "AXP20x variant %s found\n", + axp20x_model_names[axp20x->variant]); + + return 0; +} + static int axp20x_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { struct axp20x_dev *axp20x; - const struct of_device_id *of_id; int ret; axp20x = devm_kzalloc(&i2c->dev, sizeof(*axp20x), GFP_KERNEL); if (!axp20x) return -ENOMEM; - of_id = of_match_device(axp20x_of_match, &i2c->dev); - if (!of_id) { - dev_err(&i2c->dev, "Unable to setup AXP20X data\n"); - return -ENODEV; - } - axp20x->variant = (long) of_id->data; + ret = axp20x_match_device(axp20x, &i2c->dev); + if (ret) + return ret; axp20x->i2c_client = i2c; axp20x->dev = &i2c->dev; dev_set_drvdata(axp20x->dev, axp20x); - axp20x->regmap = devm_regmap_init_i2c(i2c, &axp20x_regmap_config); + axp20x->regmap = devm_regmap_init_i2c(i2c, axp20x->regmap_cfg); if (IS_ERR(axp20x->regmap)) { ret = PTR_ERR(axp20x->regmap); dev_err(&i2c->dev, "regmap init failed: %d\n", ret); @@ -199,15 +449,15 @@ static int axp20x_i2c_probe(struct i2c_client *i2c, ret = regmap_add_irq_chip(axp20x->regmap, i2c->irq, IRQF_ONESHOT | IRQF_SHARED, -1, - &axp20x_regmap_irq_chip, + axp20x->regmap_irq_chip, &axp20x->regmap_irqc); if (ret) { dev_err(&i2c->dev, "failed to add irq chip: %d\n", ret); return ret; } - ret = mfd_add_devices(axp20x->dev, -1, axp20x_cells, - ARRAY_SIZE(axp20x_cells), NULL, 0, NULL); + ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells, + axp20x->nr_cells, NULL, 0, NULL); if (ret) { dev_err(&i2c->dev, "failed to add MFD devices: %d\n", ret); @@ -245,6 +495,7 @@ static struct i2c_driver axp20x_i2c_driver = { .name = "axp20x", .owner = THIS_MODULE, .of_match_table = of_match_ptr(axp20x_of_match), + .acpi_match_table = ACPI_PTR(axp20x_acpi_match), }, .probe = axp20x_i2c_probe, .remove = axp20x_i2c_remove, diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index d0e31a2287ac..81589d176ae8 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -14,6 +14,8 @@ enum { AXP202_ID = 0, AXP209_ID, + AXP288_ID, + NR_AXP20X_VARIANTS, }; #define AXP20X_DATACACHE(m) (0x04 + (m)) @@ -49,11 +51,13 @@ enum { #define AXP20X_IRQ3_EN 0x42 #define AXP20X_IRQ4_EN 0x43 #define AXP20X_IRQ5_EN 0x44 +#define AXP20X_IRQ6_EN 0x45 #define AXP20X_IRQ1_STATE 0x48 #define AXP20X_IRQ2_STATE 0x49 #define AXP20X_IRQ3_STATE 0x4a #define AXP20X_IRQ4_STATE 0x4b #define AXP20X_IRQ5_STATE 0x4c +#define AXP20X_IRQ6_STATE 0x4d /* ADC */ #define AXP20X_ACIN_V_ADC_H 0x56 @@ -116,6 +120,15 @@ enum { #define AXP20X_CC_CTRL 0xb8 #define AXP20X_FG_RES 0xb9 +/* AXP288 specific registers */ +#define AXP288_PMIC_ADC_H 0x56 +#define AXP288_PMIC_ADC_L 0x57 +#define AXP288_ADC_TS_PIN_CTRL 0x84 + +#define AXP288_PMIC_ADC_EN 0x84 +#define AXP288_FG_TUNE5 0xed + + /* Regulators IDs */ enum { AXP20X_LDO1 = 0, @@ -169,12 +182,58 @@ enum { AXP20X_IRQ_GPIO0_INPUT, }; +enum axp288_irqs { + AXP288_IRQ_VBUS_FALL = 2, + AXP288_IRQ_VBUS_RISE, + AXP288_IRQ_OV, + AXP288_IRQ_FALLING_ALT, + AXP288_IRQ_RISING_ALT, + AXP288_IRQ_OV_ALT, + AXP288_IRQ_DONE = 10, + AXP288_IRQ_CHARGING, + AXP288_IRQ_SAFE_QUIT, + AXP288_IRQ_SAFE_ENTER, + AXP288_IRQ_ABSENT, + AXP288_IRQ_APPEND, + AXP288_IRQ_QWBTU, + AXP288_IRQ_WBTU, + AXP288_IRQ_QWBTO, + AXP288_IRQ_WBTO, + AXP288_IRQ_QCBTU, + AXP288_IRQ_CBTU, + AXP288_IRQ_QCBTO, + AXP288_IRQ_CBTO, + AXP288_IRQ_WL2, + AXP288_IRQ_WL1, + AXP288_IRQ_GPADC, + AXP288_IRQ_OT = 31, + AXP288_IRQ_GPIO0, + AXP288_IRQ_GPIO1, + AXP288_IRQ_POKO, + AXP288_IRQ_POKL, + AXP288_IRQ_POKS, + AXP288_IRQ_POKN, + AXP288_IRQ_POKP, + AXP288_IRQ_TIMER, + AXP288_IRQ_MV_CHNG, + AXP288_IRQ_BC_USB_CHNG, +}; + +#define AXP288_TS_ADC_H 0x58 +#define AXP288_TS_ADC_L 0x59 +#define AXP288_GP_ADC_H 0x5a +#define AXP288_GP_ADC_L 0x5b + struct axp20x_dev { struct device *dev; struct i2c_client *i2c_client; struct regmap *regmap; struct regmap_irq_chip_data *regmap_irqc; long variant; + int nr_cells; + struct mfd_cell *cells; + const struct regmap_config *regmap_cfg; + const struct regmap_irq_chip *regmap_irq_chip; }; #endif /* __LINUX_MFD_AXP20X_H */ -- cgit v1.2.3 From de89bd7f215b44ef18f56b0ddb579b44a1180958 Mon Sep 17 00:00:00 2001 From: Jacob Pan Date: Mon, 6 Oct 2014 21:17:15 -0700 Subject: iio: adc: Add support for axp288 adc Platform driver for X-Powers AXP288 ADC, which is a sub-device of the customized AXP288 PMIC for Intel Baytrail-CR platforms. GPADC device enumerates as one of the MFD cell devices. It uses IIO infrastructure to communicate with userspace and consumer drivers. Usages of ADC channels include battery charging and thermal sensors. Based on initial work by: Ramakrishna Pallala Acked-by: Jonathan Cameron Signed-off-by: Jacob Pan Signed-off-by: Lee Jones --- drivers/iio/adc/Kconfig | 8 ++ drivers/iio/adc/Makefile | 1 + drivers/iio/adc/axp288_adc.c | 254 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 263 insertions(+) create mode 100644 drivers/iio/adc/axp288_adc.c diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 11b048a59fde..db2681b4f24b 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -127,6 +127,14 @@ config AT91_ADC help Say yes here to build support for Atmel AT91 ADC. +config AXP288_ADC + tristate "X-Powers AXP288 ADC driver" + depends on MFD_AXP20X + help + Say yes here to have support for X-Powers power management IC (PMIC) ADC + device. Depending on platform configuration, this general purpose ADC can + be used for sampling sensors such as thermal resistors. + config EXYNOS_ADC tristate "Exynos ADC driver support" depends on ARCH_EXYNOS || (OF && COMPILE_TEST) diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index ad81b512aa3d..19640f9dc470 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_AD7793) += ad7793.o obj-$(CONFIG_AD7887) += ad7887.o obj-$(CONFIG_AD799X) += ad799x.o obj-$(CONFIG_AT91_ADC) += at91_adc.o +obj-$(CONFIG_AXP288_ADC) += axp288_adc.o obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o obj-$(CONFIG_MAX1027) += max1027.o diff --git a/drivers/iio/adc/axp288_adc.c b/drivers/iio/adc/axp288_adc.c new file mode 100644 index 000000000000..480028618a84 --- /dev/null +++ b/drivers/iio/adc/axp288_adc.c @@ -0,0 +1,254 @@ +/* + * axp288_adc.c - X-Powers AXP288 PMIC ADC Driver + * + * Copyright (C) 2014 Intel Corporation + * + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define AXP288_ADC_EN_MASK 0xF1 +#define AXP288_ADC_TS_PIN_GPADC 0xF2 +#define AXP288_ADC_TS_PIN_ON 0xF3 + +enum axp288_adc_id { + AXP288_ADC_TS, + AXP288_ADC_PMIC, + AXP288_ADC_GP, + AXP288_ADC_BATT_CHRG_I, + AXP288_ADC_BATT_DISCHRG_I, + AXP288_ADC_BATT_V, + AXP288_ADC_NR_CHAN, +}; + +struct axp288_adc_info { + int irq; + struct regmap *regmap; +}; + +static const struct iio_chan_spec const axp288_adc_channels[] = { + { + .indexed = 1, + .type = IIO_TEMP, + .channel = 0, + .address = AXP288_TS_ADC_H, + .datasheet_name = "TS_PIN", + }, { + .indexed = 1, + .type = IIO_TEMP, + .channel = 1, + .address = AXP288_PMIC_ADC_H, + .datasheet_name = "PMIC_TEMP", + }, { + .indexed = 1, + .type = IIO_TEMP, + .channel = 2, + .address = AXP288_GP_ADC_H, + .datasheet_name = "GPADC", + }, { + .indexed = 1, + .type = IIO_CURRENT, + .channel = 3, + .address = AXP20X_BATT_CHRG_I_H, + .datasheet_name = "BATT_CHG_I", + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), + }, { + .indexed = 1, + .type = IIO_CURRENT, + .channel = 4, + .address = AXP20X_BATT_DISCHRG_I_H, + .datasheet_name = "BATT_DISCHRG_I", + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), + }, { + .indexed = 1, + .type = IIO_VOLTAGE, + .channel = 5, + .address = AXP20X_BATT_V_H, + .datasheet_name = "BATT_V", + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), + }, +}; + +#define AXP288_ADC_MAP(_adc_channel_label, _consumer_dev_name, \ + _consumer_channel) \ + { \ + .adc_channel_label = _adc_channel_label, \ + .consumer_dev_name = _consumer_dev_name, \ + .consumer_channel = _consumer_channel, \ + } + +/* for consumer drivers */ +static struct iio_map axp288_adc_default_maps[] = { + AXP288_ADC_MAP("TS_PIN", "axp288-batt", "axp288-batt-temp"), + AXP288_ADC_MAP("PMIC_TEMP", "axp288-pmic", "axp288-pmic-temp"), + AXP288_ADC_MAP("GPADC", "axp288-gpadc", "axp288-system-temp"), + AXP288_ADC_MAP("BATT_CHG_I", "axp288-chrg", "axp288-chrg-curr"), + AXP288_ADC_MAP("BATT_DISCHRG_I", "axp288-chrg", "axp288-chrg-d-curr"), + AXP288_ADC_MAP("BATT_V", "axp288-batt", "axp288-batt-volt"), + {}, +}; + +static int axp288_adc_read_channel(int *val, unsigned long address, + struct regmap *regmap) +{ + u8 buf[2]; + + if (regmap_bulk_read(regmap, address, buf, 2)) + return -EIO; + *val = (buf[0] << 4) + ((buf[1] >> 4) & 0x0F); + + return IIO_VAL_INT; +} + +static int axp288_adc_set_ts(struct regmap *regmap, unsigned int mode, + unsigned long address) +{ + /* channels other than GPADC do not need to switch TS pin */ + if (address != AXP288_GP_ADC_H) + return 0; + + return regmap_write(regmap, AXP288_ADC_TS_PIN_CTRL, mode); +} + +static int axp288_adc_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + int ret; + struct axp288_adc_info *info = iio_priv(indio_dev); + + mutex_lock(&indio_dev->mlock); + switch (mask) { + case IIO_CHAN_INFO_RAW: + if (axp288_adc_set_ts(info->regmap, AXP288_ADC_TS_PIN_GPADC, + chan->address)) { + dev_err(&indio_dev->dev, "GPADC mode\n"); + ret = -EINVAL; + break; + } + ret = axp288_adc_read_channel(val, chan->address, info->regmap); + if (axp288_adc_set_ts(info->regmap, AXP288_ADC_TS_PIN_ON, + chan->address)) + dev_err(&indio_dev->dev, "TS pin restore\n"); + break; + case IIO_CHAN_INFO_PROCESSED: + ret = axp288_adc_read_channel(val, chan->address, info->regmap); + break; + default: + ret = -EINVAL; + } + mutex_unlock(&indio_dev->mlock); + + return ret; +} + +static int axp288_adc_set_state(struct regmap *regmap) +{ + /* ADC should be always enabled for internal FG to function */ + if (regmap_write(regmap, AXP288_ADC_TS_PIN_CTRL, AXP288_ADC_TS_PIN_ON)) + return -EIO; + + return regmap_write(regmap, AXP20X_ADC_EN1, AXP288_ADC_EN_MASK); +} + +static const struct iio_info axp288_adc_iio_info = { + .read_raw = &axp288_adc_read_raw, + .driver_module = THIS_MODULE, +}; + +static int axp288_adc_probe(struct platform_device *pdev) +{ + int ret; + struct axp288_adc_info *info; + struct iio_dev *indio_dev; + struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); + if (!indio_dev) + return -ENOMEM; + + info = iio_priv(indio_dev); + info->irq = platform_get_irq(pdev, 0); + if (info->irq < 0) { + dev_err(&pdev->dev, "no irq resource?\n"); + return info->irq; + } + platform_set_drvdata(pdev, indio_dev); + info->regmap = axp20x->regmap; + /* + * Set ADC to enabled state at all time, including system suspend. + * otherwise internal fuel gauge functionality may be affected. + */ + ret = axp288_adc_set_state(axp20x->regmap); + if (ret) { + dev_err(&pdev->dev, "unable to enable ADC device\n"); + return ret; + } + + indio_dev->dev.parent = &pdev->dev; + indio_dev->name = pdev->name; + indio_dev->channels = axp288_adc_channels; + indio_dev->num_channels = ARRAY_SIZE(axp288_adc_channels); + indio_dev->info = &axp288_adc_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + ret = iio_map_array_register(indio_dev, axp288_adc_default_maps); + if (ret < 0) + return ret; + + ret = iio_device_register(indio_dev); + if (ret < 0) { + dev_err(&pdev->dev, "unable to register iio device\n"); + goto err_array_unregister; + } + return 0; + +err_array_unregister: + iio_map_array_unregister(indio_dev); + + return ret; +} + +static int axp288_adc_remove(struct platform_device *pdev) +{ + struct iio_dev *indio_dev = platform_get_drvdata(pdev); + + iio_device_unregister(indio_dev); + iio_map_array_unregister(indio_dev); + + return 0; +} + +static struct platform_driver axp288_adc_driver = { + .probe = axp288_adc_probe, + .remove = axp288_adc_remove, + .driver = { + .name = "axp288_adc", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(axp288_adc_driver); + +MODULE_AUTHOR("Jacob Pan "); +MODULE_DESCRIPTION("X-Powers AXP288 ADC Driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 439e8211a78ad31615c76b18e4f13eb900c89758 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Thu, 9 Oct 2014 17:02:54 +0800 Subject: regmap: cache: fix errno in regcache_hw_init() When kmalloc() fails, we should return -ENOMEM. Signed-off-by: Xiubo Li Signed-off-by: Mark Brown --- drivers/base/regmap/regcache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index f1280dc356d0..44e6a48019a5 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -44,7 +44,7 @@ static int regcache_hw_init(struct regmap *map) map->cache_bypass = 1; tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); if (!tmp_buf) - return -EINVAL; + return -ENOMEM; ret = regmap_raw_read(map, 0, tmp_buf, map->num_reg_defaults_raw); map->cache_bypass = cache_bypass; -- cgit v1.2.3 From 729de41baf63e2172b9d61de61bbd53f231095ca Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Fri, 10 Oct 2014 10:21:14 -0500 Subject: reset: add reset_control_status helper function There are cases where a system will want to read a reset status bit before doing any other toggling. Add a reset_control_status helper function to the reset controller API. Signed-off-by: Dinh Nguyen Signed-off-by: Philipp Zabel --- drivers/reset/core.c | 15 +++++++++++++++ include/linux/reset-controller.h | 2 ++ include/linux/reset.h | 7 +++++++ 3 files changed, 24 insertions(+) diff --git a/drivers/reset/core.c b/drivers/reset/core.c index baeaf82d40d9..7955e00d04d4 100644 --- a/drivers/reset/core.c +++ b/drivers/reset/core.c @@ -125,6 +125,21 @@ int reset_control_deassert(struct reset_control *rstc) } EXPORT_SYMBOL_GPL(reset_control_deassert); +/** + * reset_control_status - returns a negative errno if not supported, a + * positive value if the reset line is asserted, or zero if the reset + * line is not asserted. + * @rstc: reset controller + */ +int reset_control_status(struct reset_control *rstc) +{ + if (rstc->rcdev->ops->status) + return rstc->rcdev->ops->status(rstc->rcdev, rstc->id); + + return -ENOSYS; +} +EXPORT_SYMBOL_GPL(reset_control_status); + /** * of_reset_control_get - Lookup and obtain a reference to a reset controller. * @node: device to be reset by the controller diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h index 41a4695fde08..ce6b962ffed4 100644 --- a/include/linux/reset-controller.h +++ b/include/linux/reset-controller.h @@ -12,11 +12,13 @@ struct reset_controller_dev; * things to reset the device * @assert: manually assert the reset line, if supported * @deassert: manually deassert the reset line, if supported + * @status: return the status of the reset line, if supported */ struct reset_control_ops { int (*reset)(struct reset_controller_dev *rcdev, unsigned long id); int (*assert)(struct reset_controller_dev *rcdev, unsigned long id); int (*deassert)(struct reset_controller_dev *rcdev, unsigned long id); + int (*status)(struct reset_controller_dev *rcdev, unsigned long id); }; struct module; diff --git a/include/linux/reset.h b/include/linux/reset.h index 349f150ae12c..da5602bd77d7 100644 --- a/include/linux/reset.h +++ b/include/linux/reset.h @@ -10,6 +10,7 @@ struct reset_control; int reset_control_reset(struct reset_control *rstc); int reset_control_assert(struct reset_control *rstc); int reset_control_deassert(struct reset_control *rstc); +int reset_control_status(struct reset_control *rstc); struct reset_control *reset_control_get(struct device *dev, const char *id); void reset_control_put(struct reset_control *rstc); @@ -57,6 +58,12 @@ static inline int reset_control_deassert(struct reset_control *rstc) return 0; } +static inline int reset_control_status(struct reset_control *rstc) +{ + WARN_ON(1); + return 0; +} + static inline void reset_control_put(struct reset_control *rstc) { WARN_ON(1); -- cgit v1.2.3 From be8a77c54815b311485a348547ec80803ee9415b Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 13 Sep 2014 00:34:29 +0200 Subject: ARM: dts: rockchip: add operating points and armclk references Add basic OPP entries for current supported Rockchip SoCs. The operating points are currently very conservative, so individual boards may opt to redefine them. Signed-off-by: Heiko Stuebner Reviewed-by: Kever Yang --- arch/arm/boot/dts/rk3066a.dtsi | 12 +++++++++++- arch/arm/boot/dts/rk3188.dtsi | 15 ++++++++++++++- arch/arm/boot/dts/rk3288.dtsi | 19 ++++++++++++++++++- 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index ad9c2db59670..8b11fbd58071 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -26,11 +26,21 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1008000 1075000 + 816000 1025000 + 600000 1025000 + 504000 1000000 + 312000 975000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ddaada788b45..ae4f04984d86 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -26,11 +26,24 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1608000 1350000 + 1416000 1250000 + 1200000 1150000 + 1008000 1075000 + 816000 975000 + 600000 950000 + 504000 925000 + 312000 875000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 874e66dbb93b..cb18bb457568 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -47,10 +47,27 @@ #address-cells = <1>; #size-cells = <0>; - cpu@500 { + cpu0: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x500>; + operating-points = < + /* KHz uV */ + 1608000 1350000 + 1512000 1300000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 312000 900000 + 216000 900000 + 126000 900000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@501 { device_type = "cpu"; -- cgit v1.2.3 From 3adb1327fb020394a10394a5117ac7d2ec5334d3 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 13 Sep 2014 00:34:30 +0200 Subject: ARM: dts: rockchip: add cpu supplies to boards This adds the cpu-supplies to the curie2, radxarock and rk3288-evb-rk808 boards. The rk3288-evb-act8846 variant cannot provide the cpu-regulator at the moment so will get its supply later. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a-bqcurie2.dts | 4 ++++ arch/arm/boot/dts/rk3188-radxarock.dts | 6 +++++- arch/arm/boot/dts/rk3288-evb-rk808.dts | 6 +++++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index d5344510c676..baf21ac6ce7f 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -60,6 +60,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 15910c9ddbc7..0950a0524947 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -118,6 +118,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -159,7 +163,7 @@ vdd_arm: REG3 { regulator-name = "VDD_ARM"; regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; regulator-always-on; }; diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index ff522f8e3df4..d8c775e6d5fe 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -17,6 +17,10 @@ compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; }; +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + &i2c0 { clock-frequency = <400000>; status = "okay"; @@ -44,7 +48,7 @@ regulator-always-on; regulator-boot-on; regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; regulator-name = "vdd_arm"; }; -- cgit v1.2.3 From b3e3a7b25825407144a0178f291b20697f1537fb Mon Sep 17 00:00:00 2001 From: Julien CHAUVEAU Date: Fri, 10 Oct 2014 10:04:13 +0200 Subject: ARM: dts: rockchip: enable DMA on SPI for rk3066 and rk3188 According to the RK3066 and RK3188 TRM, the two SPI controllers support DMA handshake interface. Add the DMA properties so they can be used when needed. Signed-off-by: Julien CHAUVEAU Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3xxx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 499468d42ada..9ba92de511ca 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -367,6 +367,8 @@ reg = <0x20070000 0x1000>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmac2 10>, <&dmac2 11>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -378,6 +380,8 @@ reg = <0x20074000 0x1000>; #address-cells = <1>; #size-cells = <0>; + dmas = <&dmac2 12>, <&dmac2 13>; + dma-names = "tx", "rx"; status = "disabled"; }; }; -- cgit v1.2.3 From 5fe62b83cfed00b10b70593e95ffbeadf77ece78 Mon Sep 17 00:00:00 2001 From: Julien CHAUVEAU Date: Tue, 14 Oct 2014 10:16:37 +0200 Subject: ARM: dts: rockchip: add I2S controllers for rk3066 and rk3188 Add the I2S/PCM controller nodes and pin controls for rk3066 and rk3188. Signed-off-by: Julien CHAUVEAU Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3066a.dtsi | 81 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3188.dtsi | 26 ++++++++++++++ 2 files changed, 107 insertions(+) diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 8b11fbd58071..0e99470db772 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -63,6 +63,51 @@ }; }; + i2s0: i2s@10118000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x10118000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 4>, <&dmac1_s 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + status = "disabled"; + }; + + i2s1: i2s@1011a000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@1011c000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011c000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + dmas = <&dmac1_s 9>, <&dmac1_s 10>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; + status = "disabled"; + }; + cru: clock-controller@20000000 { compatible = "rockchip,rk3066a-cru"; reg = <0x20000000 0x1000>; @@ -415,6 +460,42 @@ ; }; }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = , + , + , + , + , + , + , + , + ; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; + + i2s2 { + i2s2_bus: i2s2-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; }; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ae4f04984d86..b24e04f6ccc7 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -78,6 +78,21 @@ }; }; + i2s0: i2s@1011a000 { + compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + status = "disabled"; + }; + cru: clock-controller@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; @@ -408,6 +423,17 @@ ; }; }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = , + , + , + , + , + ; + }; + }; }; }; -- cgit v1.2.3 From cd78d0cd63ebce518b5c342fe6ef1f4613bb039d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 9 Oct 2014 21:50:30 -0700 Subject: ARM: dts: rockchip: enable init rate for clock We need to initialize PLL rate and some of bus clock rate while kernel init, for there is no other module will do that. Basically on rk3288 we use GPLL for cpu bus, peripheral bus and most of peripheral clock, CPLL for devices who require 50M/200M clock rate, leave NPLL behind for special requirement from display system. The common-clock-framework will help us to select best source for child clocks after we init the PLLs propriety. Signed-off-by: Kever Yang Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cb18bb457568..b53e833e5667 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -472,6 +472,16 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <400000000>, + <500000000>, <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; }; grf: syscon@ff770000 { -- cgit v1.2.3 From fe08be3ec8672ed92b3ed1b85810df9fa0f98931 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Mon, 6 Oct 2014 21:33:36 +0200 Subject: regulator: anatop: Set default voltage selector for vddpu The code reads the default voltage selector from its register. If the bootloader disables the regulator, the default voltage selector will be 0 which results in faulty behaviour of this regulator driver. This patch sets a default voltage selector for vddpu if it is not set in the register. Signed-off-by: Markus Pargmann Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- drivers/regulator/anatop-regulator.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c index 4f730af70e7c..30e8d7ad5813 100644 --- a/drivers/regulator/anatop-regulator.c +++ b/drivers/regulator/anatop-regulator.c @@ -283,6 +283,14 @@ static int anatop_regulator_probe(struct platform_device *pdev) sreg->sel = 0; sreg->bypass = true; } + + /* + * In case vddpu was disabled by the bootloader, we need to set + * a sane default until imx6-cpufreq was probed and changes the + * voltage to the correct value. In this case we set 1.25V. + */ + if (!sreg->sel && !strcmp(sreg->name, "vddpu")) + sreg->sel = 22; } else { rdesc->ops = &anatop_rops; } -- cgit v1.2.3 From da0607c8df5c6277ff75468f24e055f193b6b336 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Mon, 6 Oct 2014 21:33:37 +0200 Subject: regulator: anatop: Fail on invalid voltage selector A '0' voltage selector is invalid and can't be used with this driver. Signed-off-by: Markus Pargmann Signed-off-by: Mark Brown --- drivers/regulator/anatop-regulator.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c index 30e8d7ad5813..542d14ed48bb 100644 --- a/drivers/regulator/anatop-regulator.c +++ b/drivers/regulator/anatop-regulator.c @@ -291,6 +291,11 @@ static int anatop_regulator_probe(struct platform_device *pdev) */ if (!sreg->sel && !strcmp(sreg->name, "vddpu")) sreg->sel = 22; + + if (!sreg->sel) { + dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n"); + return -EINVAL; + } } else { rdesc->ops = &anatop_rops; } -- cgit v1.2.3 From 76f439df50aba1838e06dd01e5f20dada7473f57 Mon Sep 17 00:00:00 2001 From: Markus Pargmann Date: Wed, 8 Oct 2014 15:47:05 +0200 Subject: regulator: Add ena_gpio_initialized to regulator_config Most drivers do not set the ena_gpio field of struct regulator_config before passing it to the regulator core. This is fine as long as the gpio identifier that is passed is a positive integer. But the gpio identifier 0 is also valid. So we are not able to decide wether we got a real gpio identifier or not based on a 0 in ena_gpio. To be able to decide if it is a valid gpio that got passed, this patch adds a ena_gpio_initialized field that should be set if was initialized with a correct value, either a gpio >= 0 or a negative error number. The core then checks if ena_gpio or ena_gpio_initialized before handling it as a gpio. This way we maintain backwards compatibility and fix the behaviour for gpio number 0. Signed-off-by: Markus Pargmann Signed-off-by: Mark Brown --- drivers/regulator/core.c | 3 ++- include/linux/regulator/driver.h | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index cd87c0c37034..55a87a2722d8 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -3650,7 +3650,8 @@ regulator_register(const struct regulator_desc *regulator_desc, dev_set_drvdata(&rdev->dev, rdev); - if (config->ena_gpio && gpio_is_valid(config->ena_gpio)) { + if ((config->ena_gpio || config->ena_gpio_initialized) && + gpio_is_valid(config->ena_gpio)) { ret = regulator_ena_gpio_request(rdev, config); if (ret != 0) { rdev_err(rdev, "Failed to request enable GPIO%d: %d\n", diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h index fc0ee0ce8325..28da08e4671f 100644 --- a/include/linux/regulator/driver.h +++ b/include/linux/regulator/driver.h @@ -301,6 +301,9 @@ struct regulator_desc { * NULL). * @regmap: regmap to use for core regmap helpers if dev_get_regulator() is * insufficient. + * @ena_gpio_initialized: GPIO controlling regulator enable was properly + * initialized, meaning that >= 0 is a valid gpio + * identifier and < 0 is a non existent gpio. * @ena_gpio: GPIO controlling regulator enable. * @ena_gpio_invert: Sense for GPIO enable control. * @ena_gpio_flags: Flags to use when calling gpio_request_one() @@ -312,6 +315,7 @@ struct regulator_config { struct device_node *of_node; struct regmap *regmap; + bool ena_gpio_initialized; int ena_gpio; unsigned int ena_gpio_invert:1; unsigned int ena_gpio_flags; -- cgit v1.2.3 From e6fb2aac552ab229e01169776199c13e2524c318 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 15 Oct 2014 18:20:31 +0200 Subject: regulator: max77802: Add .set_suspend_{enable,disable} callbacks The max77802 PMIC has an enable pin (PWRREQ) that can be used to switch regulators ON and OFF automatically by the Application Processor when the system is leaving and entering sleep mode. Only the BUCKs regulators had a .set_suspend_disable function handler that used the enable pin to turn OFF the regulators during suspend. But most LDOs also support that functionality (besides 1, 3, 20 and 21) so rename the function to a more generic name and use the same function for the LDOs. Also add a .set_suspend_enable handler for all regulators and use the same function used for the .enable operation. Finally, don't treat output ON/OFF controlled by PWRREQ as an operating mode using the ambiguous MAX77802_OPMODE_STANDBY since it's not an opmode. Instead make it clear that is a control value to switch the regulator OFF by PWRREQ when the system is entering in a suspend state. Signed-off-by: Javier Martinez Canillas Signed-off-by: Mark Brown --- drivers/regulator/max77802.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/regulator/max77802.c b/drivers/regulator/max77802.c index d89792b084e9..26f6963108e3 100644 --- a/drivers/regulator/max77802.c +++ b/drivers/regulator/max77802.c @@ -49,6 +49,8 @@ #define MAX77802_RAMP_RATE_MASK_4BIT 0xF0 #define MAX77802_RAMP_RATE_SHIFT_4BIT 4 +#define MAX77802_OFF_PWRREQ 0x1 + /* MAX77802 has two register formats: 2-bit and 4-bit */ static const unsigned int ramp_table_77802_2bit[] = { 12500, @@ -83,17 +85,16 @@ static int max77802_get_opmode_shift(int id) return -EINVAL; } -/* - * Some BUCKS supports Normal[ON/OFF] mode during suspend +/** + * max77802_set_suspend_disable - Disable the regulator during system suspend + * @rdev: regulator to mark as disabled * - * BUCK 1, 6, 2-4, 5, 7-10 (all) - * - * The other mode (0x02) will make PWRREQ switch between normal - * and low power. + * All regulators expect LDO 1, 3, 20 and 21 support OFF by PWRREQ. + * Configure the regulator so the PMIC will turn it OFF during system suspend. */ -static int max77802_buck_set_suspend_disable(struct regulator_dev *rdev) +static int max77802_set_suspend_disable(struct regulator_dev *rdev) { - unsigned int val = MAX77802_OPMODE_STANDBY; + unsigned int val = MAX77802_OFF_PWRREQ; struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); int id = rdev_get_id(rdev); int shift = max77802_get_opmode_shift(id); @@ -178,6 +179,9 @@ static int max77802_enable(struct regulator_dev *rdev) int id = rdev_get_id(rdev); int shift = max77802_get_opmode_shift(id); + if (max77802->opmode[id] == MAX77802_OFF_PWRREQ) + max77802->opmode[id] = MAX77802_OPMODE_NORMAL; + return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, rdev->desc->enable_mask, max77802->opmode[id] << shift); @@ -247,6 +251,8 @@ static struct regulator_ops max77802_ldo_ops_logic1 = { .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, .set_voltage_time_sel = regulator_set_voltage_time_sel, + .set_suspend_enable = max77802_enable, + .set_suspend_disable = max77802_set_suspend_disable, .set_suspend_mode = max77802_ldo_set_suspend_mode_logic1, }; @@ -276,7 +282,8 @@ static struct regulator_ops max77802_buck_16_dvs_ops = { .set_voltage_sel = regulator_set_voltage_sel_regmap, .set_voltage_time_sel = regulator_set_voltage_time_sel, .set_ramp_delay = max77802_set_ramp_delay_4bit, - .set_suspend_disable = max77802_buck_set_suspend_disable, + .set_suspend_enable = max77802_enable, + .set_suspend_disable = max77802_set_suspend_disable, }; /* BUCKs 2-4, 5, 7-10 */ @@ -290,7 +297,8 @@ static struct regulator_ops max77802_buck_dvs_ops = { .set_voltage_sel = regulator_set_voltage_sel_regmap, .set_voltage_time_sel = regulator_set_voltage_time_sel, .set_ramp_delay = max77802_set_ramp_delay_2bit, - .set_suspend_disable = max77802_buck_set_suspend_disable, + .set_suspend_enable = max77802_enable, + .set_suspend_disable = max77802_set_suspend_disable, }; /* LDOs 3-7, 9-14, 18-26, 28, 29, 32-34 */ -- cgit v1.2.3 From b0615f1da543500f8442fa6e5adacb8c54b34c5f Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 15 Oct 2014 18:20:33 +0200 Subject: regulator: max77802: Split regulator operations for BUCKs Not all the max77802 BUCKs regulators have the same functionality, for example BUCKs 2-4 support the output to be configured as normal or Low Power Mode by the PWRREQ enable pin while the other BUCKs only support their output to be set ON or OFF by PWRREQ. As a preparation for adding a set_suspend_mode function handler for all the regulators that support Low Power Mode by PWRREQ, split the operations for BUCKs regulators. Signed-off-by: Javier Martinez Canillas Signed-off-by: Mark Brown --- drivers/regulator/max77802.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/max77802.c b/drivers/regulator/max77802.c index 26f6963108e3..8425c0d520a8 100644 --- a/drivers/regulator/max77802.c +++ b/drivers/regulator/max77802.c @@ -286,7 +286,22 @@ static struct regulator_ops max77802_buck_16_dvs_ops = { .set_suspend_disable = max77802_set_suspend_disable, }; -/* BUCKs 2-4, 5, 7-10 */ +/* BUCKs 2-4 */ +static struct regulator_ops max77802_buck_234_ops = { + .list_voltage = regulator_list_voltage_linear, + .map_voltage = regulator_map_voltage_linear, + .is_enabled = regulator_is_enabled_regmap, + .enable = max77802_enable, + .disable = regulator_disable_regmap, + .get_voltage_sel = regulator_get_voltage_sel_regmap, + .set_voltage_sel = regulator_set_voltage_sel_regmap, + .set_voltage_time_sel = regulator_set_voltage_time_sel, + .set_ramp_delay = max77802_set_ramp_delay_2bit, + .set_suspend_enable = max77802_enable, + .set_suspend_disable = max77802_set_suspend_disable, +}; + +/* BUCKs 5, 7-10 */ static struct regulator_ops max77802_buck_dvs_ops = { .list_voltage = regulator_list_voltage_linear, .map_voltage = regulator_map_voltage_linear, @@ -360,7 +375,7 @@ static struct regulator_ops max77802_buck_dvs_ops = { .name = "BUCK"#num, \ .id = MAX77802_BUCK##num, \ .supply_name = "inb"#num, \ - .ops = &max77802_buck_dvs_ops, \ + .ops = &max77802_buck_234_ops, \ .type = REGULATOR_VOLTAGE, \ .owner = THIS_MODULE, \ .min_uV = 600000, \ -- cgit v1.2.3 From efbe519945746371f92f5c3796818bf3e24c80ad Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 16 Oct 2014 18:48:47 +0200 Subject: regulator: max77802: Add .{get,set}_mode callbacks Some max77802 LDOs (1, 3, 20 and 21) support to be configured in Low Power Mode during system normal operation. Add function handlers for the .get_mode and .set_mode operations to set the mode on these LDOs. Signed-off-by: Javier Martinez Canillas Signed-off-by: Mark Brown --- drivers/regulator/max77802.c | 46 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/regulator/max77802.c b/drivers/regulator/max77802.c index 8425c0d520a8..6eabb954ec7c 100644 --- a/drivers/regulator/max77802.c +++ b/drivers/regulator/max77802.c @@ -70,6 +70,12 @@ struct max77802_regulator_prv { unsigned int opmode[MAX77802_REG_MAX]; }; +static inline int max77802_map_mode(int mode) +{ + return mode == MAX77802_OPMODE_NORMAL ? + REGULATOR_MODE_NORMAL : REGULATOR_MODE_STANDBY; +} + static int max77802_get_opmode_shift(int id) { if (id == MAX77802_BUCK1 || (id >= MAX77802_BUCK5 && @@ -104,6 +110,44 @@ static int max77802_set_suspend_disable(struct regulator_dev *rdev) rdev->desc->enable_mask, val << shift); } +/* + * Some LDOs support Low Power Mode while the system is running. + * + * LDOs 1, 3, 20, 21. + */ +static int max77802_set_mode(struct regulator_dev *rdev, unsigned int mode) +{ + struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); + int id = rdev_get_id(rdev); + unsigned int val; + int shift = max77802_get_opmode_shift(id); + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val = MAX77802_OPMODE_LP; /* ON in Low Power Mode */ + break; + case REGULATOR_MODE_NORMAL: + val = MAX77802_OPMODE_NORMAL; /* ON in Normal Mode */ + break; + default: + dev_warn(&rdev->dev, "%s: regulator mode: 0x%x not supported\n", + rdev->desc->name, mode); + return -EINVAL; + } + + max77802->opmode[id] = val; + return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, + rdev->desc->enable_mask, val << shift); +} + +static unsigned max77802_get_mode(struct regulator_dev *rdev) +{ + struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); + int id = rdev_get_id(rdev); + + return max77802_map_mode(max77802->opmode[id]); +} + /* * Some LDOs supports LPM-ON/OFF/Normal-ON mode during suspend state * (Enable Control Logic1 by PWRREQ) @@ -268,6 +312,8 @@ static struct regulator_ops max77802_ldo_ops_logic2 = { .get_voltage_sel = regulator_get_voltage_sel_regmap, .set_voltage_sel = regulator_set_voltage_sel_regmap, .set_voltage_time_sel = regulator_set_voltage_time_sel, + .set_mode = max77802_set_mode, + .get_mode = max77802_get_mode, .set_suspend_mode = max77802_ldo_set_suspend_mode_logic2, }; -- cgit v1.2.3 From 2e0eaa1aa0084ff1ee1af7cf388358b868143816 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 16 Oct 2014 18:48:48 +0200 Subject: regulator: max77802: Add set suspend mode for BUCKs and simplify code The max77802 PMIC has a special enable pin (PWRREQ) that can be used by the Application Processor (AP) to power down and up voltage rails. The max77802 PMIC regulators have 3 different enable control logics. Some regulators support to be configured on different operational mode during normal operation while others only support to be put in a Low Power Mode while the system has entered in sleep mode. Some regulators don't even support that configuration. The logics are the following: Enable Control Logic1 by PWRREQ (BUCK 2-4, LDO2, LDO4-19, LDO22, LDO35) ------------------------------- 0: Output OFF 1: Output ON/OFF (Controlled by PWRREQ) PWRREQ = HIGH (1): Output ON in Normal Mode PWRREQ = LOW (0): Output OFF 2: Output On with Low Power Mode (Controlled by PWRREQ) PWRREQ = HIGH (1) : Output ON in Normal Mode PWRREQ = LOW (0): Output ON in Low Power Mode 3: Output ON in Normal Mode Enable Control Logic2 by PWRREQ (LDO1, LDO20, LDO21) ------------------------------- 0: Output ON/OFF by ENx 1: Output ON in Low Power Mode 2: Output ON in Low Power Mode (Controlled by PWRREQ) PWRREQ = HIGH (1): Output ON in Normal Mode PWRREQ = LOW (0): Output ON in Low Power Mode 3: Output ON in Normal Mode Enable Control Logic3 by PWRREQ (LDO3) ------------------------------- 0 or 3: Output ON in Normal Mode 1: Output ON in Low Power Mode 2: Output ON in Low Power Mode (Controlled by PWRREQ) PWRREQ = HIGH (1): Output ON in Normal Mode PWRREQ = LOW (0): Output ON in Low Power Mode The driver only implemented .set_suspend_mode for the LDOs regulators but some BUCKs also support to be put in Low Power Mode on system wide suspend so they should be supported as well. Two different functions were used for the logic 1 and 2 but this is not necessary. Only normal and Low Power Mode are valid operational modes, OFF is not an mode but is a regulator state that is handled by .set_suspend_enable ad .set_suspend_disable. So the same .set_suspend_mode function can be used by all the regulators that support Output On with Low Power Mode by PWRREQ, making much simpler the code to set the suspend mode. Signed-off-by: Javier Martinez Canillas Signed-off-by: Mark Brown --- drivers/regulator/max77802.c | 93 ++++++++++++++++++++++---------------------- 1 file changed, 46 insertions(+), 47 deletions(-) diff --git a/drivers/regulator/max77802.c b/drivers/regulator/max77802.c index 6eabb954ec7c..dae2c1acd879 100644 --- a/drivers/regulator/max77802.c +++ b/drive