From 6fae8663c9940bcaa9edd8e21a9ae0f562789a3d Mon Sep 17 00:00:00 2001 From: "Naveen N. Rao" Date: Wed, 2 Aug 2017 20:12:16 +0530 Subject: perf scripting python: Add ppc64le to audit uname list Before patch: $ uname -m ppc64le $ ./perf script -s ./scripts/python/syscall-counts.py Install the audit-libs-python package to get syscall names. For example: # apt-get install python-audit (Ubuntu) # yum install audit-libs-python (Fedora) etc. Press control+C to stop and show the summary ^CWarning: 4 out of order events recorded. syscall events: event count ---------------------------------------- ----------- 4 504638 54 1206 221 42 55 21 3 12 167 10 11 8 6 7 125 6 5 6 108 5 162 4 90 4 45 3 33 3 311 1 246 1 238 1 93 1 91 1 After patch: ./perf script -s ./scripts/python/syscall-counts.py Press control+C to stop and show the summary ^CWarning: 5 out of order events recorded. syscall events: event count ---------------------------------------- ----------- write 643411 ioctl 1206 futex 54 fcntl 27 poll 14 read 12 execve 8 close 7 mprotect 6 open 6 nanosleep 5 fstat 5 mmap 4 inotify_add_watch 3 brk 3 access 3 timerfd_settime 1 clock_gettime 1 epoll_wait 1 ftruncate 1 munmap 1 Signed-off-by: Naveen N. Rao Acked-by: Paul Clarke Cc: linuxppc-dev@lists.ozlabs.org Link: http://lkml.kernel.org/n/tip-bnl67p1alkvx97pn9moxz3qp@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py index 1d95009592eb..f6c84966e4f8 100644 --- a/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py +++ b/tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/Util.py @@ -57,6 +57,7 @@ try: 'ia64' : audit.MACH_IA64, 'ppc' : audit.MACH_PPC, 'ppc64' : audit.MACH_PPC64, + 'ppc64le' : audit.MACH_PPC64LE, 's390' : audit.MACH_S390, 's390x' : audit.MACH_S390X, 'i386' : audit.MACH_X86, -- cgit v1.2.3 From 2862a16875452b697c65d8e06cc010c922d19171 Mon Sep 17 00:00:00 2001 From: Sukadev Bhattiprolu Date: Thu, 27 Jul 2017 01:42:29 -0400 Subject: perf vendor events powerpc: remove suffix in mapfile Drop the .json suffix for events directory in the mapfile.csv. Now that we have separate JSON files for each topic in a CPU (eg: see tools/perf/pmu-events/arch/powerpc/power8/*.json) the .json suffix in the mapfile is misleading and redundant. Reported-by: Michael Ellerman Signed-off-by: Sukadev Bhattiprolu Cc: Anton Blanchard Cc: Jiri Olsa Link: http://lkml.kernel.org/r/20170802174617.GA32545@us.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/pmu-events/arch/powerpc/mapfile.csv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tools/perf/pmu-events/arch/powerpc/mapfile.csv b/tools/perf/pmu-events/arch/powerpc/mapfile.csv index 14318ef215f8..a0f3a11ca19f 100644 --- a/tools/perf/pmu-events/arch/powerpc/mapfile.csv +++ b/tools/perf/pmu-events/arch/powerpc/mapfile.csv @@ -13,13 +13,13 @@ # # Power8 entries -004b0000,1,power8.json,core -004b0201,1,power8.json,core -004c0000,1,power8.json,core -004d0000,1,power8.json,core -004d0100,1,power8.json,core -004d0200,1,power8.json,core -004c0100,1,power8.json,core -004e0100,1,power9.json,core -004e0200,1,power9.json,core -004e1200,1,power9.json,core +004b0000,1,power8,core +004b0201,1,power8,core +004c0000,1,power8,core +004d0000,1,power8,core +004d0100,1,power8,core +004d0200,1,power8,core +004c0100,1,power8,core +004e0100,1,power9,core +004e0200,1,power9,core +004e1200,1,power9,core -- cgit v1.2.3 From 3c22ba5243040c13f9a79e3ae70399c0ae0872a4 Mon Sep 17 00:00:00 2001 From: Sukadev Bhattiprolu Date: Thu, 27 Jul 2017 02:23:57 -0400 Subject: perf vendor events powerpc: Update POWER9 events Update and cleanup POWER9 PMU events. Signed-off-by: Sukadev Bhattiprolu Cc: Anton Blanchard Cc: Jiri Olsa Cc: Michael Ellerman Link: http://lkml.kernel.org/r/20170802174617.GA32545@us.ibm.com Signed-off-by: Arnaldo Carvalho de Melo --- .../perf/pmu-events/arch/powerpc/power9/cache.json | 191 +- .../arch/powerpc/power9/floating-point.json | 42 +- .../pmu-events/arch/powerpc/power9/frontend.json | 517 ++-- .../pmu-events/arch/powerpc/power9/marked.json | 905 +++---- .../pmu-events/arch/powerpc/power9/memory.json | 178 +- .../perf/pmu-events/arch/powerpc/power9/other.json | 2768 ++++++++++++++++---- .../pmu-events/arch/powerpc/power9/pipeline.json | 779 +++--- tools/perf/pmu-events/arch/powerpc/power9/pmc.json | 167 +- .../arch/powerpc/power9/translation.json | 314 +-- 9 files changed, 3537 insertions(+), 2324 deletions(-) diff --git a/tools/perf/pmu-events/arch/powerpc/power9/cache.json b/tools/perf/pmu-events/arch/powerpc/power9/cache.json index 437c83b7e6af..18f6645f2897 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/cache.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/cache.json @@ -1,176 +1,137 @@ [ {, - "EventCode": "0x1002A", - "EventName": "PM_CMPLU_STALL_LARX", - "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied", - "PublicDescription": "" + "EventCode": "0x300F4", + "EventName": "PM_THRD_CONC_RUN_INST", + "BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set" }, {, - "EventCode": "0x1003C", - "EventName": "PM_CMPLU_STALL_DMISS_L2L3", - "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3", - "PublicDescription": "" + "EventCode": "0x1E056", + "EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD", + "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion" }, {, - "EventCode": "0x14048", - "EventName": "PM_INST_FROM_ON_CHIP_CACHE", - "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x4D016", + "EventName": "PM_CMPLU_STALL_FXLONG", + "BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)" }, {, - "EventCode": "0x3E054", - "EventName": "PM_LD_MISS_L1", - "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.", - "PublicDescription": "" + "EventCode": "0x2D016", + "EventName": "PM_CMPLU_STALL_FXU", + "BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes" }, {, - "EventCode": "0x400F0", - "EventName": "PM_LD_MISS_L1", - "BriefDescription": "Load Missed L1, at execution time (not gated by finish, which means this counter can be greater than loads finished)", - "PublicDescription": "" + "EventCode": "0x1D15C", + "EventName": "PM_MRK_DTLB_MISS_1G", + "BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used" }, {, - "EventCode": "0x1404A", - "EventName": "PM_INST_FROM_RL2L3_SHR", - "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x4D12A", + "EventName": "PM_MRK_DATA_FROM_RL4_CYC", + "BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load" }, {, - "EventCode": "0x1C058", - "EventName": "PM_DTLB_MISS_16G", - "BriefDescription": "Data TLB Miss page size 16G", - "PublicDescription": "" + "EventCode": "0x1003C", + "EventName": "PM_CMPLU_STALL_DMISS_L2L3", + "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3" }, {, - "EventCode": "0x1D15C", - "EventName": "PM_MRK_DTLB_MISS_1G", - "BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used", - "PublicDescription": "" + "EventCode": "0x4C014", + "EventName": "PM_CMPLU_STALL_LMQ_FULL", + "BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full" }, {, - "EventCode": "0x1E056", - "EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD", - "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion", - "PublicDescription": "" + "EventCode": "0x14048", + "EventName": "PM_INST_FROM_ON_CHIP_CACHE", + "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x101E6", - "EventName": "PM_THRESH_EXC_4096", - "BriefDescription": "Threshold counter exceed a count of 4096", - "PublicDescription": "" + "EventCode": "0x4D014", + "EventName": "PM_CMPLU_STALL_LOAD_FINISH", + "BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish" }, {, - "EventCode": "0x2C01A", - "EventName": "PM_CMPLU_STALL_LHS", - "BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data", - "PublicDescription": "" + "EventCode": "0x2404A", + "EventName": "PM_INST_FROM_RL4", + "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x2D016", - "EventName": "PM_CMPLU_STALL_FXU", - "BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes", - "PublicDescription": "" + "EventCode": "0x1404A", + "EventName": "PM_INST_FROM_RL2L3_SHR", + "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x24046", - "EventName": "PM_INST_FROM_RL2L3_MOD", - "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x401EA", + "EventName": "PM_THRESH_EXC_128", + "BriefDescription": "Threshold counter exceeded a value of 128" }, {, - "EventCode": "0x2404A", - "EventName": "PM_INST_FROM_RL4", - "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x400F6", + "EventName": "PM_BR_MPRED_CMPL", + "BriefDescription": "Number of Branch Mispredicts" }, {, "EventCode": "0x2F140", "EventName": "PM_MRK_DPTEG_FROM_L2_MEPF", - "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x2D15E", - "EventName": "PM_MRK_DTLB_MISS_16G", - "BriefDescription": "Marked Data TLB Miss page size 16G", - "PublicDescription": "" - }, - {, - "EventCode": "0x3F14A", - "EventName": "PM_MRK_DPTEG_FROM_RMEM", - "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x101E6", + "EventName": "PM_THRESH_EXC_4096", + "BriefDescription": "Threshold counter exceed a count of 4096" }, {, "EventCode": "0x3D156", "EventName": "PM_MRK_DTLB_MISS_64K", - "BriefDescription": "Marked Data TLB Miss page size 64K", - "PublicDescription": "" + "BriefDescription": "Marked Data TLB Miss page size 64K" }, {, - "EventCode": "0x3006C", - "EventName": "PM_RUN_CYC_SMT2_MODE", - "BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode", - "PublicDescription": "" + "EventCode": "0x4C15E", + "EventName": "PM_MRK_DTLB_MISS_16M", + "BriefDescription": "Marked Data TLB Miss page size 16M" }, {, - "EventCode": "0x300F4", - "EventName": "PM_THRD_CONC_RUN_INST", - "BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set", - "PublicDescription": "" + "EventCode": "0x2D15E", + "EventName": "PM_MRK_DTLB_MISS_16G", + "BriefDescription": "Marked Data TLB Miss page size 16G" }, {, - "EventCode": "0x4C014", - "EventName": "PM_CMPLU_STALL_LMQ_FULL", - "BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full", - "PublicDescription": "" + "EventCode": "0x3F14A", + "EventName": "PM_MRK_DPTEG_FROM_RMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, "EventCode": "0x4C016", "EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT", - "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict", - "PublicDescription": "" - }, - {, - "EventCode": "0x4D014", - "EventName": "PM_CMPLU_STALL_LOAD_FINISH", - "BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish", - "PublicDescription": "" + "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict" }, {, - "EventCode": "0x4D016", - "EventName": "PM_CMPLU_STALL_FXLONG", - "BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)", - "PublicDescription": "" + "EventCode": "0x2C01A", + "EventName": "PM_CMPLU_STALL_LHS", + "BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data" }, {, - "EventCode": "0x4D12A", - "EventName": "PM_MRK_DATA_FROM_RL4_CYC", - "BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load", - "PublicDescription": "" + "EventCode": "0x401E4", + "EventName": "PM_MRK_DTLB_MISS", + "BriefDescription": "Marked dtlb miss" }, {, - "EventCode": "0x4C15E", - "EventName": "PM_MRK_DTLB_MISS_16M", - "BriefDescription": "Marked Data TLB Miss page size 16M", - "PublicDescription": "" + "EventCode": "0x24046", + "EventName": "PM_INST_FROM_RL2L3_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x401E4", - "EventName": "PM_MRK_DTLB_MISS", - "BriefDescription": "Marked dtlb miss", - "PublicDescription": "" + "EventCode": "0x1002A", + "EventName": "PM_CMPLU_STALL_LARX", + "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied" }, {, - "EventCode": "0x401EA", - "EventName": "PM_THRESH_EXC_128", - "BriefDescription": "Threshold counter exceeded a value of 128", - "PublicDescription": "" + "EventCode": "0x3006C", + "EventName": "PM_RUN_CYC_SMT2_MODE", + "BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode" }, {, - "EventCode": "0x400F6", - "EventName": "PM_BR_MPRED_CMPL", - "BriefDescription": "Number of Branch Mispredicts", - "PublicDescription": "" + "EventCode": "0x1C058", + "EventName": "PM_DTLB_MISS_16G", + "BriefDescription": "Data TLB Miss page size 16G" } -] +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/powerpc/power9/floating-point.json b/tools/perf/pmu-events/arch/powerpc/power9/floating-point.json index d4e4669c1cf3..8a83bca26552 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/floating-point.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/floating-point.json @@ -1,44 +1,32 @@ [ - {, - "EventCode": "0x10058", - "EventName": "PM_MEM_LOC_THRESH_IFU", - "BriefDescription": "Local Memory above threshold for IFU speculation control", - "PublicDescription": "" - }, - {, - "EventCode": "0x4505E", - "EventName": "PM_FLOP_CMPL", - "BriefDescription": "Floating Point Operation Finished", - "PublicDescription": "" - }, {, "EventCode": "0x1415A", "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", - "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load", - "PublicDescription": "" + "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load" }, {, - "EventCode": "0x2D028", - "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2", - "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache", - "PublicDescription": "" + "EventCode": "0x10058", + "EventName": "PM_MEM_LOC_THRESH_IFU", + "BriefDescription": "Local Memory above threshold for IFU speculation control" }, {, - "EventCode": "0x2D154", - "EventName": "PM_MRK_DERAT_MISS_64K", - "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K", - "PublicDescription": "" + "EventCode": "0x2D028", + "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2", + "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache" }, {, "EventCode": "0x30012", "EventName": "PM_FLUSH_COMPLETION", - "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush", - "PublicDescription": "" + "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush" + }, + {, + "EventCode": "0x2D154", + "EventName": "PM_MRK_DERAT_MISS_64K", + "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K" }, {, "EventCode": "0x4016E", "EventName": "PM_THRESH_NOT_MET", - "BriefDescription": "Threshold counter did not meet threshold", - "PublicDescription": "" + "BriefDescription": "Threshold counter did not meet threshold" } -] +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/powerpc/power9/frontend.json b/tools/perf/pmu-events/arch/powerpc/power9/frontend.json index 5da59d15af94..7e62c46d7a20 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/frontend.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/frontend.json @@ -1,446 +1,377 @@ [ {, - "EventCode": "0x20036", - "EventName": "PM_BR_2PATH", - "BriefDescription": "Branches that are not strongly biased", - "PublicDescription": "" + "EventCode": "0x3E15C", + "EventName": "PM_MRK_L2_TM_ST_ABORT_SISTER", + "BriefDescription": "TM marked store abort for this thread" }, {, - "EventCode": "0x40036", - "EventName": "PM_BR_2PATH", - "BriefDescription": "Branches that are not strongly biased", - "PublicDescription": "" + "EventCode": "0x25044", + "EventName": "PM_IPTEG_FROM_L31_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request" }, {, - "EventCode": "0x10004", - "EventName": "PM_CMPLU_STALL_LRQ_OTHER", - "BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others", - "PublicDescription": "" + "EventCode": "0x101E8", + "EventName": "PM_THRESH_EXC_256", + "BriefDescription": "Threshold counter exceed a count of 256" }, {, - "EventCode": "0x10010", - "EventName": "PM_PMC4_OVERFLOW", - "BriefDescription": "Overflow from counter 4", - "PublicDescription": "" + "EventCode": "0x4504E", + "EventName": "PM_IPTEG_FROM_L3MISS", + "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request" + }, + {, + "EventCode": "0x1006A", + "EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL", + "BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it" + }, + {, + "EventCode": "0x4E016", + "EventName": "PM_CMPLU_STALL_LSAQ_ARB", + "BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch" }, {, "EventCode": "0x1001A", "EventName": "PM_LSU_SRQ_FULL_CYC", - "BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource", - "PublicDescription": "" + "BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource" }, {, - "EventCode": "0x10020", - "EventName": "PM_PMC4_REWIND", - "BriefDescription": "PMC4 Rewind Event", - "PublicDescription": "" + "EventCode": "0x1E15E", + "EventName": "PM_MRK_L2_TM_REQ_ABORT", + "BriefDescription": "TM abort" }, {, - "EventCode": "0x1003A", - "EventName": "PM_CMPLU_STALL_LSU_FIN", - "BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish", - "PublicDescription": "" + "EventCode": "0x34052", + "EventName": "PM_INST_SYS_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch" }, {, - "EventCode": "0x1013E", - "EventName": "PM_MRK_LD_MISS_EXPOSED_CYC", - "BriefDescription": "Marked Load exposed Miss (use edge detect to count #)", - "PublicDescription": "" + "EventCode": "0x20114", + "EventName": "PM_MRK_L2_RC_DISP", + "BriefDescription": "Marked Instruction RC dispatched in L2" + }, + {, + "EventCode": "0x4C044", + "EventName": "PM_DATA_FROM_L31_ECO_MOD", + "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load" }, {, "EventCode": "0x1C044", "EventName": "PM_DATA_FROM_L3_NO_CONFLICT", - "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load", - "PublicDescription": "" + "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load" }, {, - "EventCode": "0x15044", - "EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT", - "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x44050", + "EventName": "PM_INST_SYS_PUMP_MPRED_RTY", + "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch" }, {, - "EventCode": "0x15046", - "EventName": "PM_IPTEG_FROM_L3.1_SHR", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x30154", + "EventName": "PM_MRK_FAB_RSP_DCLAIM", + "BriefDescription": "Marked store had to do a dclaim" }, {, - "EventCode": "0x1015E", - "EventName": "PM_MRK_FAB_RSP_RD_T_INTV", - "BriefDescription": "Sampled Read got a T intervention", - "PublicDescription": "" + "EventCode": "0x30014", + "EventName": "PM_CMPLU_STALL_STORE_FIN_ARB", + "BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe" }, {, - "EventCode": "0x14054", - "EventName": "PM_INST_PUMP_CPRED", - "BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch", - "PublicDescription": "" + "EventCode": "0x3E054", + "EventName": "PM_LD_MISS_L1", + "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load." }, {, - "EventCode": "0x15152", - "EventName": "PM_SYNC_MRK_BR_LINK", - "BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt", - "PublicDescription": "" + "EventCode": "0x400F0", + "EventName": "PM_LD_MISS_L1", + "BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load." }, {, - "EventCode": "0x1515C", - "EventName": "PM_SYNC_MRK_BR_MPRED", - "BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt", - "PublicDescription": "" + "EventCode": "0x2E01A", + "EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT", + "BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete" }, {, - "EventCode": "0x1E050", - "EventName": "PM_CMPLU_STALL_TEND", - "BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2", - "PublicDescription": "" + "EventCode": "0x2D01C", + "EventName": "PM_CMPLU_STALL_STCX", + "BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2" }, {, - "EventCode": "0x1E15E", - "EventName": "PM_MRK_L2_TM_REQ_ABORT", - "BriefDescription": "TM abort", - "PublicDescription": "" + "EventCode": "0x2C010", + "EventName": "PM_CMPLU_STALL_LSU", + "BriefDescription": "Completion stall by LSU instruction" }, {, - "EventCode": "0x1F054", - "EventName": "PM_TLB_HIT", - "BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT", - "PublicDescription": "" + "EventCode": "0x2C042", + "EventName": "PM_DATA_FROM_L3_MEPF", + "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load" }, {, - "EventCode": "0x1006A", - "EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL", - "BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it", - "PublicDescription": "" + "EventCode": "0x4E012", + "EventName": "PM_CMPLU_STALL_MTFPSCR", + "BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)" }, {, - "EventCode": "0x101E8", - "EventName": "PM_THRESH_EXC_256", - "BriefDescription": "Threshold counter exceed a count of 256", - "PublicDescription": "" + "EventCode": "0x100F2", + "EventName": "PM_1PLUS_PPC_CMPL", + "BriefDescription": "1 or more ppc insts finished" }, {, - "EventCode": "0x101EC", - "EventName": "PM_THRESH_MET", - "BriefDescription": "threshold exceeded", - "PublicDescription": "" + "EventCode": "0x3001C", + "EventName": "PM_LSU_REJECT_LMQ_FULL", + "BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)" }, {, - "EventCode": "0x100F2", - "EventName": "PM_1PLUS_PPC_CMPL", - "BriefDescription": "1 or more ppc insts finished", - "PublicDescription": "" + "EventCode": "0x15046", + "EventName": "PM_IPTEG_FROM_L31_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request" }, {, - "EventCode": "0x20114", - "EventName": "PM_MRK_L2_RC_DISP", - "BriefDescription": "Marked Instruction RC dispatched in L2", - "PublicDescription": "" + "EventCode": "0x1015E", + "EventName": "PM_MRK_FAB_RSP_RD_T_INTV", + "BriefDescription": "Sampled Read got a T intervention" }, {, - "EventCode": "0x2C010", - "EventName": "PM_CMPLU_STALL_LSU", - "BriefDescription": "Completion stall by LSU instruction", - "PublicDescription": "" + "EventCode": "0x101EC", + "EventName": "PM_THRESH_MET", + "BriefDescription": "threshold exceeded" }, {, - "EventCode": "0x2C014", - "EventName": "PM_CMPLU_STALL_STORE_FINISH", - "BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish", - "PublicDescription": "" + "EventCode": "0x10020", + "EventName": "PM_PMC4_REWIND", + "BriefDescription": "PMC4 Rewind Event" }, {, - "EventCode": "0x2C01E", - "EventName": "PM_CMPLU_STALL_SYNC_PMU_INT", - "BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt", - "PublicDescription": "" + "EventCode": "0x301EA", + "EventName": "PM_THRESH_EXC_1024", + "BriefDescription": "Threshold counter exceeded a value of 1024" }, {, - "EventCode": "0x2D01C", - "EventName": "PM_CMPLU_STALL_STCX", - "BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2", - "PublicDescription": "" + "EventCode": "0x34056", + "EventName": "PM_CMPLU_STALL_LSU_MFSPR", + "BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned" }, {, - "EventCode": "0x2E01A", - "EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT", - "BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete", - "PublicDescription": "" + "EventCode": "0x44056", + "EventName": "PM_VECTOR_ST_CMPL", + "BriefDescription": "Number of vector store instructions completed" }, {, "EventCode": "0x2C124", "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER", - "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load", - "PublicDescription": "" + "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load" }, {, - "EventCode": "0x2C042", - "EventName": "PM_DATA_FROM_L3_MEPF", - "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load", - "PublicDescription": "" - }, - {, - "EventCode": "0x2D14C", - "EventName": "PM_MRK_DATA_FROM_L3.1_ECO_SHR", - "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load", - "PublicDescription": "" + "EventCode": "0x4C12A", + "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", + "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load" }, {, - "EventCode": "0x25042", - "EventName": "PM_IPTEG_FROM_L3_MEPF", - "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x3C056", + "EventName": "PM_DTLB_MISS_64K", + "BriefDescription": "Data TLB Miss page size 64K" }, {, - "EventCode": "0x25044", - "EventName": "PM_IPTEG_FROM_L3.1_MOD", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x30060", + "EventName": "PM_TM_TRANS_RUN_INST", + "BriefDescription": "Run instructions completed in transactional state (gated by the run latch)" }, {, - "EventCode": "0x2015E", - "EventName": "PM_MRK_FAB_RSP_RWITM_RTY", - "BriefDescription": "Sampled store did a rwitm and got a rty", - "PublicDescription": "" + "EventCode": "0x2C014", + "EventName": "PM_CMPLU_STALL_STORE_FINISH", + "BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish" }, {, - "EventCode": "0x24050", - "EventName": "PM_IOPS_CMPL", - "BriefDescription": "Internal Operations completed", - "PublicDescription": "" + "EventCode": "0x3515A", + "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC", + "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load" }, {, - "EventCode": "0x24154", - "EventName": "PM_THRESH_ACC", - "BriefDescription": "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs.", - "PublicDescription": "" + "EventCode": "0x34050", + "EventName": "PM_INST_SYS_PUMP_CPRED", + "BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch" }, {, - "EventCode": "0x2F152", - "EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC", - "BriefDescription": "cycles L2 RC took for a dclaim", - "PublicDescription": "" + "EventCode": "0x3015E", + "EventName": "PM_MRK_FAB_RSP_CLAIM_RTY", + "BriefDescription": "Sampled store did a rwitm and got a rty" }, {, - "EventCode": "0x200FA", - "EventName": "PM_BR_TAKEN_CMPL", - "BriefDescription": "New event for Branch Taken", - "PublicDescription": "" + "EventCode": "0x0", + "EventName": "PM_SUSPENDED", + "BriefDescription": "Counter OFF" }, {, - "EventCode": "0x30014", - "EventName": "PM_CMPLU_STALL_STORE_FIN_ARB", - "BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe", - "PublicDescription": "" + "EventCode": "0x10010", + "EventName": "PM_PMC4_OVERFLOW", + "BriefDescription": "Overflow from counter 4" }, {, - "EventCode": "0x3001C", - "EventName": "PM_LSU_REJECT_LMQ_FULL", - "BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)", - "PublicDescription": "" + "EventCode": "0x3E04A", + "EventName": "PM_DPTEG_FROM_RMEM", + "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x30026", - "EventName": "PM_CMPLU_STALL_STORE_DATA", - "BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data", - "PublicDescription": "" + "EventCode": "0x2F152", + "EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC", + "BriefDescription": "cycles L2 RC took for a dclaim" }, {, - "EventCode": "0x3012A", - "EventName": "PM_MRK_L2_RC_DONE", - "BriefDescription": "Marked RC done", - "PublicDescription": "" + "EventCode": "0x10004", + "EventName": "PM_CMPLU_STALL_LRQ_OTHER", + "BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others" }, {, - "EventCode": "0x35044", - "EventName": "PM_IPTEG_FROM_L3.1_ECO_SHR", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x4F150", + "EventName": "PM_MRK_FAB_RSP_RWITM_CYC", + "BriefDescription": "cycles L2 RC took for a rwitm" }, {, - "EventCode": "0x3E04A", - "EventName": "PM_DPTEG_FROM_RMEM", - "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x4E042", + "EventName": "PM_DPTEG_FROM_L3", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x30154", - "EventName": "PM_MRK_FAB_RSP_DCLAIM", - "BriefDescription": "Marked store had to do a dclaim", - "PublicDescription": "" + "EventCode": "0x1F054", + "EventName": "PM_TLB_HIT", + "BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT" }, {, - "EventCode": "0x3015E", - "EventName": "PM_MRK_FAB_RSP_CLAIM_RTY", - "BriefDescription": "Sampled store did a rwitm and got a rty", - "PublicDescription": "" + "EventCode": "0x2C01E", + "EventName": "PM_CMPLU_STALL_SYNC_PMU_INT", + "BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt" }, {, - "EventCode": "0x3C056", - "EventName": "PM_DTLB_MISS_64K", - "BriefDescription": "Data TLB Miss page size 64K", - "PublicDescription": "" + "EventCode": "0x24050", + "EventName": "PM_IOPS_CMPL", + "BriefDescription": "Internal Operations completed" }, {, - "EventCode": "0x34050", - "EventName": "PM_INST_SYS_PUMP_CPRED", - "BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch", - "PublicDescription": "" + "EventCode": "0x1515C", + "EventName": "PM_SYNC_MRK_BR_MPRED", + "BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt" }, {, - "EventCode": "0x34052", - "EventName": "PM_INST_SYS_PUMP_MPRED", - "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch", - "PublicDescription": "" + "EventCode": "0x300FA", + "EventName": "PM_INST_FROM_L3MISS", + "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet" }, {, - "EventCode": "0x34056", - "EventName": "PM_CMPLU_STALL_LSU_MFSPR", - "BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned", - "PublicDescription": "" + "EventCode": "0x15044", + "EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request" }, {, - "EventCode": "0x3515A", - "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC", - "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load", - "PublicDescription": "" + "EventCode": "0x15152", + "EventName": "PM_SYNC_MRK_BR_LINK", + "BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt" }, {, - "EventCode": "0x3515C", - "EventName": "PM_MRK_DATA_FROM_RL4", - "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load", - "PublicDescription": "" + "EventCode": "0x1E050", + "EventName": "PM_CMPLU_STALL_TEND", + "BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2" }, {, - "EventCode": "0x3E15C", - "EventName": "PM_MRK_L2_TM_ST_ABORT_SISTER", - "BriefDescription": "TM marked store abort for this thread", - "PublicDescription": "" + "EventCode": "0x1013E", + "EventName": "PM_MRK_LD_MISS_EXPOSED_CYC", + "BriefDescription": "Marked Load exposed Miss (use edge detect to count #)" }, {, - "EventCode": "0x30060", - "EventName": "PM_TM_TRANS_RUN_INST", - "BriefDescription": "Run instructions completed in transactional state (gated by the run latch)", - "PublicDescription": "" + "EventCode": "0x25042", + "EventName": "PM_IPTEG_FROM_L3_MEPF", + "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request" }, {, - "EventCode": "0x301E6", - "EventName": "PM_MRK_DERAT_MISS", - "BriefDescription": "Erat Miss (TLB Access) All page sizes", - "PublicDescription": "" + "EventCode": "0x14054", + "EventName": "PM_INST_PUMP_CPRED", + "BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch" }, {, - "EventCode": "0x301EA", - "EventName": "PM_THRESH_EXC_1024", - "BriefDescription": "Threshold counter exceeded a value of 1024", - "PublicDescription": "" + "EventCode": "0x4015E", + "EventName": "PM_MRK_FAB_RSP_RD_RTY", + "BriefDescription": "Sampled L2 reads retry count" }, {, - "EventCode": "0x300FA", - "EventName": "PM_INST_FROM_L3MISS", - "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet", - "PublicDescription": "" + "EventCode": "0x45048", + "EventName": "PM_IPTEG_FROM_DL2L3_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request" }, {, - "EventCode": "0x40116", - "EventName": "PM_MRK_LARX_FIN", - "BriefDescription": "Larx finished", - "PublicDescription": "" + "EventCode": "0x44052", + "EventName": "PM_INST_PUMP_MPRED", + "BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch" }, {, - "EventCode": "0x4C010", - "EventName": "PM_CMPLU_STALL_STORE_PIPE_ARB", - "BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration", - "PublicDescription": "" + "EventCode": "0x30026", + "EventName": "PM_CMPLU_STALL_STORE_DATA", + "BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data" }, {, - "EventCode": "0x4C01C", - "EventName": "PM_CMPLU_STALL_ST_FWD", - "BriefDescription": "Completion stall due to store forward", - "PublicDescription": "" + "EventCode": "0x301E6", + "EventName": "PM_MRK_DERAT_MISS", + "BriefDescription": "Erat Miss (TLB Access) All page sizes" }, {, - "EventCode": "0x4E012", - "EventName": "PM_CMPLU_STALL_MTFPSCR", - "BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)", - "PublicDescription": "" + "EventCode": "0x24154", + "EventName": "PM_THRESH_ACC", + "BriefDescription": "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs." }, {, - "EventCode": "0x4E016", - "EventName": "PM_CMPLU_STALL_LSAQ_ARB", - "BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch", - "PublicDescription": "" + "EventCode": "0x2015E", + "EventName": "PM_MRK_FAB_RSP_RWITM_RTY", + "BriefDescription": "Sampled store did a rwitm and got a rty" }, {, - "EventCode": "0x4C12A", - "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC", - "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load", - "PublicDescription": "" + "EventCode": "0x200FA", + "EventName": "PM_BR_TAKEN_CMPL", + "BriefDescription": "New event for Branch Taken" }, {, - "EventCode": "0x4C044", - "EventName": "PM_DATA_FROM_L3.1_ECO_MOD", - "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load", - "PublicDescription": "" + "EventCode": "0x35044", + "EventName": "PM_IPTEG_FROM_L31_ECO_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request" }, {, - "EventCode": "0x45044", - "EventName": "PM_IPTEG_FROM_L3.1_ECO_MOD", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x4C010", + "EventName": "PM_CMPLU_STALL_STORE_PIPE_ARB", + "BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration" }, {, - "EventCode": "0x45048", - "EventName": "PM_IPTEG_FROM_DL2L3_MOD", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x4C01C", + "EventName": "PM_CMPLU_STALL_ST_FWD", + "BriefDescription": "Completion stall due to store forward" }, {, - "EventCode": "0x4504E", - "EventName": "PM_IPTEG_FROM_L3MISS", - "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x3515C", + "EventName": "PM_MRK_DATA_FROM_RL4", + "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load" }, {, - "EventCode": "0x4E042", - "EventName": "PM_DPTEG_FROM_L3", - "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x2D14C", + "EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR", + "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load" }, {, - "EventCode": "0x4015E", - "EventName": "PM_MRK_FAB_RSP_RD_RTY", - "BriefDescription": "Sampled L2 reads retry count", - "PublicDescription": "" + "EventCode": "0x40116", + "EventName": "PM_MRK_LARX_FIN", + "BriefDescription": "Larx finished" }, {, "EventCode": "0x4C056", "EventName": "PM_DTLB_MISS_16M", - "BriefDescription": "Data TLB Miss page size 16M", - "PublicDescription": "" - }, - {, - "EventCode": "0x44050", - "EventName": "PM_INST_SYS_PUMP_MPRED_RTY", - "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch", - "PublicDescription": "" + "BriefDescription": "Data TLB Miss page size 16M" }, {, - "EventCode": "0x44052", - "EventName": "PM_INST_PUMP_MPRED", - "BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch", - "PublicDescription": "" + "EventCode": "0x1003A", + "EventName": "PM_CMPLU_STALL_LSU_FIN", + "BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish" }, {, - "EventCode": "0x44056", - "EventName": "PM_VECTOR_ST_CMPL", - "BriefDescription": "Number of vector store instructions completed", - "PublicDescription": "" + "EventCode": "0x3012A", + "EventName": "PM_MRK_L2_RC_DONE", + "BriefDescription": "Marked RC done" }, {, - "EventCode": "0x4F150", - "EventName": "PM_MRK_FAB_RSP_RWITM_CYC", - "BriefDescription": "cycles L2 RC took for a rwitm", - "PublicDescription": "" + "EventCode": "0x45044", + "EventName": "PM_IPTEG_FROM_L31_ECO_MOD", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request" } -] +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/powerpc/power9/marked.json b/tools/perf/pmu-events/arch/powerpc/power9/marked.json index e4d673235830..b9df54fb37e3 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/marked.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/marked.json @@ -1,782 +1,647 @@ [ {, - "EventCode": "0x1002C", - "EventName": "PM_L1_DCACHE_RELOADED_ALL", - "BriefDescription": "L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well", - "PublicDescription": "" - }, - {, - "EventCode": "0x10132", - "EventName": "PM_MRK_INST_ISSUED", - "BriefDescription": "Marked instruction issued", - "PublicDescription": "" + "EventCode": "0x3C052", + "EventName": "PM_DATA_SYS_PUMP_MPRED", + "BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load" }, {, - "EventCode": "0x1C042", - "EventName": "PM_DATA_FROM_L2", - "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load", - "PublicDescription": "" + "EventCode": "0x3013E", + "EventName": "PM_MRK_STALL_CMPLU_CYC", + "BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)" }, {, - "EventCode": "0x1C046", - "EventName": "PM_DATA_FROM_L3.1_SHR", - "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load", - "PublicDescription": "" + "EventCode": "0x4F056", + "EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3MISS", + "BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache" }, {, - "EventCode": "0x1C048", - "EventName": "PM_DATA_FROM_ON_CHIP_CACHE", - "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load", - "PublicDescription": "" + "EventCode": "0x24158", + "EventName": "PM_MRK_INST", + "BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens" }, {, - "EventCode": "0x14040", - "EventName": "PM_INST_FROM_L2_NO_CONFLICT", - "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x1E046", + "EventName": "PM_DPTEG_FROM_L31_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x14042", - "EventName": "PM_INST_FROM_L2", - "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x3C04A", + "EventName": "PM_DATA_FROM_RMEM", + "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load" }, {, - "EventCode": "0x14046", - "EventName": "PM_INST_FROM_L3.1_SHR", - "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x2C01C", + "EventName": "PM_CMPLU_STALL_DMISS_REMOTE", + "BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)" }, {, - "EventCode": "0x1404C", - "EventName": "PM_INST_FROM_LL4", - "BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)", - "PublicDescription": "" + "EventCode": "0x44040", + "EventName": "PM_INST_FROM_L2_DISP_CONFLICT_OTHER", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x1D14C", - "EventName": "PM_MRK_DATA_FROM_LL4", - "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load", - "PublicDescription": "" + "EventCode": "0x2E050", + "EventName": "PM_DARQ0_7_9_ENTRIES", + "BriefDescription": "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use" }, {, - "EventCode": "0x15042", - "EventName": "PM_IPTEG_FROM_L2", - "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x2D02E", + "EventName": "PM_RADIX_PWC_L3_PTE_FROM_L2", + "BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation" }, {, - "EventCode": "0x1504E", - "EventName": "PM_IPTEG_FROM_L2MISS", - "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request", - "PublicDescription": "" + "EventCode": "0x3F05E", + "EventName": "PM_RADIX_PWC_L3_PTE_FROM_L3", + "BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation" }, {, - "EventCode": "0x1E042", - "EventName": "PM_DPTEG_FROM_L2", - "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x2E01E", + "EventName": "PM_CMPLU_STALL_NTC_FLUSH", + "BriefDescription": "Completion stall due to ntc flush" }, {, - "EventCode": "0x1E044", - "EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT", - "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x1F14C", + "EventName": "PM_MRK_DPTEG_FROM_LL4", + "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x1E046", - "EventName": "PM_DPTEG_FROM_L3.1_SHR", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x20130", + "EventName": "PM_MRK_INST_DECODED", + "BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only" }, {, - "EventCode": "0x1F14A", - "EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR", - "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x3F144", + "EventName": "PM_MRK_DPTEG_FROM_L31_ECO_SHR", + "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" }, {, - "EventCode": "0x1F14C", - "EventName": "PM_MRK_DPTEG_FROM_LL4", - "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included", - "PublicDescription": "" + "EventCode": "0x4D058", + "EventName": "PM_VECTOR_FLOP_CMPL", + "BriefDescription": "Vector FP instruction completed" }, {, - "EventCode": "0x1005C", - "EventName": "PM_CMPLU_STALL_DP", - "BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector", - "PublicDescription": "" + "EventCode": "0x14040", + "EventName": "PM_INST_FROM_L2_NO_CONFLICT", + "BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)" }, {, - "EventCode": "0x1C052", - "EventName": "PM_DATA_GRP_PUMP_MPRED_RTY", - "BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load", - "PublicDescription": "" + "EventCode": "0x4404E", + "EventName": "PM_INST_FROM_L3MISS_MOD", + "BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a i