From 6f14293257309a02a6d451e80e4ef1d78560479e Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 11 Oct 2024 15:34:08 +0200 Subject: MIPS: Allow using more than 32-bit addresses for reset vectors when possible While most MIPS64 CPUs use 32-bit values for their VP Local Reset Exception Base registers, some I6500 CPUs can utilize a 64-bit value, allowing addressing up to 47 bits of physical memory. For the EyeQ6H CPU, where physical memory addresses exceed the 4GB limit, utilizing this feature is mandatory to enable SMP support. Unfortunately, there is no way to detect this capability based solely on the ID of the CPU. According to Imagination, which designed the CPU, the only reliable method is to fill the reset base field with 0xFF and then read back its value. If the upper part of the read-back value is zero, it indicates that the address space is limited to 32 bits. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Bogendoerfer --- arch/mips/include/asm/mips-cm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/mips/include/asm/mips-cm.h') diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 1e782275850a..23ce951f445b 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -326,7 +326,9 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) +GCR_CX_ACCESSOR_RW(64, 0x020, reset64_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET64_BASE_BEVEXCBASE GENMASK_ULL(47, 12) #define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ -- cgit v1.2.3