From f15cbe6f1a4b4d9df59142fc8e4abb973302cf44 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Tue, 29 Jul 2008 08:09:44 +0900 Subject: sh: migrate to arch/sh/include/ This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg Signed-off-by: Paul Mundt --- arch/sh/include/asm/.gitignore | 1 + arch/sh/include/asm/Kbuild | 8 + arch/sh/include/asm/a.out.h | 20 + arch/sh/include/asm/adc.h | 13 + arch/sh/include/asm/addrspace.h | 53 +++ arch/sh/include/asm/atomic-grb.h | 169 ++++++++ arch/sh/include/asm/atomic-irq.h | 71 +++ arch/sh/include/asm/atomic-llsc.h | 107 +++++ arch/sh/include/asm/atomic.h | 89 ++++ arch/sh/include/asm/auxvec.h | 36 ++ arch/sh/include/asm/bitops-grb.h | 169 ++++++++ arch/sh/include/asm/bitops-irq.h | 91 ++++ arch/sh/include/asm/bitops.h | 103 +++++ arch/sh/include/asm/bug.h | 79 ++++ arch/sh/include/asm/bugs.h | 73 ++++ arch/sh/include/asm/byteorder.h | 70 +++ arch/sh/include/asm/cache.h | 51 +++ arch/sh/include/asm/cacheflush.h | 81 ++++ arch/sh/include/asm/checksum.h | 5 + arch/sh/include/asm/checksum_32.h | 215 +++++++++ arch/sh/include/asm/checksum_64.h | 78 ++++ arch/sh/include/asm/clock.h | 97 +++++ arch/sh/include/asm/cmpxchg-grb.h | 70 +++ arch/sh/include/asm/cmpxchg-irq.h | 40 ++ arch/sh/include/asm/cpu-features.h | 25 ++ arch/sh/include/asm/cputime.h | 6 + arch/sh/include/asm/current.h | 20 + arch/sh/include/asm/delay.h | 26 ++ arch/sh/include/asm/device.h | 12 + arch/sh/include/asm/div64.h | 1 + arch/sh/include/asm/dma-mapping.h | 192 +++++++++ arch/sh/include/asm/dma.h | 166 +++++++ arch/sh/include/asm/dmabrg.h | 23 + arch/sh/include/asm/edosk7705.h | 30 ++ arch/sh/include/asm/elf.h | 244 +++++++++++ arch/sh/include/asm/emergency-restart.h | 6 + arch/sh/include/asm/entry-macros.S | 33 ++ arch/sh/include/asm/errno.h | 6 + arch/sh/include/asm/fb.h | 19 + arch/sh/include/asm/fcntl.h | 1 + arch/sh/include/asm/fixmap.h | 117 +++++ arch/sh/include/asm/flat.h | 24 ++ arch/sh/include/asm/fpu.h | 55 +++ arch/sh/include/asm/freq.h | 18 + arch/sh/include/asm/futex-irq.h | 111 +++++ arch/sh/include/asm/futex.h | 77 ++++ arch/sh/include/asm/gpio.h | 19 + arch/sh/include/asm/hardirq.h | 16 + arch/sh/include/asm/hd64461.h | 250 +++++++++++ arch/sh/include/asm/hd64465/gpio.h | 46 ++ arch/sh/include/asm/hd64465/hd64465.h | 256 +++++++++++ arch/sh/include/asm/hd64465/io.h | 44 ++ arch/sh/include/asm/heartbeat.h | 17 + arch/sh/include/asm/hp6xx.h | 58 +++ arch/sh/include/asm/hugetlb.h | 92 ++++ arch/sh/include/asm/hw_irq.h | 123 ++++++ arch/sh/include/asm/i2c-sh7760.h | 22 + arch/sh/include/asm/ilsel.h | 45 ++ arch/sh/include/asm/io.h | 366 ++++++++++++++++ arch/sh/include/asm/io_generic.h | 49 +++ arch/sh/include/asm/io_trapped.h | 58 +++ arch/sh/include/asm/ioctl.h | 1 + arch/sh/include/asm/ioctls.h | 103 +++++ arch/sh/include/asm/ipcbuf.h | 29 ++ arch/sh/include/asm/irq.h | 57 +++ arch/sh/include/asm/irq_regs.h | 1 + arch/sh/include/asm/irqflags.h | 34 ++ arch/sh/include/asm/irqflags_32.h | 99 +++++ arch/sh/include/asm/irqflags_64.h | 85 ++++ arch/sh/include/asm/kdebug.h | 9 + arch/sh/include/asm/kexec.h | 62 +++ arch/sh/include/asm/kgdb.h | 69 +++ arch/sh/include/asm/kmap_types.h | 32 ++ arch/sh/include/asm/lboxre2.h | 27 ++ arch/sh/include/asm/linkage.h | 7 + arch/sh/include/asm/local.h | 7 + arch/sh/include/asm/machvec.h | 70 +++ arch/sh/include/asm/magicpanelr2.h | 67 +++ arch/sh/include/asm/mc146818rtc.h | 7 + arch/sh/include/asm/microdev.h | 80 ++++ arch/sh/include/asm/migor.h | 65 +++ arch/sh/include/asm/mman.h | 17 + arch/sh/include/asm/mmu.h | 76 ++++ arch/sh/include/asm/mmu_context.h | 185 ++++++++ arch/sh/include/asm/mmu_context_32.h | 47 ++ arch/sh/include/asm/mmu_context_64.h | 78 ++++ arch/sh/include/asm/mmzone.h | 48 +++ arch/sh/include/asm/module.h | 44 ++ arch/sh/include/asm/msgbuf.h | 31 ++ arch/sh/include/asm/mutex.h | 9 + arch/sh/include/asm/page.h | 183 ++++++++ arch/sh/include/asm/param.h | 22 + arch/sh/include/asm/parport.h | 16 + arch/sh/include/asm/pci.h | 144 +++++++ arch/sh/include/asm/percpu.h | 6 + arch/sh/include/asm/pgalloc.h | 96 +++++ arch/sh/include/asm/pgtable.h | 152 +++++++ arch/sh/include/asm/pgtable_32.h | 479 +++++++++++++++++++++ arch/sh/include/asm/pgtable_64.h | 314 ++++++++++++++ arch/sh/include/asm/pm.h | 17 + arch/sh/include/asm/poll.h | 1 + arch/sh/include/asm/posix_types.h | 13 + arch/sh/include/asm/posix_types_32.h | 122 ++++++ arch/sh/include/asm/posix_types_64.h | 131 ++++++ arch/sh/include/asm/processor.h | 66 +++ arch/sh/include/asm/processor_32.h | 216 ++++++++++ arch/sh/include/asm/processor_64.h | 275 ++++++++++++ arch/sh/include/asm/ptrace.h | 130 ++++++ arch/sh/include/asm/push-switch.h | 31 ++ arch/sh/include/asm/r7780rp.h | 198 +++++++++ arch/sh/include/asm/resource.h | 6 + arch/sh/include/asm/rtc.h | 16 + arch/sh/include/asm/rts7751r2d.h | 70 +++ arch/sh/include/asm/rwsem.h | 188 ++++++++ arch/sh/include/asm/scatterlist.h | 27 ++ arch/sh/include/asm/sdk7780.h | 81 ++++ arch/sh/include/asm/se.h | 99 +++++ arch/sh/include/asm/se7206.h | 13 + arch/sh/include/asm/se7343.h | 149 +++++++ arch/sh/include/asm/se7721.h | 70 +++ arch/sh/include/asm/se7722.h | 112 +++++ arch/sh/include/asm/se7751.h | 73 ++++ arch/sh/include/asm/se7780.h | 108 +++++ arch/sh/include/asm/sections.h | 11 + arch/sh/include/asm/segment.h | 34 ++ arch/sh/include/asm/sembuf.h | 25 ++ arch/sh/include/asm/serial.h | 36 ++ arch/sh/include/asm/setup.h | 27 ++ arch/sh/include/asm/sfp-machine.h | 84 ++++ arch/sh/include/asm/sh7760fb.h | 197 +++++++++ arch/sh/include/asm/sh7763rdp.h | 54 +++ arch/sh/include/asm/sh7785lcr.h | 55 +++ arch/sh/include/asm/sh_bios.h | 19 + arch/sh/include/asm/sh_keysc.h | 13 + arch/sh/include/asm/sh_mobile_lcdc.h | 66 +++ arch/sh/include/asm/shmbuf.h | 42 ++ arch/sh/include/asm/shmin.h | 9 + arch/sh/include/asm/shmparam.h | 22 + arch/sh/include/asm/sigcontext.h | 40 ++ arch/sh/include/asm/siginfo.h | 6 + arch/sh/include/asm/signal.h | 160 +++++++ arch/sh/include/asm/smc37c93x.h | 190 ++++++++ arch/sh/include/asm/smp.h | 50 +++ arch/sh/include/asm/snapgear.h | 71 +++ arch/sh/include/asm/socket.h | 57 +++ arch/sh/include/asm/sockios.h | 14 + arch/sh/include/asm/sparsemem.h | 16 + arch/sh/include/asm/spi.h | 13 + arch/sh/include/asm/spinlock.h | 223 ++++++++++ arch/sh/include/asm/spinlock_types.h | 21 + arch/sh/include/asm/stat.h | 138 ++++++ arch/sh/include/asm/statfs.h | 6 + arch/sh/include/asm/string.h | 5 + arch/sh/include/asm/string_32.h | 131 ++++++ arch/sh/include/asm/string_64.h | 17 + arch/sh/include/asm/system.h | 190 ++++++++ arch/sh/include/asm/system_32.h | 102 +++++ arch/sh/include/asm/system_64.h | 40 ++ arch/sh/include/asm/systemh7751.h | 71 +++ arch/sh/include/asm/termbits.h | 198 +++++++++ arch/sh/include/asm/termios.h | 90 ++++ arch/sh/include/asm/thread_info.h | 141 ++++++ arch/sh/include/asm/timer.h | 44 ++ arch/sh/include/asm/timex.h | 18 + arch/sh/include/asm/titan.h | 17 + arch/sh/include/asm/tlb.h | 27 ++ arch/sh/include/asm/tlb_64.h | 77 ++++ arch/sh/include/asm/tlbflush.h | 49 +++ arch/sh/include/asm/topology.h | 47 ++ arch/sh/include/asm/types.h | 35 ++ arch/sh/include/asm/uaccess.h | 256 +++++++++++ arch/sh/include/asm/uaccess_32.h | 249 +++++++++++ arch/sh/include/asm/uaccess_64.h | 79 ++++ arch/sh/include/asm/ubc.h | 64 +++ arch/sh/include/asm/ucontext.h | 12 + arch/sh/include/asm/unaligned.h | 19 + arch/sh/include/asm/unistd.h | 13 + arch/sh/include/asm/unistd_32.h | 384 +++++++++++++++++ arch/sh/include/asm/unistd_64.h | 423 ++++++++++++++++++ arch/sh/include/asm/user.h | 67 +++ arch/sh/include/asm/vga.h | 6 + arch/sh/include/asm/watchdog.h | 107 +++++ arch/sh/include/asm/xor.h | 1 + arch/sh/include/cpu-sh2/cpu/addrspace.h | 19 + arch/sh/include/cpu-sh2/cpu/cache.h | 41 ++ arch/sh/include/cpu-sh2/cpu/cacheflush.h | 44 ++ arch/sh/include/cpu-sh2/cpu/dma.h | 23 + arch/sh/include/cpu-sh2/cpu/freq.h | 18 + arch/sh/include/cpu-sh2/cpu/mmu_context.h | 16 + arch/sh/include/cpu-sh2/cpu/rtc.h | 8 + arch/sh/include/cpu-sh2/cpu/sigcontext.h | 17 + arch/sh/include/cpu-sh2/cpu/timer.h | 6 + arch/sh/include/cpu-sh2/cpu/ubc.h | 32 ++ arch/sh/include/cpu-sh2/cpu/watchdog.h | 69 +++ arch/sh/include/cpu-sh2a/cpu/addrspace.h | 10 + arch/sh/include/cpu-sh2a/cpu/cache.h | 40 ++ arch/sh/include/cpu-sh2a/cpu/cacheflush.h | 44 ++ arch/sh/include/cpu-sh2a/cpu/dma.h | 23 + arch/sh/include/cpu-sh2a/cpu/freq.h | 16 + arch/sh/include/cpu-sh2a/cpu/mmu_context.h | 16 + arch/sh/include/cpu-sh2a/cpu/rtc.h | 8 + arch/sh/include/cpu-sh2a/cpu/timer.h | 6 + arch/sh/include/cpu-sh2a/cpu/ubc.h | 32 ++ arch/sh/include/cpu-sh2a/cpu/watchdog.h | 69 +++ arch/sh/include/cpu-sh3/cpu/adc.h | 28 ++ arch/sh/include/cpu-sh3/cpu/addrspace.h | 19 + arch/sh/include/cpu-sh3/cpu/cache.h | 43 ++ arch/sh/include/cpu-sh3/cpu/cacheflush.h | 70 +++ arch/sh/include/cpu-sh3/cpu/dac.h | 41 ++ arch/sh/include/cpu-sh3/cpu/dma.h | 51 +++ arch/sh/include/cpu-sh3/cpu/freq.h | 27 ++ arch/sh/include/cpu-sh3/cpu/gpio.h | 67 +++ arch/sh/include/cpu-sh3/cpu/mmu_context.h | 44 ++ arch/sh/include/cpu-sh3/cpu/rtc.h | 8 + arch/sh/include/cpu-sh3/cpu/sigcontext.h | 17 + arch/sh/include/cpu-sh3/cpu/timer.h | 67 +++ arch/sh/include/cpu-sh3/cpu/ubc.h | 42 ++ arch/sh/include/cpu-sh3/cpu/watchdog.h | 25 ++ arch/sh/include/cpu-sh4/cpu/addrspace.h | 35 ++ arch/sh/include/cpu-sh4/cpu/cache.h | 42 ++ arch/sh/include/cpu-sh4/cpu/cacheflush.h | 43 ++ arch/sh/include/cpu-sh4/cpu/dma-sh7780.h | 39 ++ arch/sh/include/cpu-sh4/cpu/dma.h | 65 +++ arch/sh/include/cpu-sh4/cpu/fpu.h | 32 ++ arch/sh/include/cpu-sh4/cpu/freq.h | 44 ++ arch/sh/include/cpu-sh4/cpu/mmu_context.h | 63 +++ arch/sh/include/cpu-sh4/cpu/rtc.h | 13 + arch/sh/include/cpu-sh4/cpu/sigcontext.h | 24 ++ arch/sh/include/cpu-sh4/cpu/sq.h | 35 ++ arch/sh/include/cpu-sh4/cpu/timer.h | 60 +++ arch/sh/include/cpu-sh4/cpu/ubc.h | 64 +++ arch/sh/include/cpu-sh4/cpu/watchdog.h | 25 ++ arch/sh/include/cpu-sh5/cpu/addrspace.h | 11 + arch/sh/include/cpu-sh5/cpu/cache.h | 97 +++++ arch/sh/include/cpu-sh5/cpu/cacheflush.h | 33 ++ arch/sh/include/cpu-sh5/cpu/dma.h | 6 + arch/sh/include/cpu-sh5/cpu/irq.h | 117 +++++ arch/sh/include/cpu-sh5/cpu/mmu_context.h | 21 + arch/sh/include/cpu-sh5/cpu/registers.h | 106 +++++ arch/sh/include/cpu-sh5/cpu/rtc.h | 8 + arch/sh/include/cpu-sh5/cpu/timer.h | 4 + arch/sh/include/mach-dreamcast/mach/dma.h | 34 ++ arch/sh/include/mach-dreamcast/mach/maple.h | 37 ++ arch/sh/include/mach-dreamcast/mach/pci.h | 25 ++ arch/sh/include/mach-dreamcast/mach/sysasic.h | 43 ++ arch/sh/include/mach-landisk/mach/gio.h | 37 ++ arch/sh/include/mach-landisk/mach/iodata_landisk.h | 42 ++ arch/sh/include/mach-sh03/mach/io.h | 25 ++ arch/sh/include/mach-sh03/mach/sh03.h | 18 + 249 files changed, 16564 insertions(+) create mode 100644 arch/sh/include/asm/.gitignore create mode 100644 arch/sh/include/asm/Kbuild create mode 100644 arch/sh/include/asm/a.out.h create mode 100644 arch/sh/include/asm/adc.h create mode 100644 arch/sh/include/asm/addrspace.h create mode 100644 arch/sh/include/asm/atomic-grb.h create mode 100644 arch/sh/include/asm/atomic-irq.h create mode 100644 arch/sh/include/asm/atomic-llsc.h create mode 100644 arch/sh/include/asm/atomic.h create mode 100644 arch/sh/include/asm/auxvec.h create mode 100644 arch/sh/include/asm/bitops-grb.h create mode 100644 arch/sh/include/asm/bitops-irq.h create mode 100644 arch/sh/include/asm/bitops.h create mode 100644 arch/sh/include/asm/bug.h create mode 100644 arch/sh/include/asm/bugs.h create mode 100644 arch/sh/include/asm/byteorder.h create mode 100644 arch/sh/include/asm/cache.h create mode 100644 arch/sh/include/asm/cacheflush.h create mode 100644 arch/sh/include/asm/checksum.h create mode 100644 arch/sh/include/asm/checksum_32.h create mode 100644 arch/sh/include/asm/checksum_64.h create mode 100644 arch/sh/include/asm/clock.h create mode 100644 arch/sh/include/asm/cmpxchg-grb.h create mode 100644 arch/sh/include/asm/cmpxchg-irq.h create mode 100644 arch/sh/include/asm/cpu-features.h create mode 100644 arch/sh/include/asm/cputime.h create mode 100644 arch/sh/include/asm/current.h create mode 100644 arch/sh/include/asm/delay.h create mode 100644 arch/sh/include/asm/device.h create mode 100644 arch/sh/include/asm/div64.h create mode 100644 arch/sh/include/asm/dma-mapping.h create mode 100644 arch/sh/include/asm/dma.h create mode 100644 arch/sh/include/asm/dmabrg.h create mode 100644 arch/sh/include/asm/edosk7705.h create mode 100644 arch/sh/include/asm/elf.h create mode 100644 arch/sh/include/asm/emergency-restart.h create mode 100644 arch/sh/include/asm/entry-macros.S create mode 100644 arch/sh/include/asm/errno.h create mode 100644 arch/sh/include/asm/fb.h create mode 100644 arch/sh/include/asm/fcntl.h create mode 100644 arch/sh/include/asm/fixmap.h create mode 100644 arch/sh/include/asm/flat.h create mode 100644 arch/sh/include/asm/fpu.h create mode 100644 arch/sh/include/asm/freq.h create mode 100644 arch/sh/include/asm/futex-irq.h create mode 100644 arch/sh/include/asm/futex.h create mode 100644 arch/sh/include/asm/gpio.h create mode 100644 arch/sh/include/asm/hardirq.h create mode 100644 arch/sh/include/asm/hd64461.h create mode 100644 arch/sh/include/asm/hd64465/gpio.h create mode 100644 arch/sh/include/asm/hd64465/hd64465.h create mode 100644 arch/sh/include/asm/hd64465/io.h create mode 100644 arch/sh/include/asm/heartbeat.h create mode 100644 arch/sh/include/asm/hp6xx.h create mode 100644 arch/sh/include/asm/hugetlb.h create mode 100644 arch/sh/include/asm/hw_irq.h create mode 100644 arch/sh/include/asm/i2c-sh7760.h create mode 100644 arch/sh/include/asm/ilsel.h create mode 100644 arch/sh/include/asm/io.h create mode 100644 arch/sh/include/asm/io_generic.h create mode 100644 arch/sh/include/asm/io_trapped.h create mode 100644 arch/sh/include/asm/ioctl.h create mode 100644 arch/sh/include/asm/ioctls.h create mode 100644 arch/sh/include/asm/ipcbuf.h create mode 100644 arch/sh/include/asm/irq.h create mode 100644 arch/sh/include/asm/irq_regs.h create mode 100644 arch/sh/include/asm/irqflags.h create mode 100644 arch/sh/include/asm/irqflags_32.h create mode 100644 arch/sh/include/asm/irqflags_64.h create mode 100644 arch/sh/include/asm/kdebug.h create mode 100644 arch/sh/include/asm/kexec.h create mode 100644 arch/sh/include/asm/kgdb.h create mode 100644 arch/sh/include/asm/kmap_types.h create mode 100644 arch/sh/include/asm/lboxre2.h create mode 100644 arch/sh/include/asm/linkage.h create mode 100644 arch/sh/include/asm/local.h create mode 100644 arch/sh/include/asm/machvec.h create mode 100644 arch/sh/include/asm/magicpanelr2.h create mode 100644 arch/sh/include/asm/mc146818rtc.h create mode 100644 arch/sh/include/asm/microdev.h create mode 100644 arch/sh/include/asm/migor.h create mode 100644 arch/sh/include/asm/mman.h create mode 100644 arch/sh/include/asm/mmu.h create mode 100644 arch/sh/include/asm/mmu_context.h create mode 100644 arch/sh/include/asm/mmu_context_32.h create mode 100644 arch/sh/include/asm/mmu_context_64.h create mode 100644 arch/sh/include/asm/mmzone.h create mode 100644 arch/sh/include/asm/module.h create mode 100644 arch/sh/include/asm/msgbuf.h create mode 100644 arch/sh/include/asm/mutex.h create mode 100644 arch/sh/include/asm/page.h create mode 100644 arch/sh/include/asm/param.h create mode 100644 arch/sh/include/asm/parport.h create mode 100644 arch/sh/include/asm/pci.h create mode 100644 arch/sh/include/asm/percpu.h create mode 100644 arch/sh/include/asm/pgalloc.h create mode 100644 arch/sh/include/asm/pgtable.h create mode 100644 arch/sh/include/asm/pgtable_32.h create mode 100644 arch/sh/include/asm/pgtable_64.h create mode 100644 arch/sh/include/asm/pm.h create mode 100644 arch/sh/include/asm/poll.h create mode 100644 arch/sh/include/asm/posix_types.h create mode 100644 arch/sh/include/asm/posix_types_32.h create mode 100644 arch/sh/include/asm/posix_types_64.h create mode 100644 arch/sh/include/asm/processor.h create mode 100644 arch/sh/include/asm/processor_32.h create mode 100644 arch/sh/include/asm/processor_64.h create mode 100644 arch/sh/include/asm/ptrace.h create mode 100644 arch/sh/include/asm/push-switch.h create mode 100644 arch/sh/include/asm/r7780rp.h create mode 100644 arch/sh/include/asm/resource.h create mode 100644 arch/sh/include/asm/rtc.h create mode 100644 arch/sh/include/asm/rts7751r2d.h create mode 100644 arch/sh/include/asm/rwsem.h create mode 100644 arch/sh/include/asm/scatterlist.h create mode 100644 arch/sh/include/asm/sdk7780.h create mode 100644 arch/sh/include/asm/se.h create mode 100644 arch/sh/include/asm/se7206.h create mode 100644 arch/sh/include/asm/se7343.h create mode 100644 arch/sh/include/asm/se7721.h create mode 100644 arch/sh/include/asm/se7722.h create mode 100644 arch/sh/include/asm/se7751.h create mode 100644 arch/sh/include/asm/se7780.h create mode 100644 arch/sh/include/asm/sections.h create mode 100644 arch/sh/include/asm/segment.h create mode 100644 arch/sh/include/asm/sembuf.h create mode 100644 arch/sh/include/asm/serial.h create mode 100644 arch/sh/include/asm/setup.h create mode 100644 arch/sh/include/asm/sfp-machine.h create mode 100644 arch/sh/include/asm/sh7760fb.h create mode 100644 arch/sh/include/asm/sh7763rdp.h create mode 100644 arch/sh/include/asm/sh7785lcr.h create mode 100644 arch/sh/include/asm/sh_bios.h create mode 100644 arch/sh/include/asm/sh_keysc.h create mode 100644 arch/sh/include/asm/sh_mobile_lcdc.h create mode 100644 arch/sh/include/asm/shmbuf.h create mode 100644 arch/sh/include/asm/shmin.h create mode 100644 arch/sh/include/asm/shmparam.h create mode 100644 arch/sh/include/asm/sigcontext.h create mode 100644 arch/sh/include/asm/siginfo.h create mode 100644 arch/sh/include/asm/signal.h create mode 100644 arch/sh/include/asm/smc37c93x.h create mode 100644 arch/sh/include/asm/smp.h create mode 100644 arch/sh/include/asm/snapgear.h create mode 100644 arch/sh/include/asm/socket.h create mode 100644 arch/sh/include/asm/sockios.h create mode 100644 arch/sh/include/asm/sparsemem.h create mode 100644 arch/sh/include/asm/spi.h create mode 100644 arch/sh/include/asm/spinlock.h create mode 100644 arch/sh/include/asm/spinlock_types.h create mode 100644 arch/sh/include/asm/stat.h create mode 100644 arch/sh/include/asm/statfs.h create mode 100644 arch/sh/include/asm/string.h create mode 100644 arch/sh/include/asm/string_32.h create mode 100644 arch/sh/include/asm/string_64.h create mode 100644 arch/sh/include/asm/system.h create mode 100644 arch/sh/include/asm/system_32.h create mode 100644 arch/sh/include/asm/system_64.h create mode 100644 arch/sh/include/asm/systemh7751.h create mode 100644 arch/sh/include/asm/termbits.h create mode 100644 arch/sh/include/asm/termios.h create mode 100644 arch/sh/include/asm/thread_info.h create mode 100644 arch/sh/include/asm/timer.h create mode 100644 arch/sh/include/asm/timex.h create mode 100644 arch/sh/include/asm/titan.h create mode 100644 arch/sh/include/asm/tlb.h create mode 100644 arch/sh/include/asm/tlb_64.h create mode 100644 arch/sh/include/asm/tlbflush.h create mode 100644 arch/sh/include/asm/topology.h create mode 100644 arch/sh/include/asm/types.h create mode 100644 arch/sh/include/asm/uaccess.h create mode 100644 arch/sh/include/asm/uaccess_32.h create mode 100644 arch/sh/include/asm/uaccess_64.h create mode 100644 arch/sh/include/asm/ubc.h create mode 100644 arch/sh/include/asm/ucontext.h create mode 100644 arch/sh/include/asm/unaligned.h create mode 100644 arch/sh/include/asm/unistd.h create mode 100644 arch/sh/include/asm/unistd_32.h create mode 100644 arch/sh/include/asm/unistd_64.h create mode 100644 arch/sh/include/asm/user.h create mode 100644 arch/sh/include/asm/vga.h create mode 100644 arch/sh/include/asm/watchdog.h create mode 100644 arch/sh/include/asm/xor.h create mode 100644 arch/sh/include/cpu-sh2/cpu/addrspace.h create mode 100644 arch/sh/include/cpu-sh2/cpu/cache.h create mode 100644 arch/sh/include/cpu-sh2/cpu/cacheflush.h create mode 100644 arch/sh/include/cpu-sh2/cpu/dma.h create mode 100644 arch/sh/include/cpu-sh2/cpu/freq.h create mode 100644 arch/sh/include/cpu-sh2/cpu/mmu_context.h create mode 100644 arch/sh/include/cpu-sh2/cpu/rtc.h create mode 100644 arch/sh/include/cpu-sh2/cpu/sigcontext.h create mode 100644 arch/sh/include/cpu-sh2/cpu/timer.h create mode 100644 arch/sh/include/cpu-sh2/cpu/ubc.h create mode 100644 arch/sh/include/cpu-sh2/cpu/watchdog.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/addrspace.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/cache.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/cacheflush.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/dma.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/freq.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/mmu_context.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/rtc.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/timer.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/ubc.h create mode 100644 arch/sh/include/cpu-sh2a/cpu/watchdog.h create mode 100644 arch/sh/include/cpu-sh3/cpu/adc.h create mode 100644 arch/sh/include/cpu-sh3/cpu/addrspace.h create mode 100644 arch/sh/include/cpu-sh3/cpu/cache.h create mode 100644 arch/sh/include/cpu-sh3/cpu/cacheflush.h create mode 100644 arch/sh/include/cpu-sh3/cpu/dac.h create mode 100644 arch/sh/include/cpu-sh3/cpu/dma.h create mode 100644 arch/sh/include/cpu-sh3/cpu/freq.h create mode 100644 arch/sh/include/cpu-sh3/cpu/gpio.h create mode 100644 arch/sh/include/cpu-sh3/cpu/mmu_context.h create mode 100644 arch/sh/include/cpu-sh3/cpu/rtc.h create mode 100644 arch/sh/include/cpu-sh3/cpu/sigcontext.h create mode 100644 arch/sh/include/cpu-sh3/cpu/timer.h create mode 100644 arch/sh/include/cpu-sh3/cpu/ubc.h create mode 100644 arch/sh/include/cpu-sh3/cpu/watchdog.h create mode 100644 arch/sh/include/cpu-sh4/cpu/addrspace.h create mode 100644 arch/sh/include/cpu-sh4/cpu/cache.h create mode 100644 arch/sh/include/cpu-sh4/cpu/cacheflush.h create mode 100644 arch/sh/include/cpu-sh4/cpu/dma-sh7780.h create mode 100644 arch/sh/include/cpu-sh4/cpu/dma.h create mode 100644 arch/sh/include/cpu-sh4/cpu/fpu.h create mode 100644 arch/sh/include/cpu-sh4/cpu/freq.h create mode 100644 arch/sh/include/cpu-sh4/cpu/mmu_context.h create mode 100644 arch/sh/include/cpu-sh4/cpu/rtc.h create mode 100644 arch/sh/include/cpu-sh4/cpu/sigcontext.h create mode 100644 arch/sh/include/cpu-sh4/cpu/sq.h create mode 100644 arch/sh/include/cpu-sh4/cpu/timer.h create mode 100644 arch/sh/include/cpu-sh4/cpu/ubc.h create mode 100644 arch/sh/include/cpu-sh4/cpu/watchdog.h create mode 100644 arch/sh/include/cpu-sh5/cpu/addrspace.h create mode 100644 arch/sh/include/cpu-sh5/cpu/cache.h create mode 100644 arch/sh/include/cpu-sh5/cpu/cacheflush.h create mode 100644 arch/sh/include/cpu-sh5/cpu/dma.h create mode 100644 arch/sh/include/cpu-sh5/cpu/irq.h create mode 100644 arch/sh/include/cpu-sh5/cpu/mmu_context.h create mode 100644 arch/sh/include/cpu-sh5/cpu/registers.h create mode 100644 arch/sh/include/cpu-sh5/cpu/rtc.h create mode 100644 arch/sh/include/cpu-sh5/cpu/timer.h create mode 100644 arch/sh/include/mach-dreamcast/mach/dma.h create mode 100644 arch/sh/include/mach-dreamcast/mach/maple.h create mode 100644 arch/sh/include/mach-dreamcast/mach/pci.h create mode 100644 arch/sh/include/mach-dreamcast/mach/sysasic.h create mode 100644 arch/sh/include/mach-landisk/mach/gio.h create mode 100644 arch/sh/include/mach-landisk/mach/iodata_landisk.h create mode 100644 arch/sh/include/mach-sh03/mach/io.h create mode 100644 arch/sh/include/mach-sh03/mach/sh03.h (limited to 'arch/sh/include') diff --git a/arch/sh/include/asm/.gitignore b/arch/sh/include/asm/.gitignore new file mode 100644 index 000000000000..378db779fb6c --- /dev/null +++ b/arch/sh/include/asm/.gitignore @@ -0,0 +1 @@ +machtypes.h diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild new file mode 100644 index 000000000000..43910cdf78a5 --- /dev/null +++ b/arch/sh/include/asm/Kbuild @@ -0,0 +1,8 @@ +include include/asm-generic/Kbuild.asm + +header-y += cpu-features.h + +unifdef-y += unistd_32.h +unifdef-y += unistd_64.h +unifdef-y += posix_types_32.h +unifdef-y += posix_types_64.h diff --git a/arch/sh/include/asm/a.out.h b/arch/sh/include/asm/a.out.h new file mode 100644 index 000000000000..1f93130e179c --- /dev/null +++ b/arch/sh/include/asm/a.out.h @@ -0,0 +1,20 @@ +#ifndef __ASM_SH_A_OUT_H +#define __ASM_SH_A_OUT_H + +struct exec +{ + unsigned long a_info; /* Use macros N_MAGIC, etc for access */ + unsigned a_text; /* length of text, in bytes */ + unsigned a_data; /* length of data, in bytes */ + unsigned a_bss; /* length of uninitialized data area for file, in bytes */ + unsigned a_syms; /* length of symbol table data in file, in bytes */ + unsigned a_entry; /* start address */ + unsigned a_trsize; /* length of relocation info for text, in bytes */ + unsigned a_drsize; /* length of relocation info for data, in bytes */ +}; + +#define N_TRSIZE(a) ((a).a_trsize) +#define N_DRSIZE(a) ((a).a_drsize) +#define N_SYMSIZE(a) ((a).a_syms) + +#endif /* __ASM_SH_A_OUT_H */ diff --git a/arch/sh/include/asm/adc.h b/arch/sh/include/asm/adc.h new file mode 100644 index 000000000000..48824c1fab80 --- /dev/null +++ b/arch/sh/include/asm/adc.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ADC_H +#define __ASM_ADC_H +#ifdef __KERNEL__ +/* + * Copyright (C) 2004 Andriy Skulysh + */ + +#include + +int adc_single(unsigned int channel); + +#endif /* __KERNEL__ */ +#endif /* __ASM_ADC_H */ diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h new file mode 100644 index 000000000000..2702d81bfc0d --- /dev/null +++ b/arch/sh/include/asm/addrspace.h @@ -0,0 +1,53 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 by Kaz Kojima + * + * Defitions for the address spaces of the SH CPUs. + */ +#ifndef __ASM_SH_ADDRSPACE_H +#define __ASM_SH_ADDRSPACE_H + +#ifdef __KERNEL__ + +#include + +/* If this CPU supports segmentation, hook up the helpers */ +#ifdef P1SEG + +/* + [ P0/U0 (virtual) ] 0x00000000 <------ User space + [ P1 (fixed) cached ] 0x80000000 <------ Kernel space + [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access + [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area + [ P4 control ] 0xE0000000 + */ + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +#ifdef CONFIG_29BIT +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) \ + ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) \ + ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) \ + ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) \ + ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) +#endif /* 29BIT */ +#endif /* P1SEG */ + +/* Check if an address can be reached in 29 bits */ +#define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000) + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_ADDRSPACE_H */ diff --git a/arch/sh/include/asm/atomic-grb.h b/arch/sh/include/asm/atomic-grb.h new file mode 100644 index 000000000000..4c5b7dbfcedb --- /dev/null +++ b/arch/sh/include/asm/atomic-grb.h @@ -0,0 +1,169 @@ +#ifndef __ASM_SH_ATOMIC_GRB_H +#define __ASM_SH_ATOMIC_GRB_H + +static inline void atomic_add(int i, atomic_t *v) +{ + int tmp; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " add %2, %0 \n\t" /* add */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (v) + : "r" (i) + : "memory" , "r0", "r1"); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + int tmp; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " sub %2, %0 \n\t" /* sub */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (v) + : "r" (i) + : "memory" , "r0", "r1"); +} + +static inline int atomic_add_return(int i, atomic_t *v) +{ + int tmp; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " add %2, %0 \n\t" /* add */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (v) + : "r" (i) + : "memory" , "r0", "r1"); + + return tmp; +} + +static inline int atomic_sub_return(int i, atomic_t *v) +{ + int tmp; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " sub %2, %0 \n\t" /* sub */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (v) + : "r" (i) + : "memory", "r0", "r1"); + + return tmp; +} + +static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) +{ + int tmp; + unsigned int _mask = ~mask; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " and %2, %0 \n\t" /* add */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (v) + : "r" (_mask) + : "memory" , "r0", "r1"); +} + +static inline void atomic_set_mask(unsigned int mask, atomic_t *v) +{ + int tmp; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " or %2, %0 \n\t" /* or */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (v) + : "r" (mask) + : "memory" , "r0", "r1"); +} + +static inline int atomic_cmpxchg(atomic_t *v, int old, int new) +{ + int ret; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" + " nop \n\t" + " mov r15, r1 \n\t" + " mov #-8, r15 \n\t" + " mov.l @%1, %0 \n\t" + " cmp/eq %2, %0 \n\t" + " bf 1f \n\t" + " mov.l %3, @%1 \n\t" + "1: mov r1, r15 \n\t" + : "=&r" (ret) + : "r" (v), "r" (old), "r" (new) + : "memory" , "r0", "r1" , "t"); + + return ret; +} + +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int ret; + unsigned long tmp; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" + " nop \n\t" + " mov r15, r1 \n\t" + " mov #-12, r15 \n\t" + " mov.l @%2, %1 \n\t" + " mov %1, %0 \n\t" + " cmp/eq %4, %0 \n\t" + " bt/s 1f \n\t" + " add %3, %1 \n\t" + " mov.l %1, @%2 \n\t" + "1: mov r1, r15 \n\t" + : "=&r" (ret), "=&r" (tmp) + : "r" (v), "r" (a), "r" (u) + : "memory" , "r0", "r1" , "t"); + + return ret != u; +} +#endif /* __ASM_SH_ATOMIC_GRB_H */ diff --git a/arch/sh/include/asm/atomic-irq.h b/arch/sh/include/asm/atomic-irq.h new file mode 100644 index 000000000000..74f7943cff6f --- /dev/null +++ b/arch/sh/include/asm/atomic-irq.h @@ -0,0 +1,71 @@ +#ifndef __ASM_SH_ATOMIC_IRQ_H +#define __ASM_SH_ATOMIC_IRQ_H + +/* + * To get proper branch prediction for the main line, we must branch + * forward to code at the end of this object's .text section, then + * branch back to restart the operation. + */ +static inline void atomic_add(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + *(long *)v += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + *(long *)v -= i; + local_irq_restore(flags); +} + +static inline int atomic_add_return(int i, atomic_t *v) +{ + unsigned long temp, flags; + + local_irq_save(flags); + temp = *(long *)v; + temp += i; + *(long *)v = temp; + local_irq_restore(flags); + + return temp; +} + +static inline int atomic_sub_return(int i, atomic_t *v) +{ + unsigned long temp, flags; + + local_irq_save(flags); + temp = *(long *)v; + temp -= i; + *(long *)v = temp; + local_irq_restore(flags); + + return temp; +} + +static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + *(long *)v &= ~mask; + local_irq_restore(flags); +} + +static inline void atomic_set_mask(unsigned int mask, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + *(long *)v |= mask; + local_irq_restore(flags); +} + +#endif /* __ASM_SH_ATOMIC_IRQ_H */ diff --git a/arch/sh/include/asm/atomic-llsc.h b/arch/sh/include/asm/atomic-llsc.h new file mode 100644 index 000000000000..4b00b78e3f4f --- /dev/null +++ b/arch/sh/include/asm/atomic-llsc.h @@ -0,0 +1,107 @@ +#ifndef __ASM_SH_ATOMIC_LLSC_H +#define __ASM_SH_ATOMIC_LLSC_H + +/* + * To get proper branch prediction for the main line, we must branch + * forward to code at the end of this object's .text section, then + * branch back to restart the operation. + */ +static inline void atomic_add(int i, atomic_t *v) +{ + unsigned long tmp; + + __asm__ __volatile__ ( +"1: movli.l @%2, %0 ! atomic_add \n" +" add %1, %0 \n" +" movco.l %0, @%2 \n" +" bf 1b \n" + : "=&z" (tmp) + : "r" (i), "r" (&v->counter) + : "t"); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + unsigned long tmp; + + __asm__ __volatile__ ( +"1: movli.l @%2, %0 ! atomic_sub \n" +" sub %1, %0 \n" +" movco.l %0, @%2 \n" +" bf 1b \n" + : "=&z" (tmp) + : "r" (i), "r" (&v->counter) + : "t"); +} + +/* + * SH-4A note: + * + * We basically get atomic_xxx_return() for free compared with + * atomic_xxx(). movli.l/movco.l require r0 due to the instruction + * encoding, so the retval is automatically set without having to + * do any special work. + */ +static inline int atomic_add_return(int i, atomic_t *v) +{ + unsigned long temp; + + __asm__ __volatile__ ( +"1: movli.l @%2, %0 ! atomic_add_return \n" +" add %1, %0 \n" +" movco.l %0, @%2 \n" +" bf 1b \n" +" synco \n" + : "=&z" (temp) + : "r" (i), "r" (&v->counter) + : "t"); + + return temp; +} + +static inline int atomic_sub_return(int i, atomic_t *v) +{ + unsigned long temp; + + __asm__ __volatile__ ( +"1: movli.l @%2, %0 ! atomic_sub_return \n" +" sub %1, %0 \n" +" movco.l %0, @%2 \n" +" bf 1b \n" +" synco \n" + : "=&z" (temp) + : "r" (i), "r" (&v->counter) + : "t"); + + return temp; +} + +static inline void atomic_clear_mask(unsigned int mask, atomic_t *v) +{ + unsigned long tmp; + + __asm__ __volatile__ ( +"1: movli.l @%2, %0 ! atomic_clear_mask \n" +" and %1, %0 \n" +" movco.l %0, @%2 \n" +" bf 1b \n" + : "=&z" (tmp) + : "r" (~mask), "r" (&v->counter) + : "t"); +} + +static inline void atomic_set_mask(unsigned int mask, atomic_t *v) +{ + unsigned long tmp; + + __asm__ __volatile__ ( +"1: movli.l @%2, %0 ! atomic_set_mask \n" +" or %1, %0 \n" +" movco.l %0, @%2 \n" +" bf 1b \n" + : "=&z" (tmp) + : "r" (mask), "r" (&v->counter) + : "t"); +} + +#endif /* __ASM_SH_ATOMIC_LLSC_H */ diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h new file mode 100644 index 000000000000..c043ef003028 --- /dev/null +++ b/arch/sh/include/asm/atomic.h @@ -0,0 +1,89 @@ +#ifndef __ASM_SH_ATOMIC_H +#define __ASM_SH_ATOMIC_H + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + * + */ + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) ( (atomic_t) { (i) } ) + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v,i) ((v)->counter = (i)) + +#include +#include + +#if defined(CONFIG_GUSA_RB) +#include +#elif defined(CONFIG_CPU_SH4A) +#include +#else +#include +#endif + +#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) + +#define atomic_dec_return(v) atomic_sub_return(1,(v)) +#define atomic_inc_return(v) atomic_add_return(1,(v)) + +/* + * atomic_inc_and_test - increment and test + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1 + * and returns true if the result is zero, or false for all + * other cases. + */ +#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) + +#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) +#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) + +#define atomic_inc(v) atomic_add(1,(v)) +#define atomic_dec(v) atomic_sub(1,(v)) + +#ifndef CONFIG_GUSA_RB +static inline int atomic_cmpxchg(atomic_t *v, int old, int new) +{ + int ret; + unsigned long flags; + + local_irq_save(flags); + ret = v->counter; + if (likely(ret == old)) + v->counter = new; + local_irq_restore(flags); + + return ret; +} + +static inline int atomic_add_unless(atomic_t *v, int a, int u) +{ + int ret; + unsigned long flags; + + local_irq_save(flags); + ret = v->counter; + if (ret != u) + v->counter += a; + local_irq_restore(flags); + + return ret != u; +} +#endif + +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) +#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) + +/* Atomic operations are already serializing on SH */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#include +#endif /* __ASM_SH_ATOMIC_H */ diff --git a/arch/sh/include/asm/auxvec.h b/arch/sh/include/asm/auxvec.h new file mode 100644 index 000000000000..a6b9d4f4859e --- /dev/null +++ b/arch/sh/include/asm/auxvec.h @@ -0,0 +1,36 @@ +#ifndef __ASM_SH_AUXVEC_H +#define __ASM_SH_AUXVEC_H + +/* + * Architecture-neutral AT_ values in 0-17, leave some room + * for more of them. + */ + +/* + * This entry gives some information about the FPU initialization + * performed by the kernel. + */ +#define AT_FPUCW 18 /* Used FPU control word. */ + +#ifdef CONFIG_VSYSCALL +/* + * Only define this in the vsyscall case, the entry point to + * the vsyscall page gets placed here. The kernel will attempt + * to build a gate VMA we don't care about otherwise.. + */ +#define AT_SYSINFO_EHDR 33 +#endif + +/* + * More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the + * value is -1, then the cache doesn't exist. Otherwise: + * + * bit 0-3: Cache set-associativity; 0 means fully associative. + * bit 4-7: Log2 of cacheline size. + * bit 8-31: Size of the entire cache >> 8. + */ +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 + +#endif /* __ASM_SH_AUXVEC_H */ diff --git a/arch/sh/include/asm/bitops-grb.h b/arch/sh/include/asm/bitops-grb.h new file mode 100644 index 000000000000..a5907b94395b --- /dev/null +++ b/arch/sh/include/asm/bitops-grb.h @@ -0,0 +1,169 @@ +#ifndef __ASM_SH_BITOPS_GRB_H +#define __ASM_SH_BITOPS_GRB_H + +static inline void set_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long tmp; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " or %2, %0 \n\t" /* or */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (a) + : "r" (mask) + : "memory" , "r0", "r1"); +} + +static inline void clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long tmp; + + a += nr >> 5; + mask = ~(1 << (nr & 0x1f)); + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " and %2, %0 \n\t" /* and */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (a) + : "r" (mask) + : "memory" , "r0", "r1"); +} + +static inline void change_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long tmp; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-6, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%1, %0 \n\t" /* load old value */ + " xor %2, %0 \n\t" /* xor */ + " mov.l %0, @%1 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "+r" (a) + : "r" (mask) + : "memory" , "r0", "r1"); +} + +static inline int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long tmp; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-14, r15 \n\t" /* LOGIN: r15 = size */ + " mov.l @%2, %0 \n\t" /* load old value */ + " mov %0, %1 \n\t" + " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ + " mov #-1, %1 \n\t" /* retvat = -1 */ + " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ + " or %3, %0 \n\t" + " mov.l %0, @%2 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "=&r" (retval), + "+r" (a) + : "r" (mask) + : "memory" , "r0", "r1" ,"t"); + + return retval; +} + +static inline int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval,not_mask; + volatile unsigned int *a = addr; + unsigned long tmp; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + + not_mask = ~mask; + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-14, r15 \n\t" /* LOGIN */ + " mov.l @%2, %0 \n\t" /* load old value */ + " mov %0, %1 \n\t" /* %1 = *a */ + " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ + " mov #-1, %1 \n\t" /* retvat = -1 */ + " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ + " and %4, %0 \n\t" + " mov.l %0, @%2 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "=&r" (retval), + "+r" (a) + : "r" (mask), + "r" (not_mask) + : "memory" , "r0", "r1", "t"); + + return retval; +} + +static inline int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long tmp; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + + __asm__ __volatile__ ( + " .align 2 \n\t" + " mova 1f, r0 \n\t" /* r0 = end point */ + " mov r15, r1 \n\t" /* r1 = saved sp */ + " mov #-14, r15 \n\t" /* LOGIN */ + " mov.l @%2, %0 \n\t" /* load old value */ + " mov %0, %1 \n\t" /* %1 = *a */ + " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ + " mov #-1, %1 \n\t" /* retvat = -1 */ + " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ + " xor %3, %0 \n\t" + " mov.l %0, @%2 \n\t" /* store new value */ + "1: mov r1, r15 \n\t" /* LOGOUT */ + : "=&r" (tmp), + "=&r" (retval), + "+r" (a) + : "r" (mask) + : "memory" , "r0", "r1", "t"); + + return retval; +} +#endif /* __ASM_SH_BITOPS_GRB_H */ diff --git a/arch/sh/include/asm/bitops-irq.h b/arch/sh/include/asm/bitops-irq.h new file mode 100644 index 000000000000..653a12750584 --- /dev/null +++ b/arch/sh/include/asm/bitops-irq.h @@ -0,0 +1,91 @@ +#ifndef __ASM_SH_BITOPS_IRQ_H +#define __ASM_SH_BITOPS_IRQ_H + +static inline void set_bit(int nr, volatile void *addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a |= mask; + local_irq_restore(flags); +} + +static inline void clear_bit(int nr, volatile void *addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a &= ~mask; + local_irq_restore(flags); +} + +static inline void change_bit(int nr, volatile void *addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a ^= mask; + local_irq_restore(flags); +} + +static inline int test_and_set_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a |= mask; + local_irq_restore(flags); + + return retval; +} + +static inline int test_and_clear_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + local_irq_restore(flags); + + return retval; +} + +static inline int test_and_change_bit(int nr, volatile void *addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a ^= mask; + local_irq_restore(flags); + + return retval; +} + +#endif /* __ASM_SH_BITOPS_IRQ_H */ diff --git a/arch/sh/include/asm/bitops.h b/arch/sh/include/asm/bitops.h new file mode 100644 index 000000000000..d7d382f63ee5 --- /dev/null +++ b/arch/sh/include/asm/bitops.h @@ -0,0 +1,103 @@ +#ifndef __ASM_SH_BITOPS_H +#define __ASM_SH_BITOPS_H + +#ifdef __KERNEL__ + +#ifndef _LINUX_BITOPS_H +#error only can be included directly +#endif + +#include +/* For __swab32 */ +#include + +#ifdef CONFIG_GUSA_RB +#include +#else +#include +#endif + + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +#include + +#ifdef CONFIG_SUPERH32 +static inline unsigned long ffz(unsigned long word) +{ + unsigned long result; + + __asm__("1:\n\t" + "shlr %1\n\t" + "bt/s 1b\n\t" + " add #1, %0" + : "=r" (result), "=r" (word) + : "0" (~0L), "1" (word) + : "t"); + return result; +} + +/** + * __ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static inline unsigned long __ffs(unsigned long word) +{ + unsigned long result; + + __asm__("1:\n\t" + "shlr %1\n\t" + "bf/s 1b\n\t" + " add #1, %0" + : "=r" (result), "=r" (word) + : "0" (~0L), "1" (word) + : "t"); + return result; +} +#else +static inline unsigned long ffz(unsigned long word) +{ + unsigned long result, __d2, __d3; + + __asm__("gettr tr0, %2\n\t" + "pta $+32, tr0\n\t" + "andi %1, 1, %3\n\t" + "beq %3, r63, tr0\n\t" + "pta $+4, tr0\n" + "0:\n\t" + "shlri.l %1, 1, %1\n\t" + "addi %0, 1, %0\n\t" + "andi %1, 1, %3\n\t" + "beqi %3, 1, tr0\n" + "1:\n\t" + "ptabs %2, tr0\n\t" + : "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3) + : "0" (0L), "1" (word)); + + return result; +} + +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_BITOPS_H */ diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h new file mode 100644 index 000000000000..c01718040166 --- /dev/null +++ b/arch/sh/include/asm/bug.h @@ -0,0 +1,79 @@ +#ifndef __ASM_SH_BUG_H +#define __ASM_SH_BUG_H + +#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */ + +#ifdef CONFIG_GENERIC_BUG +#define HAVE_ARCH_BUG +#define HAVE_ARCH_WARN_ON + +/** + * _EMIT_BUG_ENTRY + * %1 - __FILE__ + * %2 - __LINE__ + * %3 - trap type + * %4 - sizeof(struct bug_entry) + * + * The trapa opcode itself sits in %0. + * The %O notation is used to avoid # generation. + * + * The offending file and line are encoded in the __bug_table section. + */ +#ifdef CONFIG_DEBUG_BUGVERBOSE +#define _EMIT_BUG_ENTRY \ + "\t.pushsection __bug_table,\"a\"\n" \ + "2:\t.long 1b, %O1\n" \ + "\t.short %O2, %O3\n" \ + "\t.org 2b+%O4\n" \ + "\t.popsection\n" +#else +#define _EMIT_BUG_ENTRY \ + "\t.pushsection __bug_table,\"a\"\n" \ + "2:\t.long 1b\n" \ + "\t.short %O3\n" \ + "\t.org 2b+%O4\n" \ + "\t.popsection\n" +#endif + +#define BUG() \ +do { \ + __asm__ __volatile__ ( \ + "1:\t.short %O0\n" \ + _EMIT_BUG_ENTRY \ + : \ + : "n" (TRAPA_BUG_OPCODE), \ + "i" (__FILE__), \ + "i" (__LINE__), "i" (0), \ + "i" (sizeof(struct bug_entry))); \ +} while (0) + +#define __WARN() \ +do { \ + __asm__ __volatile__ ( \ + "1:\t.short %O0\n" \ + _EMIT_BUG_ENTRY \ + : \ + : "n" (TRAPA_BUG_OPCODE), \ + "i" (__FILE__), \ + "i" (__LINE__), \ + "i" (BUGFLAG_WARNING), \ + "i" (sizeof(struct bug_entry))); \ +} while (0) + +#define WARN_ON(x) ({ \ + int __ret_warn_on = !!(x); \ + if (__builtin_constant_p(__ret_warn_on)) { \ + if (__ret_warn_on) \ + __WARN(); \ + } else { \ + if (unlikely(__ret_warn_on)) \ + __WARN(); \ + } \ + unlikely(__ret_warn_on); \ +}) + +#endif /* CONFIG_GENERIC_BUG */ + +#include + +#endif /* __ASM_SH_BUG_H */ diff --git a/arch/sh/include/asm/bugs.h b/arch/sh/include/asm/bugs.h new file mode 100644 index 000000000000..121b2ecddfc3 --- /dev/null +++ b/arch/sh/include/asm/bugs.h @@ -0,0 +1,73 @@ +#ifndef __ASM_SH_BUGS_H +#define __ASM_SH_BUGS_H + +/* + * This is included by init/main.c to check for architecture-dependent bugs. + * + * Needs: + * void check_bugs(void); + */ + +/* + * I don't know of any Super-H bugs yet. + */ + +#include + +static void __init check_bugs(void) +{ + extern unsigned long loops_per_jiffy; + char *p = &init_utsname()->machine[2]; /* "sh" */ + + current_cpu_data.loops_per_jiffy = loops_per_jiffy; + + switch (current_cpu_data.type) { + case CPU_SH7619: + *p++ = '2'; + break; + case CPU_SH7203 ... CPU_MXG: + *p++ = '2'; + *p++ = 'a'; + break; + case CPU_SH7705 ... CPU_SH7729: + *p++ = '3'; + break; + case CPU_SH7750 ... CPU_SH4_501: + *p++ = '4'; + break; + case CPU_SH7763 ... CPU_SHX3: + *p++ = '4'; + *p++ = 'a'; + break; + case CPU_SH7343 ... CPU_SH7366: + *p++ = '4'; + *p++ = 'a'; + *p++ = 'l'; + *p++ = '-'; + *p++ = 'd'; + *p++ = 's'; + *p++ = 'p'; + break; + case CPU_SH5_101 ... CPU_SH5_103: + *p++ = '6'; + *p++ = '4'; + break; + case CPU_SH_NONE: + /* + * Specifically use CPU_SH_NONE rather than default:, + * so we're able to have the compiler whine about + * unhandled enumerations. + */ + break; + } + + printk("CPU: %s\n", get_cpu_subtype(¤t_cpu_data)); + +#ifndef __LITTLE_ENDIAN__ + /* 'eb' means 'Endian Big' */ + *p++ = 'e'; + *p++ = 'b'; +#endif + *p = '\0'; +} +#endif /* __ASM_SH_BUGS_H */ diff --git a/arch/sh/include/asm/byteorder.h b/arch/sh/include/asm/byteorder.h new file mode 100644 index 000000000000..4c13e6117563 --- /dev/null +++ b/arch/sh/include/asm/byteorder.h @@ -0,0 +1,70 @@ +#ifndef __ASM_SH_BYTEORDER_H +#define __ASM_SH_BYTEORDER_H + +/* + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2000, 2001 Paolo Alberelli + */ +#include +#include + +static inline __attribute_const__ __u32 ___arch__swab32(__u32 x) +{ + __asm__( +#ifdef __SH5__ + "byterev %0, %0\n\t" + "shari %0, 32, %0" +#else + "swap.b %0, %0\n\t" + "swap.w %0, %0\n\t" + "swap.b %0, %0" +#endif + : "=r" (x) + : "0" (x)); + + return x; +} + +static inline __attribute_const__ __u16 ___arch__swab16(__u16 x) +{ + __asm__( +#ifdef __SH5__ + "byterev %0, %0\n\t" + "shari %0, 32, %0" +#else + "swap.b %0, %0" +#endif + : "=r" (x) + : "0" (x)); + + return x; +} + +static inline __u64 ___arch__swab64(__u64 val) +{ + union { + struct { __u32 a,b; } s; + __u64 u; + } v, w; + v.u = val; + w.s.b = ___arch__swab32(v.s.a); + w.s.a = ___arch__swab32(v.s.b); + return w.u; +} + +#define __arch__swab64(x) ___arch__swab64(x) +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __LITTLE_ENDIAN__ +#include +#else +#include +#endif + +#endif /* __ASM_SH_BYTEORDER_H */ diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h new file mode 100644 index 000000000000..02df18ea9608 --- /dev/null +++ b/arch/sh/include/asm/cache.h @@ -0,0 +1,51 @@ +/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $ + * + * include/asm-sh/cache.h + * + * Copyright 1999 (C) Niibe Yutaka + * Copyright 2002, 2003 (C) Paul Mundt + */ +#ifndef __ASM_SH_CACHE_H +#define __ASM_SH_CACHE_H +#ifdef __KERNEL__ + +#include +#include + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#define __read_mostly __attribute__((__section__(".data.read_mostly"))) + +#ifndef __ASSEMBLY__ +struct cache_info { + unsigned int ways; /* Number of cache ways */ + unsigned int sets; /* Number of cache sets */ + unsigned int linesz; /* Cache line size (bytes) */ + + unsigned int way_size; /* sets * line size */ + + /* + * way_incr is the address offset for accessing the next way + * in memory mapped cache array ops. + */ + unsigned int way_incr; + unsigned int entry_shift; + unsigned int entry_mask; + + /* + * Compute a mask which selects the address bits which overlap between + * 1. those used to select the cache set during indexing + * 2. those in the physical page number. + */ + unsigned int alias_mask; + + unsigned int n_aliases; /* Number of aliases */ + + unsigned long flags; +}; + +int __init detect_cpu_and_cache_system(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_CACHE_H */ diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h new file mode 100644 index 000000000000..09acbc32d6c7 --- /dev/null +++ b/arch/sh/include/asm/cacheflush.h @@ -0,0 +1,81 @@ +#ifndef __ASM_SH_CACHEFLUSH_H +#define __ASM_SH_CACHEFLUSH_H + +#ifdef __KERNEL__ + +#ifdef CONFIG_CACHE_OFF +/* + * Nothing to do when the cache is disabled, initial flush and explicit + * disabling is handled at CPU init time. + * + * See arch/sh/kernel/cpu/init.c:cache_init(). + */ +#define p3_cache_init() do { } while (0) +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_dup_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) +#define flush_dcache_page(page) do { } while (0) +#define flush_icache_range(start, end) do { } while (0) +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_cache_sigtramp(vaddr) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) +#define __flush_wback_region(start, size) do { (void)(start); } while (0) +#define __flush_purge_region(start, size) do { (void)(start); } while (0) +#define __flush_invalidate_region(start, size) do { (void)(start); } while (0) +#else +#include + +/* + * Consistent DMA requires that the __flush_xxx() primitives must be set + * for any of the enabled non-coherent caches (most of the UP CPUs), + * regardless of PIPT or VI