From 7536ad8dbfcfd56cd04d005b76cd9ecf2036e220 Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Tue, 14 Apr 2020 15:47:54 -0500 Subject: firmware: fpga: replace the error codes with the standard ones MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Intel service layer driver has defined error codes for the specific services, which started from FPGA configuration then RSU (Remote Status Update). Intel service layer driver should define the standard error codes rather than keep adding more error codes for the new services. The standard error codes will be used by all the clients of Intel service layer driver. Replace FPGA and RSU specific error codes with Intel service layer’s Common error codes. Signed-off-by: Richard Gong Link: https://lore.kernel.org/r/1586897274-307-2-git-send-email-richard.gong@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/fpga/stratix10-soc.c | 25 ++++++++++--------------- 1 file changed, 10 insertions(+), 15 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index 215d33789c74..bae98c8ce362 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -154,11 +154,11 @@ static void s10_receive_callback(struct stratix10_svc_client *client, * Here we set status bits as we receive them. Elsewhere, we always use * test_and_clear_bit() to check status in priv->status */ - for (i = 0; i <= SVC_STATUS_RECONFIG_ERROR; i++) + for (i = 0; i <= SVC_STATUS_ERROR; i++) if (status & (1 << i)) set_bit(i, &priv->status); - if (status & BIT(SVC_STATUS_RECONFIG_BUFFER_DONE)) { + if (status & BIT(SVC_STATUS_BUFFER_DONE)) { s10_unlock_bufs(priv, data->kaddr1); s10_unlock_bufs(priv, data->kaddr2); s10_unlock_bufs(priv, data->kaddr3); @@ -209,8 +209,7 @@ static int s10_ops_write_init(struct fpga_manager *mgr, } ret = 0; - if (!test_and_clear_bit(SVC_STATUS_RECONFIG_REQUEST_OK, - &priv->status)) { + if (!test_and_clear_bit(SVC_STATUS_OK, &priv->status)) { ret = -ETIMEDOUT; goto init_done; } @@ -323,17 +322,15 @@ static int s10_ops_write(struct fpga_manager *mgr, const char *buf, &priv->status_return_completion, S10_BUFFER_TIMEOUT); - if (test_and_clear_bit(SVC_STATUS_RECONFIG_BUFFER_DONE, - &priv->status) || - test_and_clear_bit(SVC_STATUS_RECONFIG_BUFFER_SUBMITTED, + if (test_and_clear_bit(SVC_STATUS_BUFFER_DONE, &priv->status) || + test_and_clear_bit(SVC_STATUS_BUFFER_SUBMITTED, &priv->status)) { ret = 0; continue; } - if (test_and_clear_bit(SVC_STATUS_RECONFIG_ERROR, - &priv->status)) { - dev_err(dev, "ERROR - giving up - SVC_STATUS_RECONFIG_ERROR\n"); + if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) { + dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n"); ret = -EFAULT; break; } @@ -393,13 +390,11 @@ static int s10_ops_write_complete(struct fpga_manager *mgr, timeout = ret; ret = 0; - if (test_and_clear_bit(SVC_STATUS_RECONFIG_COMPLETED, - &priv->status)) + if (test_and_clear_bit(SVC_STATUS_COMPLETED, &priv->status)) break; - if (test_and_clear_bit(SVC_STATUS_RECONFIG_ERROR, - &priv->status)) { - dev_err(dev, "ERROR - giving up - SVC_STATUS_RECONFIG_ERROR\n"); + if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) { + dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n"); ret = -EFAULT; break; } -- cgit v1.2.3 From 4db8180ffe7c07bc4a602c82d6d9c1c04751583d Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Fri, 24 Apr 2020 13:58:02 -0700 Subject: firmware: xilinx: Remove eemi ops for fpga related APIs Use direct function call instead of using eemi ops for fpga related APIs. Also remove eemi ops structure. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Link: https://lore.kernel.org/r/1587761887-4279-21-git-send-email-jolly.shah@xilinx.com Signed-off-by: Greg Kroah-Hartman --- drivers/fpga/zynqmp-fpga.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index b8a88d21d038..4a1139e05280 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -40,16 +40,12 @@ static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr, static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, const char *buf, size_t size) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); struct zynqmp_fpga_priv *priv; dma_addr_t dma_addr; u32 eemi_flags = 0; char *kbuf; int ret; - if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_load) - return -ENXIO; - priv = mgr->priv; kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); @@ -63,7 +59,7 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG) eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL; - ret = eemi_ops->fpga_load(dma_addr, size, eemi_flags); + ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags); dma_free_coherent(priv->dev, size, kbuf, dma_addr); @@ -78,13 +74,9 @@ static int zynqmp_fpga_ops_write_complete(struct fpga_manager *mgr, static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr) { - const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); - u32 status; - - if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_get_status) - return FPGA_MGR_STATE_UNKNOWN; + u32 status = 0; - eemi_ops->fpga_get_status(&status); + zynqmp_pm_fpga_get_status(&status); if (status & IXR_FPGA_DONE_MASK) return FPGA_MGR_STATE_OPERATING; -- cgit v1.2.3 From 724142f8c42a7b01dbf9738eb00d7addbad6f862 Mon Sep 17 00:00:00 2001 From: Wu Hao Date: Mon, 27 Apr 2020 09:06:23 +0800 Subject: fpga: dfl: fme: add performance reporting support This patch adds support for performance reporting private feature for FPGA Management Engine (FME). Now it supports several different performance counters, including 'basic', 'cache', 'fabric', 'vtd' and 'vtd_sip'. It allows user to use standard linux tools to access these performance counters. e.g. List all events by "perf list" perf list | grep fme dfl_fme0/cache_read_hit/ [Kernel PMU event] dfl_fme0/cache_read_miss/ [Kernel PMU event] ... dfl_fme0/fab_mmio_read/ [Kernel PMU event] dfl_fme0/fab_mmio_write/ [Kernel PMU event] ... dfl_fme0/fab_port_mmio_read,portid=?/ [Kernel PMU event] dfl_fme0/fab_port_mmio_write,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_port_devtlb_1g_fill,portid=?/ [Kernel PMU event] dfl_fme0/vtd_port_devtlb_2m_fill,portid=?/ [Kernel PMU event] ... dfl_fme0/vtd_sip_iotlb_1g_hit/ [Kernel PMU event] dfl_fme0/vtd_sip_iotlb_1g_miss/ [Kernel PMU event] ... dfl_fme0/clock [Kernel PMU event] ... e.g. check increased counter value after run one application using "perf stat" command. perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_mmio_write/ ./test Performance counter stats for './test': 1 dfl_fme0/fab_mmio_read/ 2 dfl_fme0/fab_mmio_write/ 1.009496520 seconds time elapsed Please note that fabric counters support both fab_* and fab_port_*, but actually they are sharing one set of performance counters in hardware. If user wants to monitor overall data events on fab_* then fab_port_* can't be supported at the same time, see example below: perf stat -e dfl_fme0/fab_mmio_read/,dfl_fme0/fab_port_mmio_write,portid=0/ Performance counter stats for 'system wide': 0 dfl_fme0/fab_mmio_read/ dfl_fme0/fab_port_mmio_write,portid=0/ 2.141064085 seconds time elapsed Signed-off-by: Luwei Kang Signed-off-by: Xu Yilun Signed-off-by: Wu Hao Link: https://lore.kernel.org/r/1587949583-12058-3-git-send-email-hao.wu@intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/fpga/Kconfig | 2 +- drivers/fpga/Makefile | 1 + drivers/fpga/dfl-fme-main.c | 4 + drivers/fpga/dfl-fme-perf.c | 1020 +++++++++++++++++++++++++++++++++++++++++++ drivers/fpga/dfl-fme.h | 2 + drivers/fpga/dfl.h | 2 + 6 files changed, 1030 insertions(+), 1 deletion(-) create mode 100644 drivers/fpga/dfl-fme-perf.c (limited to 'drivers/fpga') diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 72380e1d31c7..b2408a710662 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -156,7 +156,7 @@ config FPGA_DFL config FPGA_DFL_FME tristate "FPGA DFL FME Driver" - depends on FPGA_DFL && HWMON + depends on FPGA_DFL && HWMON && PERF_EVENTS help The FPGA Management Engine (FME) is a feature device implemented under Device Feature List (DFL) framework. Select this option to diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index 4865b74b00a4..d8e21dfc6778 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o +dfl-fme-objs += dfl-fme-perf.o dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o dfl-afu-objs += dfl-afu-error.o diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index 1d4690c99268..353305629a0e 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -579,6 +579,10 @@ static struct dfl_feature_driver fme_feature_drvs[] = { .id_table = fme_power_mgmt_id_table, .ops = &fme_power_mgmt_ops, }, + { + .id_table = fme_perf_id_table, + .ops = &fme_perf_ops, + }, { .ops = NULL, }, diff --git a/drivers/fpga/dfl-fme-perf.c b/drivers/fpga/dfl-fme-perf.c new file mode 100644 index 000000000000..6ce1ed222ea4 --- /dev/null +++ b/drivers/fpga/dfl-fme-perf.c @@ -0,0 +1,1020 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA Management Engine (FME) Global Performance Reporting + * + * Copyright 2019 Intel Corporation, Inc. + * + * Authors: + * Kang Luwei + * Xiao Guangrong + * Wu Hao + * Xu Yilun + * Joseph Grecco + * Enno Luebbers + * Tim Whisonant + * Ananda Ravuri + * Mitchel, Henry + */ + +#include +#include "dfl.h" +#include "dfl-fme.h" + +/* + * Performance Counter Registers for Cache. + * + * Cache Events are listed below as CACHE_EVNT_*. + */ +#define CACHE_CTRL 0x8 +#define CACHE_RESET_CNTR BIT_ULL(0) +#define CACHE_FREEZE_CNTR BIT_ULL(8) +#define CACHE_CTRL_EVNT GENMASK_ULL(19, 16) +#define CACHE_EVNT_RD_HIT 0x0 +#define CACHE_EVNT_WR_HIT 0x1 +#define CACHE_EVNT_RD_MISS 0x2 +#define CACHE_EVNT_WR_MISS 0x3 +#define CACHE_EVNT_RSVD 0x4 +#define CACHE_EVNT_HOLD_REQ 0x5 +#define CACHE_EVNT_DATA_WR_PORT_CONTEN 0x6 +#define CACHE_EVNT_TAG_WR_PORT_CONTEN 0x7 +#define CACHE_EVNT_TX_REQ_STALL 0x8 +#define CACHE_EVNT_RX_REQ_STALL 0x9 +#define CACHE_EVNT_EVICTIONS 0xa +#define CACHE_EVNT_MAX CACHE_EVNT_EVICTIONS +#define CACHE_CHANNEL_SEL BIT_ULL(20) +#define CACHE_CHANNEL_RD 0 +#define CACHE_CHANNEL_WR 1 +#define CACHE_CNTR0 0x10 +#define CACHE_CNTR1 0x18 +#define CACHE_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define CACHE_CNTR_EVNT GENMASK_ULL(63, 60) + +/* + * Performance Counter Registers for Fabric. + * + * Fabric Events are listed below as FAB_EVNT_* + */ +#define FAB_CTRL 0x20 +#define FAB_RESET_CNTR BIT_ULL(0) +#define FAB_FREEZE_CNTR BIT_ULL(8) +#define FAB_CTRL_EVNT GENMASK_ULL(19, 16) +#define FAB_EVNT_PCIE0_RD 0x0 +#define FAB_EVNT_PCIE0_WR 0x1 +#define FAB_EVNT_PCIE1_RD 0x2 +#define FAB_EVNT_PCIE1_WR 0x3 +#define FAB_EVNT_UPI_RD 0x4 +#define FAB_EVNT_UPI_WR 0x5 +#define FAB_EVNT_MMIO_RD 0x6 +#define FAB_EVNT_MMIO_WR 0x7 +#define FAB_EVNT_MAX FAB_EVNT_MMIO_WR +#define FAB_PORT_ID GENMASK_ULL(21, 20) +#define FAB_PORT_FILTER BIT_ULL(23) +#define FAB_PORT_FILTER_DISABLE 0 +#define FAB_PORT_FILTER_ENABLE 1 +#define FAB_CNTR 0x28 +#define FAB_CNTR_EVNT_CNTR GENMASK_ULL(59, 0) +#define FAB_CNTR_EVNT GENMASK_ULL(63, 60) + +/* + * Performance Counter Registers for Clock. + * + * Clock Counter can't be reset or frozen by SW. + */ +#define CLK_CNTR 0x30 +#define BASIC_EVNT_CLK 0x0 +#define BASIC_EVNT_MAX BASIC_EVNT_CLK + +/* + * Performance Counter Registers for IOMMU / VT-D. + * + * VT-D Events are listed below as VTD_EVNT_* and VTD_SIP_EVNT_* + */ +#define VTD_CTRL 0x38 +#define VTD_RESET_CNTR BIT_ULL(0) +#define VTD_FREEZE_CNTR BIT_ULL(8) +#define VTD_CTRL_EVNT GENMASK_ULL(19, 16) +#define VTD_EVNT_AFU_MEM_RD_TRANS 0x0 +#define VTD_EVNT_AFU_MEM_WR_TRANS 0x1 +#define VTD_EVNT_AFU_DEVTLB_RD_HIT 0x2 +#define VTD_EVNT_AFU_DEVTLB_WR_HIT 0x3 +#define VTD_EVNT_DEVTLB_4K_FILL 0x4 +#define VTD_EVNT_DEVTLB_2M_FILL 0x5 +#define VTD_EVNT_DEVTLB_1G_FILL 0x6 +#define VTD_EVNT_MAX VTD_EVNT_DEVTLB_1G_FILL +#define VTD_CNTR 0x40 +#define VTD_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define VTD_CNTR_EVNT GENMASK_ULL(63, 60) + +#define VTD_SIP_CTRL 0x48 +#define VTD_SIP_RESET_CNTR BIT_ULL(0) +#define VTD_SIP_FREEZE_CNTR BIT_ULL(8) +#define VTD_SIP_CTRL_EVNT GENMASK_ULL(19, 16) +#define VTD_SIP_EVNT_IOTLB_4K_HIT 0x0 +#define VTD_SIP_EVNT_IOTLB_2M_HIT 0x1 +#define VTD_SIP_EVNT_IOTLB_1G_HIT 0x2 +#define VTD_SIP_EVNT_SLPWC_L3_HIT 0x3 +#define VTD_SIP_EVNT_SLPWC_L4_HIT 0x4 +#define VTD_SIP_EVNT_RCC_HIT 0x5 +#define VTD_SIP_EVNT_IOTLB_4K_MISS 0x6 +#define VTD_SIP_EVNT_IOTLB_2M_MISS 0x7 +#define VTD_SIP_EVNT_IOTLB_1G_MISS 0x8 +#define VTD_SIP_EVNT_SLPWC_L3_MISS 0x9 +#define VTD_SIP_EVNT_SLPWC_L4_MISS 0xa +#define VTD_SIP_EVNT_RCC_MISS 0xb +#define VTD_SIP_EVNT_MAX VTD_SIP_EVNT_SLPWC_L4_MISS +#define VTD_SIP_CNTR 0X50 +#define VTD_SIP_CNTR_EVNT_CNTR GENMASK_ULL(47, 0) +#define VTD_SIP_CNTR_EVNT GENMASK_ULL(63, 60) + +#define PERF_TIMEOUT 30 + +#define PERF_MAX_PORT_NUM 1U + +/** + * struct fme_perf_priv - priv data structure for fme perf driver + * + * @dev: parent device. + * @ioaddr: mapped base address of mmio region. + * @pmu: pmu data structure for fme perf counters. + * @id: id of this fme performance report private feature. + * @fab_users: current user number on fabric counters. + * @fab_port_id: used to indicate current working mode of fabric counters. + * @fab_lock: lock to protect fabric counters working mode. + * @cpu: active CPU to which the PMU is bound for accesses. + * @cpuhp_node: node for CPU hotplug notifier link. + * @cpuhp_state: state for CPU hotplug notification; + */ +struct fme_perf_priv { + struct device *dev; + void __iomem *ioaddr; + struct pmu pmu; + u64 id; + + u32 fab_users; + u32 fab_port_id; + spinlock_t fab_lock; + + unsigned int cpu; + struct hlist_node node; + enum cpuhp_state cpuhp_state; +}; + +/** + * struct fme_perf_event_ops - callbacks for fme perf events + * + * @event_init: callback invoked during event init. + * @event_destroy: callback invoked during event destroy. + * @read_counter: callback to read hardware counters. + */ +struct fme_perf_event_ops { + int (*event_init)(struct fme_perf_priv *priv, u32 event, u32 portid); + void (*event_destroy)(struct fme_perf_priv *priv, u32 event, + u32 portid); + u64 (*read_counter)(struct fme_perf_priv *priv, u32 event, u32 portid); +}; + +#define to_fme_perf_priv(_pmu) container_of(_pmu, struct fme_perf_priv, pmu) + +static ssize_t cpumask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pmu *pmu = dev_get_drvdata(dev); + struct fme_perf_priv *priv; + + priv = to_fme_perf_priv(pmu); + + return cpumap_print_to_pagebuf(true, buf, cpumask_of(priv->cpu)); +} +static DEVICE_ATTR_RO(cpumask); + +static struct attribute *fme_perf_cpumask_attrs[] = { + &dev_attr_cpumask.attr, + NULL, +}; + +static struct attribute_group fme_perf_cpumask_group = { + .attrs = fme_perf_cpumask_attrs, +}; + +#define FME_EVENT_MASK GENMASK_ULL(11, 0) +#define FME_EVENT_SHIFT 0 +#define FME_EVTYPE_MASK GENMASK_ULL(15, 12) +#define FME_EVTYPE_SHIFT 12 +#define FME_EVTYPE_BASIC 0 +#define FME_EVTYPE_CACHE 1 +#define FME_EVTYPE_FABRIC 2 +#define FME_EVTYPE_VTD 3 +#define FME_EVTYPE_VTD_SIP 4 +#define FME_EVTYPE_MAX FME_EVTYPE_VTD_SIP +#define FME_PORTID_MASK GENMASK_ULL(23, 16) +#define FME_PORTID_SHIFT 16 +#define FME_PORTID_ROOT (0xffU) + +#define get_event(_config) FIELD_GET(FME_EVENT_MASK, _config) +#define get_evtype(_config) FIELD_GET(FME_EVTYPE_MASK, _config) +#define get_portid(_config) FIELD_GET(FME_PORTID_MASK, _config) + +PMU_FORMAT_ATTR(event, "config:0-11"); +PMU_FORMAT_ATTR(evtype, "config:12-15"); +PMU_FORMAT_ATTR(portid, "config:16-23"); + +static struct attribute *fme_perf_format_attrs[] = { + &format_attr_event.attr, + &format_attr_evtype.attr, + &format_attr_portid.attr, + NULL, +}; + +static struct attribute_group fme_perf_format_group = { + .name = "format", + .attrs = fme_perf_format_attrs, +}; + +/* + * There are no default events, but we need to create + * "events" group (with empty attrs) before updating + * it with detected events (using pmu->attr_update). + */ +static struct attribute *fme_perf_events_attrs_empty[] = { + NULL, +}; + +static struct attribute_group fme_perf_events_group = { + .name = "events", + .attrs = fme_perf_events_attrs_empty, +}; + +static const struct attribute_group *fme_perf_groups[] = { + &fme_perf_format_group, + &fme_perf_cpumask_group, + &fme_perf_events_group, + NULL, +}; + +static bool is_portid_root(u32 portid) +{ + return portid == FME_PORTID_ROOT; +} + +static bool is_portid_port(u32 portid) +{ + return portid < PERF_MAX_PORT_NUM; +} + +static bool is_portid_root_or_port(u32 portid) +{ + return is_portid_root(portid) || is_portid_port(portid); +} + +static u64 fme_read_perf_cntr_reg(void __iomem *addr) +{ + u32 low; + u64 v; + + /* + * For 64bit counter registers, the counter may increases and carries + * out of bit [31] between 2 32bit reads. So add extra reads to help + * to prevent this issue. This only happens in platforms which don't + * support 64bit read - readq is split into 2 readl. + */ + do { + v = readq(addr); + low = readl(addr); + } while (((u32)v) > low); + + return v; +} + +static int basic_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (event <= BASIC_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 basic_read_event_counter(struct fme_perf_priv *priv, + u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + + return fme_read_perf_cntr_reg(base + CLK_CNTR); +} + +static int cache_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= CACHE_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 cache_read_event_counter(struct fme_perf_priv *priv, + u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v, count; + u8 channel; + + if (event == CACHE_EVNT_WR_HIT || event == CACHE_EVNT_WR_MISS || + event == CACHE_EVNT_DATA_WR_PORT_CONTEN || + event == CACHE_EVNT_TAG_WR_PORT_CONTEN) + channel = CACHE_CHANNEL_WR; + else + channel = CACHE_CHANNEL_RD; + + /* set channel access type and cache event code. */ + v = readq(base + CACHE_CTRL); + v &= ~(CACHE_CHANNEL_SEL | CACHE_CTRL_EVNT); + v |= FIELD_PREP(CACHE_CHANNEL_SEL, channel); + v |= FIELD_PREP(CACHE_CTRL_EVNT, event); + writeq(v, base + CACHE_CTRL); + + if (readq_poll_timeout_atomic(base + CACHE_CNTR0, v, + FIELD_GET(CACHE_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched cache event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + CACHE_CNTR0); + count = FIELD_GET(CACHE_CNTR_EVNT_CNTR, v); + v = fme_read_perf_cntr_reg(base + CACHE_CNTR1); + count += FIELD_GET(CACHE_CNTR_EVNT_CNTR, v); + + return count; +} + +static bool is_fabric_event_supported(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + if (event > FAB_EVNT_MAX || !is_portid_root_or_port(portid)) + return false; + + if (priv->id == FME_FEATURE_ID_GLOBAL_DPERF && + (event == FAB_EVNT_PCIE1_RD || event == FAB_EVNT_UPI_RD || + event == FAB_EVNT_PCIE1_WR || event == FAB_EVNT_UPI_WR)) + return false; + + return true; +} + +static int fabric_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + void __iomem *base = priv->ioaddr; + int ret = 0; + u64 v; + + if (!is_fabric_event_supported(priv, event, portid)) + return -EINVAL; + + /* + * as fabric counter set only can be in either overall or port mode. + * In overall mode, it counts overall data for FPGA, and in port mode, + * it is configured to monitor on one individual port. + * + * so every time, a new event is initialized, driver checks + * current working mode and if someone is using this counter set. + */ + spin_lock(&priv->fab_lock); + if (priv->fab_users && priv->fab_port_id != portid) { + dev_dbg(priv->dev, "conflict fabric event monitoring mode.\n"); + ret = -EOPNOTSUPP; + goto exit; + } + + priv->fab_users++; + + /* + * skip if current working mode matches, otherwise change the working + * mode per input port_id, to monitor overall data or another port. + */ + if (priv->fab_port_id == portid) + goto exit; + + priv->fab_port_id = portid; + + v = readq(base + FAB_CTRL); + v &= ~(FAB_PORT_FILTER | FAB_PORT_ID); + + if (is_portid_root(portid)) { + v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_DISABLE); + } else { + v |= FIELD_PREP(FAB_PORT_FILTER, FAB_PORT_FILTER_ENABLE); + v |= FIELD_PREP(FAB_PORT_ID, portid); + } + writeq(v, base + FAB_CTRL); + +exit: + spin_unlock(&priv->fab_lock); + return ret; +} + +static void fabric_event_destroy(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + spin_lock(&priv->fab_lock); + priv->fab_users--; + spin_unlock(&priv->fab_lock); +} + +static u64 fabric_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + v = readq(base + FAB_CTRL); + v &= ~FAB_CTRL_EVNT; + v |= FIELD_PREP(FAB_CTRL_EVNT, event); + writeq(v, base + FAB_CTRL); + + if (readq_poll_timeout_atomic(base + FAB_CNTR, v, + FIELD_GET(FAB_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched fab event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + FAB_CNTR); + return FIELD_GET(FAB_CNTR_EVNT_CNTR, v); +} + +static int vtd_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= VTD_EVNT_MAX && is_portid_port(portid)) + return 0; + + return -EINVAL; +} + +static u64 vtd_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + event += (portid * (VTD_EVNT_MAX + 1)); + + v = readq(base + VTD_CTRL); + v &= ~VTD_CTRL_EVNT; + v |= FIELD_PREP(VTD_CTRL_EVNT, event); + writeq(v, base + VTD_CTRL); + + if (readq_poll_timeout_atomic(base + VTD_CNTR, v, + FIELD_GET(VTD_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched vtd event code in counter register.\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + VTD_CNTR); + return FIELD_GET(VTD_CNTR_EVNT_CNTR, v); +} + +static int vtd_sip_event_init(struct fme_perf_priv *priv, u32 event, u32 portid) +{ + if (priv->id == FME_FEATURE_ID_GLOBAL_IPERF && + event <= VTD_SIP_EVNT_MAX && is_portid_root(portid)) + return 0; + + return -EINVAL; +} + +static u64 vtd_sip_read_event_counter(struct fme_perf_priv *priv, u32 event, + u32 portid) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + v = readq(base + VTD_SIP_CTRL); + v &= ~VTD_SIP_CTRL_EVNT; + v |= FIELD_PREP(VTD_SIP_CTRL_EVNT, event); + writeq(v, base + VTD_SIP_CTRL); + + if (readq_poll_timeout_atomic(base + VTD_SIP_CNTR, v, + FIELD_GET(VTD_SIP_CNTR_EVNT, v) == event, + 1, PERF_TIMEOUT)) { + dev_err(priv->dev, "timeout, unmatched vtd sip event code in counter register\n"); + return 0; + } + + v = fme_read_perf_cntr_reg(base + VTD_SIP_CNTR); + return FIELD_GET(VTD_SIP_CNTR_EVNT_CNTR, v); +} + +static struct fme_perf_event_ops fme_perf_event_ops[] = { + [FME_EVTYPE_BASIC] = {.event_init = basic_event_init, + .read_counter = basic_read_event_counter,}, + [FME_EVTYPE_CACHE] = {.event_init = cache_event_init, + .read_counter = cache_read_event_counter,}, + [FME_EVTYPE_FABRIC] = {.event_init = fabric_event_init, + .event_destroy = fabric_event_destroy, + .read_counter = fabric_read_event_counter,}, + [FME_EVTYPE_VTD] = {.event_init = vtd_event_init, + .read_counter = vtd_read_event_counter,}, + [FME_EVTYPE_VTD_SIP] = {.event_init = vtd_sip_event_init, + .read_counter = vtd_sip_read_event_counter,}, +}; + +static ssize_t fme_perf_event_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *eattr; + unsigned long config; + char *ptr = buf; + + eattr = container_of(attr, struct dev_ext_attribute, attr); + config = (unsigned long)eattr->var; + + ptr += sprintf(ptr, "event=0x%02x", (unsigned int)get_event(config)); + ptr += sprintf(ptr, ",evtype=0x%02x", (unsigned int)get_evtype(config)); + + if (is_portid_root(get_portid(config))) + ptr += sprintf(ptr, ",portid=0x%02x\n", FME_PORTID_ROOT); + else + ptr += sprintf(ptr, ",portid=?\n"); + + return (ssize_t)(ptr - buf); +} + +#define FME_EVENT_ATTR(_name) \ + __ATTR(_name, 0444, fme_perf_event_show, NULL) + +#define FME_PORT_EVENT_CONFIG(_event, _type) \ + (void *)((((_event) << FME_EVENT_SHIFT) & FME_EVENT_MASK) | \ + (((_type) << FME_EVTYPE_SHIFT) & FME_EVTYPE_MASK)) + +#define FME_EVENT_CONFIG(_event, _type) \ + (void *)((((_event) << FME_EVENT_SHIFT) & FME_EVENT_MASK) | \ + (((_type) << FME_EVTYPE_SHIFT) & FME_EVTYPE_MASK) | \ + (FME_PORTID_ROOT << FME_PORTID_SHIFT)) + +/* FME Perf Basic Events */ +#define FME_EVENT_BASIC(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_##_name = { \ + .attr = FME_EVENT_ATTR(_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_BASIC), \ +} + +FME_EVENT_BASIC(clock, BASIC_EVNT_CLK); + +static struct attribute *fme_perf_basic_events_attrs[] = { + &fme_perf_event_clock.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_basic_events_group = { + .name = "events", + .attrs = fme_perf_basic_events_attrs, +}; + +/* FME Perf Cache Events */ +#define FME_EVENT_CACHE(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_cache_##_name = { \ + .attr = FME_EVENT_ATTR(cache_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_CACHE), \ +} + +FME_EVENT_CACHE(read_hit, CACHE_EVNT_RD_HIT); +FME_EVENT_CACHE(read_miss, CACHE_EVNT_RD_MISS); +FME_EVENT_CACHE(write_hit, CACHE_EVNT_WR_HIT); +FME_EVENT_CACHE(write_miss, CACHE_EVNT_WR_MISS); +FME_EVENT_CACHE(hold_request, CACHE_EVNT_HOLD_REQ); +FME_EVENT_CACHE(tx_req_stall, CACHE_EVNT_TX_REQ_STALL); +FME_EVENT_CACHE(rx_req_stall, CACHE_EVNT_RX_REQ_STALL); +FME_EVENT_CACHE(eviction, CACHE_EVNT_EVICTIONS); +FME_EVENT_CACHE(data_write_port_contention, CACHE_EVNT_DATA_WR_PORT_CONTEN); +FME_EVENT_CACHE(tag_write_port_contention, CACHE_EVNT_TAG_WR_PORT_CONTEN); + +static struct attribute *fme_perf_cache_events_attrs[] = { + &fme_perf_event_cache_read_hit.attr.attr, + &fme_perf_event_cache_read_miss.attr.attr, + &fme_perf_event_cache_write_hit.attr.attr, + &fme_perf_event_cache_write_miss.attr.attr, + &fme_perf_event_cache_hold_request.attr.attr, + &fme_perf_event_cache_tx_req_stall.attr.attr, + &fme_perf_event_cache_rx_req_stall.attr.attr, + &fme_perf_event_cache_eviction.attr.attr, + &fme_perf_event_cache_data_write_port_contention.attr.attr, + &fme_perf_event_cache_tag_write_port_contention.attr.attr, + NULL, +}; + +static umode_t fme_perf_events_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct fme_perf_priv *priv = to_fme_perf_priv(pmu); + + return (priv->id == FME_FEATURE_ID_GLOBAL_IPERF) ? attr->mode : 0; +} + +static const struct attribute_group fme_perf_cache_events_group = { + .name = "events", + .attrs = fme_perf_cache_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +/* FME Perf Fabric Events */ +#define FME_EVENT_FABRIC(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_fab_##_name = { \ + .attr = FME_EVENT_ATTR(fab_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_FABRIC), \ +} + +#define FME_EVENT_FABRIC_PORT(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_fab_port_##_name = { \ + .attr = FME_EVENT_ATTR(fab_port_##_name), \ + .var = FME_PORT_EVENT_CONFIG(_event, FME_EVTYPE_FABRIC), \ +} + +FME_EVENT_FABRIC(pcie0_read, FAB_EVNT_PCIE0_RD); +FME_EVENT_FABRIC(pcie0_write, FAB_EVNT_PCIE0_WR); +FME_EVENT_FABRIC(pcie1_read, FAB_EVNT_PCIE1_RD); +FME_EVENT_FABRIC(pcie1_write, FAB_EVNT_PCIE1_WR); +FME_EVENT_FABRIC(upi_read, FAB_EVNT_UPI_RD); +FME_EVENT_FABRIC(upi_write, FAB_EVNT_UPI_WR); +FME_EVENT_FABRIC(mmio_read, FAB_EVNT_MMIO_RD); +FME_EVENT_FABRIC(mmio_write, FAB_EVNT_MMIO_WR); + +FME_EVENT_FABRIC_PORT(pcie0_read, FAB_EVNT_PCIE0_RD); +FME_EVENT_FABRIC_PORT(pcie0_write, FAB_EVNT_PCIE0_WR); +FME_EVENT_FABRIC_PORT(pcie1_read, FAB_EVNT_PCIE1_RD); +FME_EVENT_FABRIC_PORT(pcie1_write, FAB_EVNT_PCIE1_WR); +FME_EVENT_FABRIC_PORT(upi_read, FAB_EVNT_UPI_RD); +FME_EVENT_FABRIC_PORT(upi_write, FAB_EVNT_UPI_WR); +FME_EVENT_FABRIC_PORT(mmio_read, FAB_EVNT_MMIO_RD); +FME_EVENT_FABRIC_PORT(mmio_write, FAB_EVNT_MMIO_WR); + +static struct attribute *fme_perf_fabric_events_attrs[] = { + &fme_perf_event_fab_pcie0_read.attr.attr, + &fme_perf_event_fab_pcie0_write.attr.attr, + &fme_perf_event_fab_pcie1_read.attr.attr, + &fme_perf_event_fab_pcie1_write.attr.attr, + &fme_perf_event_fab_upi_read.attr.attr, + &fme_perf_event_fab_upi_write.attr.attr, + &fme_perf_event_fab_mmio_read.attr.attr, + &fme_perf_event_fab_mmio_write.attr.attr, + &fme_perf_event_fab_port_pcie0_read.attr.attr, + &fme_perf_event_fab_port_pcie0_write.attr.attr, + &fme_perf_event_fab_port_pcie1_read.attr.attr, + &fme_perf_event_fab_port_pcie1_write.attr.attr, + &fme_perf_event_fab_port_upi_read.attr.attr, + &fme_perf_event_fab_port_upi_write.attr.attr, + &fme_perf_event_fab_port_mmio_read.attr.attr, + &fme_perf_event_fab_port_mmio_write.attr.attr, + NULL, +}; + +static umode_t fme_perf_fabric_events_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); + struct fme_perf_priv *priv = to_fme_perf_priv(pmu); + struct dev_ext_attribute *eattr; + unsigned long var; + + eattr = container_of(attr, struct dev_ext_attribute, attr.attr); + var = (unsigned long)eattr->var; + + if (is_fabric_event_supported(priv, get_event(var), get_portid(var))) + return attr->mode; + + return 0; +} + +static const struct attribute_group fme_perf_fabric_events_group = { + .name = "events", + .attrs = fme_perf_fabric_events_attrs, + .is_visible = fme_perf_fabric_events_visible, +}; + +/* FME Perf VTD Events */ +#define FME_EVENT_VTD_PORT(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_vtd_port_##_name = { \ + .attr = FME_EVENT_ATTR(vtd_port_##_name), \ + .var = FME_PORT_EVENT_CONFIG(_event, FME_EVTYPE_VTD), \ +} + +FME_EVENT_VTD_PORT(read_transaction, VTD_EVNT_AFU_MEM_RD_TRANS); +FME_EVENT_VTD_PORT(write_transaction, VTD_EVNT_AFU_MEM_WR_TRANS); +FME_EVENT_VTD_PORT(devtlb_read_hit, VTD_EVNT_AFU_DEVTLB_RD_HIT); +FME_EVENT_VTD_PORT(devtlb_write_hit, VTD_EVNT_AFU_DEVTLB_WR_HIT); +FME_EVENT_VTD_PORT(devtlb_4k_fill, VTD_EVNT_DEVTLB_4K_FILL); +FME_EVENT_VTD_PORT(devtlb_2m_fill, VTD_EVNT_DEVTLB_2M_FILL); +FME_EVENT_VTD_PORT(devtlb_1g_fill, VTD_EVNT_DEVTLB_1G_FILL); + +static struct attribute *fme_perf_vtd_events_attrs[] = { + &fme_perf_event_vtd_port_read_transaction.attr.attr, + &fme_perf_event_vtd_port_write_transaction.attr.attr, + &fme_perf_event_vtd_port_devtlb_read_hit.attr.attr, + &fme_perf_event_vtd_port_devtlb_write_hit.attr.attr, + &fme_perf_event_vtd_port_devtlb_4k_fill.attr.attr, + &fme_perf_event_vtd_port_devtlb_2m_fill.attr.attr, + &fme_perf_event_vtd_port_devtlb_1g_fill.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_vtd_events_group = { + .name = "events", + .attrs = fme_perf_vtd_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +/* FME Perf VTD SIP Events */ +#define FME_EVENT_VTD_SIP(_name, _event) \ +static struct dev_ext_attribute fme_perf_event_vtd_sip_##_name = { \ + .attr = FME_EVENT_ATTR(vtd_sip_##_name), \ + .var = FME_EVENT_CONFIG(_event, FME_EVTYPE_VTD_SIP), \ +} + +FME_EVENT_VTD_SIP(iotlb_4k_hit, VTD_SIP_EVNT_IOTLB_4K_HIT); +FME_EVENT_VTD_SIP(iotlb_2m_hit, VTD_SIP_EVNT_IOTLB_2M_HIT); +FME_EVENT_VTD_SIP(iotlb_1g_hit, VTD_SIP_EVNT_IOTLB_1G_HIT); +FME_EVENT_VTD_SIP(slpwc_l3_hit, VTD_SIP_EVNT_SLPWC_L3_HIT); +FME_EVENT_VTD_SIP(slpwc_l4_hit, VTD_SIP_EVNT_SLPWC_L4_HIT); +FME_EVENT_VTD_SIP(rcc_hit, VTD_SIP_EVNT_RCC_HIT); +FME_EVENT_VTD_SIP(iotlb_4k_miss, VTD_SIP_EVNT_IOTLB_4K_MISS); +FME_EVENT_VTD_SIP(iotlb_2m_miss, VTD_SIP_EVNT_IOTLB_2M_MISS); +FME_EVENT_VTD_SIP(iotlb_1g_miss, VTD_SIP_EVNT_IOTLB_1G_MISS); +FME_EVENT_VTD_SIP(slpwc_l3_miss, VTD_SIP_EVNT_SLPWC_L3_MISS); +FME_EVENT_VTD_SIP(slpwc_l4_miss, VTD_SIP_EVNT_SLPWC_L4_MISS); +FME_EVENT_VTD_SIP(rcc_miss, VTD_SIP_EVNT_RCC_MISS); + +static struct attribute *fme_perf_vtd_sip_events_attrs[] = { + &fme_perf_event_vtd_sip_iotlb_4k_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_2m_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_1g_hit.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l3_hit.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l4_hit.attr.attr, + &fme_perf_event_vtd_sip_rcc_hit.attr.attr, + &fme_perf_event_vtd_sip_iotlb_4k_miss.attr.attr, + &fme_perf_event_vtd_sip_iotlb_2m_miss.attr.attr, + &fme_perf_event_vtd_sip_iotlb_1g_miss.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l3_miss.attr.attr, + &fme_perf_event_vtd_sip_slpwc_l4_miss.attr.attr, + &fme_perf_event_vtd_sip_rcc_miss.attr.attr, + NULL, +}; + +static const struct attribute_group fme_perf_vtd_sip_events_group = { + .name = "events", + .attrs = fme_perf_vtd_sip_events_attrs, + .is_visible = fme_perf_events_visible, +}; + +static const struct attribute_group *fme_perf_events_groups[] = { + &fme_perf_basic_events_group, + &fme_perf_cache_events_group, + &fme_perf_fabric_events_group, + &fme_perf_vtd_events_group, + &fme_perf_vtd_sip_events_group, + NULL, +}; + +static struct fme_perf_event_ops *get_event_ops(u32 evtype) +{ + if (evtype > FME_EVTYPE_MAX) + return NULL; + + return &fme_perf_event_ops[evtype]; +} + +static void fme_perf_event_destroy(struct perf_event *event) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + + if (ops->event_destroy) + ops->event_destroy(priv, event->hw.idx, event->hw.config_base); +} + +static int fme_perf_event_init(struct perf_event *event) +{ + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + struct fme_perf_event_ops *ops; + u32 eventid, evtype, portid; + + /* test the event attr type check for PMU enumeration */ + if (event->attr.type != event->pmu->type) + return -ENOENT; + + /* + * fme counters are shared across all cores. + * Therefore, it does not support per-process mode. + * Also, it does not support event sampling mode. + */ + if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) + return -EINVAL; + + if (event->cpu < 0) + return -EINVAL; + + if (event->cpu != priv->cpu) + return -EINVAL; + + eventid = get_event(event->attr.config); + portid = get_portid(event->attr.config); + evtype = get_evtype(event->attr.config); + if (evtype > FME_EVTYPE_MAX) + return -EINVAL; + + hwc->event_base = evtype; + hwc->idx = (int)eventid; + hwc->config_base = portid; + + event->destroy = fme_perf_event_destroy; + + dev_dbg(priv->dev, "%s event=0x%x, evtype=0x%x, portid=0x%x,\n", + __func__, eventid, evtype, portid); + + ops = get_event_ops(evtype); + if (ops->event_init) + return ops->event_init(priv, eventid, portid); + + return 0; +} + +static void fme_perf_event_update(struct perf_event *event) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 now, prev, delta; + + now = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); + prev = local64_read(&hwc->prev_count); + delta = now - prev; + + local64_add(delta, &event->count); +} + +static void fme_perf_event_start(struct perf_event *event, int flags) +{ + struct fme_perf_event_ops *ops = get_event_ops(event->hw.event_base); + struct fme_perf_priv *priv = to_fme_perf_priv(event->pmu); + struct hw_perf_event *hwc = &event->hw; + u64 count; + + count = ops->read_counter(priv, (u32)hwc->idx, hwc->config_base); + local64_set(&hwc->prev_count, count); +} + +static void fme_perf_event_stop(struct perf_event *event, int flags) +{ + fme_perf_event_update(event); +} + +static int fme_perf_event_add(struct perf_event *event, int flags) +{ + if (flags & PERF_EF_START) + fme_perf_event_start(event, flags); + + return 0; +} + +static void fme_perf_event_del(struct perf_event *event, int flags) +{ + fme_perf_event_stop(event, PERF_EF_UPDATE); +} + +static void fme_perf_event_read(struct perf_event *event) +{ + fme_perf_event_update(event); +} + +static void fme_perf_setup_hardware(struct fme_perf_priv *priv) +{ + void __iomem *base = priv->ioaddr; + u64 v; + + /* read and save current working mode for fabric counters */ + v = readq(base + FAB_CTRL); + + if (FIELD_GET(FAB_PORT_FILTER, v) == FAB_PORT_FILTER_DISABLE) + priv->fab_port_id = FME_PORTID_ROOT; + else + priv->fab_port_id = FIELD_GET(FAB_PORT_ID, v); +} + +static int fme_perf_pmu_register(struct platform_device *pdev, + struct fme_perf_priv *priv) +{ + struct pmu *pmu = &priv->pmu; + char *name; + int ret; + + spin_lock_init(&priv->fab_lock); + + fme_perf_setup_hardware(priv); + + pmu->task_ctx_nr = perf_invalid_context; + pmu->attr_groups = fme_perf_groups; + pmu->attr_update = fme_perf_events_groups; + pmu->event_init = fme_perf_event_init; + pmu->add = fme_perf_event_add; + pmu->del = fme_perf_event_del; + pmu->start = fme_perf_event_start; + pmu->stop = fme_perf_event_stop; + pmu->read = fme_perf_event_read; + pmu->capabilities = PERF_PMU_CAP_NO_INTERRUPT | + PERF_PMU_CAP_NO_EXCLUDE; + + name = devm_kasprintf(priv->dev, GFP_KERNEL, "dfl_fme%d", pdev->id); + + ret = perf_pmu_register(pmu, name, -1); + if (ret) + return ret; + + return 0; +} + +static void fme_perf_pmu_unregister(struct fme_perf_priv *priv) +{ + perf_pmu_unregister(&priv->pmu); +} + +static int fme_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) +{ + struct fme_perf_priv *priv; + int target; + + priv = hlist_entry_safe(node, struct fme_perf_priv, node); + + if (cpu != priv->cpu) + return 0; + + target = cpumask_any_but(cpu_online_mask, cpu); + if (target >= nr_cpu_ids) + return 0; + + priv->cpu = target; + return 0; +} + +static int fme_perf_init(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct fme_perf_priv *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = &pdev->dev; + priv->ioaddr = feature->ioaddr; + priv->id = feature->id; + priv->cpu = raw_smp_processor_id(); + + ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/fpga/dfl_fme:online", + NULL, fme_perf_offline_cpu); + if (ret < 0) + return ret; + + priv->cpuhp_state = ret; + + /* Register the pmu instance for cpu hotplug */ + ret = cpuhp_state_add_instance_nocalls(priv->cpuhp_state, &priv->node); + if (ret) + goto cpuhp_instance_err; + + ret = fme_perf_pmu_register(pdev, priv); + if (ret) + goto pmu_register_err; + + feature->priv = priv; + return 0; + +pmu_register_err: + cpuhp_state_remove_instance_nocalls(priv->cpuhp_state, &priv->node); +cpuhp_instance_err: + cpuhp_remove_multi_state(priv->cpuhp_state); + return ret; +} + +static void fme_perf_uinit(struct platform_device *pdev, + struct dfl_feature *feature) +{ + struct fme_perf_priv *priv = feature->priv; + + fme_perf_pmu_unregister(priv); + cpuhp_state_remove_instance_nocalls(priv->cpuhp_state, &priv->node); + cpuhp_remove_multi_state(priv->cpuhp_state); +} + +const struct dfl_feature_id fme_perf_id_table[] = { + {.id = FME_FEATURE_ID_GLOBAL_IPERF,}, + {.id = FME_FEATURE_ID_GLOBAL_DPERF,}, + {0,} +}; + +const struct dfl_feature_ops fme_perf_ops = { + .init = fme_perf_init, + .uinit = fme_perf_uinit, +}; diff --git a/drivers/fpga/dfl-fme.h b/drivers/fpga/dfl-fme.h index 6685c8ef965b..4195dd68193e 100644 --- a/drivers/fpga/dfl-fme.h +++ b/drivers/fpga/dfl-fme.h @@ -38,5 +38,7 @@ extern const struct dfl_feature_id fme_pr_mgmt_id_table[]; extern const struct dfl_feature_ops fme_global_err_ops; extern const struct dfl_feature_id fme_global_err_id_table[]; extern const struct attribute_group fme_global_err_group; +extern const struct dfl_feature_ops fme_perf_ops; +extern const struct dfl_feature_id fme_perf_id_table[]; #endif /* __DFL_FME_H */ diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 9f0e656de720..d312678a9aca 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -197,12 +197,14 @@ struct dfl_feature_driver { * feature dev (platform device)'s reources. * @ioaddr: mapped mmio resource address. * @ops: ops of this sub feature. + * @priv: priv data of this feature. */ struct dfl_feature { u64 id; int resource_index; void __iomem *ioaddr; const struct dfl_feature_ops *ops; + void *priv; }; #define DEV_STATUS_IN_USE 0 -- cgit v1.2.3 From b6862193ca12e4bce6a18f31bb36eaa6d801b377 Mon Sep 17 00:00:00 2001 From: Xu Yilun Date: Mon, 18 Nov 2019 13:20:41 +0800 Subject: fpga: dfl: support multiple opens on feature device node. Each DFL functional block, e.g. AFU (Accelerated Function Unit) and FME (FPGA Management Engine), could implement more than one function within its region, but current driver only allows one user application to access it by exclusive open on device node. So this is not convenient and flexible for userspace applications, as they have to combine lots of different functions into one single application. This patch removes the limitation here to allow multiple opens to each feature device node for AFU and FME from userspace applications. If user still needs exclusive access to these device node, O_EXCL flag must be issued together with open. Signed-off-by: Wu Hao Signed-off-by: Xu Yilun Signed-off-by: Moritz Fischer --- drivers/fpga/dfl-afu-main.c | 26 +++++++++++++++----------- drivers/fpga/dfl-fme-main.c | 19 ++++++++++++------- drivers/fpga/dfl.c | 15 +++++++++++++-- drivers/fpga/dfl.h | 35 +++++++++++++++++++++++++++-------- 4 files changed, 67 insertions(+), 28 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 65437b6a6842..435bde40f361 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -561,14 +561,16 @@ static int afu_open(struct inode *inode, struct file *filp) if (WARN_ON(!pdata)) return -ENODEV; - ret = dfl_feature_dev_use_begin(pdata); - if (ret) - return ret; - - dev_dbg(&fdev->dev, "Device File Open\n"); - filp->private_data = fdev; + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); + if (!ret) { + dev_dbg(&fdev->dev, "Device File Opened %d Times\n", + dfl_feature_dev_use_count(pdata)); + filp->private_data = fdev; + } + mutex_unlock(&pdata->lock); - return 0; + return ret; } static int afu_release(struct inode *inode, struct file *filp) @@ -581,12 +583,14 @@ static int afu_release(struct inode *inode, struct file *filp) pdata = dev_get_platdata(&pdev->dev); mutex_lock(&pdata->lock); - __port_reset(pdev); - afu_dma_region_destroy(pdata); - mutex_unlock(&pdata->lock); - dfl_feature_dev_use_end(pdata); + if (!dfl_feature_dev_use_count(pdata)) { + __port_reset(pdev); + afu_dma_region_destroy(pdata); + } + mutex_unlock(&pdata->lock); + return 0; } diff --git a/drivers/fpga/dfl-fme-main.c b/drivers/fpga/dfl-fme-main.c index 1d4690c99268..56d720c1af39 100644 --- a/drivers/fpga/dfl-fme-main.c +++ b/drivers/fpga/dfl-fme-main.c @@ -600,14 +600,16 @@ static int fme_open(struct inode *inode, struct file *filp) if (WARN_ON(!pdata)) return -ENODEV; - ret = dfl_feature_dev_use_begin(pdata); - if (ret) - return ret; - - dev_dbg(&fdev->dev, "Device File Open\n"); - filp->private_data = pdata; + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL); + if (!ret) { + dev_dbg(&fdev->dev, "Device File Opened %d Times\n", + dfl_feature_dev_use_count(pdata)); + filp->private_data = pdata; + } + mutex_unlock(&pdata->lock); - return 0; + return ret; } static int fme_release(struct inode *inode, struct file *filp) @@ -616,7 +618,10 @@ static int fme_release(struct inode *inode, struct file *filp) struct platform_device *pdev = pdata->dev; dev_dbg(&pdev->dev, "Device File Release\n"); + + mutex_lock(&pdata->lock); dfl_feature_dev_use_end(pdata); + mutex_unlock(&pdata->lock); return 0; } diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 96a2b8274a33..990994874bf1 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -1079,6 +1079,7 @@ static int __init dfl_fpga_init(void) */ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) { + struct dfl_feature_platform_data *pdata; struct platform_device *port_pdev; int ret = -ENODEV; @@ -1093,7 +1094,11 @@ int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id) goto put_dev_exit; } - ret = dfl_feature_dev_use_begin(dev_get_platdata(&port_pdev->dev)); + pdata = dev_get_platdata(&port_pdev->dev); + + mutex_lock(&pdata->lock); + ret = dfl_feature_dev_use_begin(pdata, true); + mutex_unlock(&pdata->lock); if (ret) goto put_dev_exit; @@ -1120,6 +1125,7 @@ EXPORT_SYMBOL_GPL(dfl_fpga_cdev_release_port); */ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) { + struct dfl_feature_platform_data *pdata; struct platform_device *port_pdev; int ret = -ENODEV; @@ -1138,7 +1144,12 @@ int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id) if (ret) goto put_dev_exit; - dfl_feature_dev_use_end(dev_get_platdata(&port_pdev->dev)); + pdata = dev_get_platdata(&port_pdev->dev); + + mutex_lock(&pdata->lock); + dfl_feature_dev_use_end(pdata); + mutex_unlock(&pdata->lock); + cdev->released_port_num--; put_dev_exit: put_device(&port_pdev->dev); diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 9f0e656de720..4a9a33cd9979 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -205,8 +205,6 @@ struct dfl_feature { const struct dfl_feature_ops *ops; }; -#define DEV_STATUS_IN_USE 0 - #define FEATURE_DEV_ID_UNUSED (-1) /** @@ -219,8 +217,9 @@ struct dfl_feature { * @dfl_cdev: ptr to container device. * @id: id used for this feature device. * @disable_count: count for port disable. + * @excl_open: set on feature device exclusive open. + * @open_count: count for feature device open. * @num: number for sub features. - * @dev_status: dev status (e.g. DEV_STATUS_IN_USE). * @private: ptr to feature dev private data. * @features: sub features of this feature dev. */ @@ -232,26 +231,46 @@ struct dfl_feature_platform_data { struct dfl_fpga_cdev *dfl_cdev; int id; unsigned int disable_count; - unsigned long dev_status; + bool excl_open; + int open_count; void *private; int num; struct dfl_feature features[0]; }; static inline -int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata) +int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata, + bool excl) { - /* Test and set IN_USE flags to ensure file is exclusively used */ - if (test_and_set_bit_lock(DEV_STATUS_IN_USE, &pdata->dev_status)) + if (pdata->excl_open) return -EBUSY; + if (excl) { + if (pdata->open_count) + return -EBUSY; + + pdata->excl_open = true; + } + pdata->open_count++; + return 0; } static inline void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata) { - clear_bit_unlock(DEV_STATUS_IN_USE, &pdata->dev_status); + pdata->excl_open = false; + + if (WARN_ON(pdata->open_count <= 0)) + return; + + pdata->open_count--; +} + +static inline +int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata) +{ + return pdata->open_count; } static inline -- cgit v1.2.3 From 1493674ba3c0f0d48f5f1bdd8a32cbc3bb7be619 Mon Sep 17 00:00:00 2001 From: Sergiu Cuciurean Date: Thu, 27 Feb 2020 14:09:32 +0200 Subject: fpga: ice40-spi: Use new structure for SPI transfer delays In a recent change to the SPI subsystem [1], a new `delay` struct was added to replace the `delay_usecs`. This change replaces the current `delay_usecs` with `delay` for this driver. The `spi_transfer_delay_exec()` function [in the SPI framework] makes sure that both `delay_usecs` & `delay` are used (in this order to preserve backwards compatibility). [1] commit bebcfd272df6 ("spi: introduce `delay` field for `spi_transfer` + spi_transfer_delay_exec()") Signed-off-by: Sergiu Cuciurean Signed-off-by: Moritz Fischer --- drivers/fpga/ice40-spi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c index 56e112e14a10..8d689fea0dab 100644 --- a/drivers/fpga/ice40-spi.c +++ b/drivers/fpga/ice40-spi.c @@ -46,10 +46,16 @@ static int ice40_fpga_ops_write_init(struct fpga_manager *mgr, struct spi_message message; struct spi_transfer assert_cs_then_reset_delay = { .cs_change = 1, - .delay_usecs = ICE40_SPI_RESET_DELAY + .delay = { + .value = ICE40_SPI_RESET_DELAY, + .unit = SPI_DELAY_UNIT_USECS + } }; struct spi_transfer housekeeping_delay_then_release_cs = { - .delay_usecs = ICE40_SPI_HOUSEKEEPING_DELAY + .delay = { + .value = ICE40_SPI_HOUSEKEEPING_DELAY, + .unit = SPI_DELAY_UNIT_USECS + } }; int ret; -- cgit v1.2.3 From a1d1f5d490a475db9fbf7e9d164009f9c26345b2 Mon Sep 17 00:00:00 2001 From: Sergiu Cuciurean Date: Thu, 27 Feb 2020 16:24:14 +0200 Subject: fpga: machxo2-spi: Use new structure for SPI transfer delays In a recent change to the SPI subsystem [1], a new `delay` struct was added to replace the `delay_usecs`. This change replaces the current `delay_usecs` with `delay` for this driver. The `spi_transfer_delay_exec()` function [in the SPI framework] makes sure that both `delay_usecs` & `delay` are used (in this order to preserve backwards compatibility). [1] commit bebcfd272df6 ("spi: introduce `delay` field for `spi_transfer` + spi_transfer_delay_exec()") Signed-off-by: Sergiu Cuciurean Signed-off-by: Moritz Fischer --- drivers/fpga/machxo2-spi.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/machxo2-spi.c b/drivers/fpga/machxo2-spi.c index 4d8a87641587..b316369156fe 100644 --- a/drivers/fpga/machxo2-spi.c +++ b/drivers/fpga/machxo2-spi.c @@ -157,7 +157,8 @@ static int machxo2_cleanup(struct fpga_manager *mgr) spi_message_init(&msg); tx[1].tx_buf = &refresh; tx[1].len = sizeof(refresh); - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; + tx[1].delay.value = MACHXO2_REFRESH_USEC; + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[1], &msg); ret = spi_sync(spi, &msg); if (ret) @@ -208,7 +209,8 @@ static int machxo2_write_init(struct fpga_manager *mgr, spi_message_init(&msg); tx[0].tx_buf = &enable; tx[0].len = sizeof(enable); - tx[0].delay_usecs = MACHXO2_LOW_DELAY_USEC; + tx[0].delay.value = MACHXO2_LOW_DELAY_USEC; + tx[0].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[0], &msg); tx[1].tx_buf = &erase; @@ -269,7 +271,8 @@ static int machxo2_write(struct fpga_manager *mgr, const char *buf, spi_message_init(&msg); tx.tx_buf = payload; tx.len = MACHXO2_BUF_SIZE; - tx.delay_usecs = MACHXO2_HIGH_DELAY_USEC; + tx.delay.value = MACHXO2_HIGH_DELAY_USEC; + tx.delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx, &msg); ret = spi_sync(spi, &msg); if (ret) { @@ -317,7 +320,8 @@ static int machxo2_write_complete(struct fpga_manager *mgr, spi_message_init(&msg); tx[1].tx_buf = &refresh; tx[1].len = sizeof(refresh); - tx[1].delay_usecs = MACHXO2_REFRESH_USEC; + tx[1].delay.value = MACHXO2_REFRESH_USEC; + tx[1].delay.unit = SPI_DELAY_UNIT_USECS; spi_message_add_tail(&tx[1], &msg); ret = spi_sync(spi, &msg); if (ret) -- cgit v1.2.3 From d299253cf5b4e0f21ff1ce1d2f02e5ea634ebcb9 Mon Sep 17 00:00:00 2001 From: Richard Gong Date: Fri, 14 Feb 2020 10:00:48 -0600 Subject: fpga: stratix10-soc: add compatible property value for intel agilex Add compatible property value so we can reuse FPGA manager driver on Intel Agilex SoC platform. Signed-off-by: Richard Gong Signed-off-by: Moritz Fischer --- drivers/fpga/stratix10-soc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c index 215d33789c74..bac93d009170 100644 --- a/drivers/fpga/stratix10-soc.c +++ b/drivers/fpga/stratix10-soc.c @@ -482,7 +482,8 @@ static int s10_remove(struct platform_device *pdev) } static const struct of_device_id s10_of_match[] = { - { .compatible = "intel,stratix10-soc-fpga-mgr", }, + {.compatible = "intel,stratix10-soc-fpga-mgr"}, + {.compatible = "intel,agilex-soc-fpga-mgr"}, {}, }; -- cgit v1.2.3 From 5a53881580f90a5e4404954af16a5646ee9d7842 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Thu, 19 Mar 2020 16:21:53 -0500 Subject: fpga: dfl.h: Replace zero-length array with flexible-array member The current codebase makes use of the zero-length array language extension to the C90 standard, but the preferred mechanism to declare variable-length types such as these ones is a flexible array member[1][2], introduced in C99: struct foo { int stuff; struct boo array[]; }; By making use of the mechanism above, we will get a compiler warning in case the flexible array does not occur last in the structure, which will help us prevent some kind of undefined behavior bugs from being inadvertently introduced[3] to the codebase from now on. Also, notice that, dynamic memory allocations won't be affected by this change: "Flexible array members have incomplete type, and so the sizeof operator may not be applied. As a quirk of the original implementation of zero-length arrays, sizeof evaluates to zero."[1] This issue was found with the help of Coccinelle. [1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html [2] https://github.com/KSPP/linux/issues/21 [3] commit 76497732932f ("cxgb3/l2t: Fix undefined behaviour") Signed-off-by: Gustavo A. R. Silva Signed-off-by: Moritz Fischer --- drivers/fpga/dfl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 4a9a33cd9979..74784d3cfe7c 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -235,7 +235,7 @@ struct dfl_feature_platform_data { int open_count; void *private; int num; - struct dfl_feature features[0]; + struct dfl_feature features[]; }; static inline -- cgit v1.2.3 From a2b9d4eadb7727772698d06e4cbeb1a1e2538675 Mon Sep 17 00:00:00 2001 From: Dominic Chen Date: Mon, 9 Mar 2020 14:53:23 -0400 Subject: fpga: dfl: afu: support debug access to memory-mapped afu regions Allow debug access to memory-mapped regions using e.g. gdb. Signed-off-by: Dominic Chen Acked-by: Wu Hao Signed-off-by: Moritz Fischer --- drivers/fpga/dfl-afu-main.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/fpga') diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 435bde40f361..b0c31789a909 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -750,6 +750,12 @@ static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return -EINVAL; } +static const struct vm_operations_struct afu_vma_ops = { +#ifdef CONFIG_HAVE_IOREMAP_PROT + .access = generic_access_phys, +#endif +}; + static int afu_mmap(struct file *filp, struct vm_area_struct *vma) { struct platform_device *pdev = filp->private_data; @@ -779,6 +785,9 @@ static int afu_mmap(struct file *filp, struct vm_area_struct *vma) !(region.flags & DFL_PORT_REGION_WRITE)) return -EPERM; + /* Support debug access to the mapping */ + vma->vm_ops = &afu_vma_ops; + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); return remap_pfn_range(vma, vma->vm_start, -- cgit v1.2.3 From c9d7e3da1f3c4cf5dddfc5d7ce4d76d013aba1cc Mon Sep 17 00:00:00 2001 From: Souptick Joarder Date: Mon, 18 May 2020 23:49:51 +0530 Subject: fpga: dfl: afu: Corrected error handling levels Corrected error handling goto sequnece. Level put_pages should be called when pinned pages >= 0 && pinned != npages. Level free_pages should be called when pinned pages < 0. Fixes: fa8dda1edef9 ("fpga: dfl: afu: add DFL_FPGA_PORT_DMA_MAP/UNMAP ioctls support") Signed-off-by: Souptick Joarder Acked-by: Wu Hao Reviewed-by: Xu Yilun Link: https://lore.kernel.org/r/1589825991-3545-1-git-send-email-jrdr.linux@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/fpga/dfl-afu-dma-region.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/fpga') diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl-afu-dma-region.c index 62f924489db5..5942343a5d6e 100644 --- a/drivers/fpga/dfl-afu-dma-region.c +++ b/drivers/fpga/dfl-afu-dma-region.c @@ -61,10 +61,10 @@ static int afu_dma_pin_pages(struct dfl_feature_platform_data *pdata, region->pages); if (pinned < 0) { ret = pinned; - goto put_pages; + goto free_pages; } else if (pinned != npages) { ret = -EFAULT; - goto free_pages; + goto put_pages; } dev_dbg(dev, "%d pages pinned\n", pinned); -- cgit v1.2.3