From 4932d37055e7a459a92424c4d21ebf8c2c0fb19a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 8 Dec 2020 16:19:42 +0100 Subject: drm/amdgpu: limit the amdgpu_vm_update_ptes trace point MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The text output should not be more than a page, so only print the first 32 page table entries. If we need all of them we can still look into the binary trace. Signed-off-by: Christian König Reviewed-by: Shashank Sharma Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 324d5e3f3579..6752d8b13118 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -358,10 +358,11 @@ TRACE_EVENT(amdgpu_vm_update_ptes, } ), TP_printk("pid:%u vm_ctx:0x%llx start:0x%010llx end:0x%010llx," - " flags:0x%llx, incr:%llu, dst:\n%s", __entry->pid, + " flags:0x%llx, incr:%llu, dst:\n%s%s", __entry->pid, __entry->vm_ctx, __entry->start, __entry->end, __entry->flags, __entry->incr, __print_array( - __get_dynamic_array(dst), __entry->nptes, 8)) + __get_dynamic_array(dst), min(__entry->nptes, 32u), 8), + __entry->nptes > 32 ? "..." : "") ); TRACE_EVENT(amdgpu_vm_set_ptes, -- cgit v1.2.3 From 0269764a731bba0b5b1afb134abab702fbde1f04 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Mon, 7 Dec 2020 17:20:27 -0500 Subject: drm/amd/display: Drop unnecessary function call After refactor our amdgpu_dm_atomic_commit, this function only invoke drm_atomic_helper_commit. For this reason, this commit drops amdgpu_dm_atomic_commit and add drm_atomic_helper_commit directly in the atomic_commit hook. v2: squash in warning fix (Alex) Reviewed-by: Alex Deucher Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c23896207e9d..562d874f81fb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -196,10 +196,6 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); -static int amdgpu_dm_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock); - static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, @@ -2212,7 +2208,7 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .get_format_info = amd_get_format_info, .output_poll_changed = drm_fb_helper_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, - .atomic_commit = amdgpu_dm_atomic_commit, + .atomic_commit = drm_atomic_helper_commit, }; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { @@ -8070,20 +8066,6 @@ static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_stat stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state); } -static int amdgpu_dm_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock) -{ - /* - * Add check here for SoC's that support hardware cursor plane, to - * unset legacy_cursor_update - */ - - return drm_atomic_helper_commit(dev, state, nonblock); - - /*TODO Handle EINTR, reenable IRQ*/ -} - /** * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation. * @state: The atomic state to commit -- cgit v1.2.3 From 0d801007f90ec023aefc1da19529bf9985050227 Mon Sep 17 00:00:00 2001 From: Jiansong Chen Date: Wed, 9 Dec 2020 19:43:44 +0800 Subject: drm/amdkfd: correct pipe offset calculation Correct pipe offset calculation in is_pipe_enabled function, it should be done in queues. Signed-off-by: Jiansong Chen Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index f0a6f6665c81..e686ce2bf3b3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -72,8 +72,8 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type) static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe) { int i; - int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec - + pipe * dqm->dev->shared_resources.num_queue_per_pipe; + int pipe_offset = (mec * dqm->dev->shared_resources.num_pipe_per_mec + + pipe) * dqm->dev->shared_resources.num_queue_per_pipe; /* queue is available for KFD usage if bit is 1 */ for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i) -- cgit v1.2.3 From 18a4b3de5fc1c63c80e3be0673886431a56e4307 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 7 Dec 2020 16:21:03 +0800 Subject: drm/amd/pm: support power source switch on Sienna Cichlid Enable power source switch on Sienna Cichlid. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index db0f2a476c23..1ce13944721b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -302,6 +302,9 @@ static int sienna_cichlid_check_powerplay_table(struct smu_context *smu) table_context->power_play_table; struct smu_baco_context *smu_baco = &smu->smu_baco; + if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC) + smu->dc_controlled_by_gpio = true; + if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO || powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) smu_baco->platform_support = true; @@ -2740,6 +2743,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq, .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range, .run_btc = sienna_cichlid_run_btc, + .set_power_source = smu_v11_0_set_power_source, .get_pp_feature_mask = smu_cmn_get_pp_feature_mask, .set_pp_feature_mask = smu_cmn_set_pp_feature_mask, .get_gpu_metrics = sienna_cichlid_get_gpu_metrics, -- cgit v1.2.3 From 0cb4c62125a904259e24016b5e85408c27dc412a Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 7 Dec 2020 16:53:25 +0800 Subject: drm/amd/pm: correct power limit setting for SMU V11 Correct the power limit setting for SMU V11 asics. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index 624065d3c079..f2565eed469f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -929,9 +929,13 @@ int smu_v11_0_get_current_power_limit(struct smu_context *smu, if (power_src < 0) return -EINVAL; + /* + * BIT 24-31: ControllerId (only PPT0 is supported for now) + * BIT 16-23: PowerSource + */ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetPptLimit, - power_src << 16, + (0 << 24) | (power_src << 16), power_limit); if (ret) dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__); @@ -941,6 +945,7 @@ int smu_v11_0_get_current_power_limit(struct smu_context *smu, int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) { + int power_src; int ret = 0; if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { @@ -948,6 +953,22 @@ int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) return -EOPNOTSUPP; } + power_src = smu_cmn_to_asic_specific_index(smu, + CMN2ASIC_MAPPING_PWR, + smu->adev->pm.ac_power ? + SMU_POWER_SOURCE_AC : + SMU_POWER_SOURCE_DC); + if (power_src < 0) + return -EINVAL; + + /* + * BIT 24-31: ControllerId (only PPT0 is supported for now) + * BIT 16-23: PowerSource + * BIT 0-15: PowerLimit + */ + n &= 0xFFFF; + n |= 0 << 24; + n |= (power_src) << 16; ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL); if (ret) { dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__); -- cgit v1.2.3 From ac7804bb9908b972c1aa02eb79a5688c051a5668 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 8 Dec 2020 11:59:52 +0800 Subject: drm/amd/pm: correct the gpo control for sienna cichlid New SMC message was introduced for gpo control on sienna cichlid. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 + drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h | 4 ++- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 42 ++++++++++++++++------ 3 files changed, 36 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index 4a6d1381df16..1251dd411516 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -209,6 +209,7 @@ __SMU_DUMMY_MAP(SetSoftMinCclk), \ __SMU_DUMMY_MAP(SetSoftMaxCclk), \ __SMU_DUMMY_MAP(SetGpoFeaturePMask), \ + __SMU_DUMMY_MAP(DisallowGpo), \ #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h index 35dd6072cc45..dad2832ff3b1 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h @@ -134,6 +134,8 @@ #define PPSMC_MSG_SetGpoFeaturePMask 0x45 #define PPSMC_MSG_SetSMBUSInterrupt 0x46 -#define PPSMC_Message_Count 0x47 +#define PPSMC_MSG_DisallowGpo 0x56 + +#define PPSMC_Message_Count 0x58 #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 1ce13944721b..d88361554d94 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -128,6 +128,7 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), + MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), }; static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { @@ -2653,19 +2654,40 @@ static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu) static int sienna_cichlid_gpo_control(struct smu_context *smu, bool enablement) { + uint32_t smu_version; int ret = 0; + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) { - if (enablement) - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetGpoFeaturePMask, - GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, - NULL); - else - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetGpoFeaturePMask, - 0, - NULL); + ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (ret) + return ret; + + if (enablement) { + if (smu_version < 0x003a2500) { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetGpoFeaturePMask, + GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK, + NULL); + } else { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_DisallowGpo, + 0, + NULL); + } + } else { + if (smu_version < 0x003a2500) { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_SetGpoFeaturePMask, + 0, + NULL); + } else { + ret = smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_DisallowGpo, + 1, + NULL); + } + } } return ret; -- cgit v1.2.3 From a7e660e526c9936cad3871d8cd1e3360b0b87469 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 8 Dec 2020 12:26:09 +0800 Subject: drm/amd/pm: expose the firmware_capability from firmware_info table That will help to determine whether 2ND_USB20_PORT workaround is needed for Sienna Cichlid. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 1 + drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 2 ++ 2 files changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h index 89be49a43500..4bdbcce7092d 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h @@ -227,6 +227,7 @@ struct smu_bios_boot_up_values uint32_t content_revision; uint32_t fclk; uint32_t lclk; + uint32_t firmware_caps; }; enum smu_table_id diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index f2565eed469f..45ecd0386e9f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -554,6 +554,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; smu->smu_table.boot_values.pp_table_id = 0; + smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability; break; case 3: default: @@ -569,6 +570,7 @@ int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; + smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability; } smu->smu_table.boot_values.format_revision = header->format_revision; -- cgit v1.2.3 From ad26bd11261c8b07cb88aa4e81e2d3f8e1452d77 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 8 Dec 2020 12:30:09 +0800 Subject: drm/amdgpu: new macro for determining 2ND_USB20PORT support Used for determining 2ND_USB20PORT support from firmware_capability. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index c38635992101..3cb8d4c5c1a3 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -499,6 +499,7 @@ enum atombios_firmware_capability ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, + ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, }; enum atom_cooling_solution_id{ -- cgit v1.2.3 From 88dfd5d5c8cb973c141a674000d40573daea58a2 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Tue, 8 Dec 2020 13:07:24 +0800 Subject: drm/amd/pm: new SMC message for 2nd usb2.0 port workaround The workaround is needed by sienna cichlid. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_types.h | 1 + drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h | 2 ++ drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 + 3 files changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index 1251dd411516..1787ae8a9fd9 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -210,6 +210,7 @@ __SMU_DUMMY_MAP(SetSoftMaxCclk), \ __SMU_DUMMY_MAP(SetGpoFeaturePMask), \ __SMU_DUMMY_MAP(DisallowGpo), \ + __SMU_DUMMY_MAP(Enable2ndUSB20Port), \ #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h index dad2832ff3b1..d2e10a724560 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0_7_ppsmc.h @@ -136,6 +136,8 @@ #define PPSMC_MSG_DisallowGpo 0x56 +#define PPSMC_MSG_Enable2ndUSB20Port 0x57 + #define PPSMC_Message_Count 0x58 #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index d88361554d94..b1b038f24cce 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -129,6 +129,7 @@ static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0), MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0), + MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0), }; static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = { -- cgit v1.2.3 From d7f52e2930015d6104ed6eb4c987d1b396dc548c Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 9 Dec 2020 11:43:22 +0800 Subject: drm/amd/pm: fulfill sienna cichlid 2nd usb2.0 port workaround Fulfill the 2nd usb2.0 port workaround for sienna cichlid. Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 40 +++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index b1b038f24cce..3163de39472a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -2693,6 +2693,44 @@ static int sienna_cichlid_gpo_control(struct smu_context *smu, return ret; } + +static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu) +{ + uint32_t smu_version; + int ret = 0; + + ret = smu_cmn_get_smc_version(smu, NULL, &smu_version); + if (ret) + return ret; + + /* + * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45 + * onwards PMFWs. + */ + if (smu_version < 0x003A2D00) + return 0; + + return smu_cmn_send_smc_msg_with_param(smu, + SMU_MSG_Enable2ndUSB20Port, + smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ? + 1 : 0, + NULL); +} + +static int sienna_cichlid_system_features_control(struct smu_context *smu, + bool en) +{ + int ret = 0; + + if (en) { + ret = sienna_cichlid_notify_2nd_usb20_port(smu); + if (ret) + return ret; + } + + return smu_v11_0_system_features_control(smu, en); +} + static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask, .set_default_dpm_table = sienna_cichlid_set_default_dpm_table, @@ -2733,7 +2771,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = { .set_driver_table_location = smu_v11_0_set_driver_table_location, .set_tool_table_location = smu_v11_0_set_tool_table_location, .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location, - .system_features_control = smu_v11_0_system_features_control, + .system_features_control = sienna_cichlid_system_features_control, .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param, .send_smc_msg = smu_cmn_send_smc_msg, .init_display_count = NULL, -- cgit v1.2.3 From 4c4d5a49c6347e27e1c80fb4275f8ad160bcf4f3 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 9 Dec 2020 16:34:22 +0800 Subject: drm/amd/pm: typo fix (CUSTOM -> COMPUTE) The "COMPUTE" was wrongly spelled as "CUSTOM". Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 3163de39472a..b8127be43320 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -220,7 +220,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; -- cgit v1.2.3 From 7c431455cdd6add04f0d4a1a671095623d18622d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 30 Nov 2020 18:57:50 -0500 Subject: drm/amdgpu/display: move link_bandwidth_kbps under CONFIG_DRM_AMD_DC_DCN It's only used when CONFIG_DRM_AMD_DC_DCN is set. Fixes and set but not used warning. Acked-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 562d874f81fb..0a908cb8119c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5120,9 +5120,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, int preferred_refresh = 0; #if defined(CONFIG_DRM_AMD_DC_DCN) struct dsc_dec_dpcd_caps dsc_caps; -#endif uint32_t link_bandwidth_kbps; - +#endif struct dc_sink *sink = NULL; if (aconnector == NULL) { DRM_ERROR("aconnector is NULL!\n"); @@ -5204,11 +5203,9 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw, &dsc_caps); -#endif link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)); -#if defined(CONFIG_DRM_AMD_DC_DCN) if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) { /* Set DSC policy according to dsc_clock_en */ dc_dsc_policy_set_enable_dsc_when_not_needed( -- cgit v1.2.3 From fe96eb197e98efa32c129c4af3b44813c42bb93f Mon Sep 17 00:00:00 2001 From: Xiaomeng Hou Date: Tue, 1 Dec 2020 17:49:50 +0800 Subject: drm/amd/pm: update the smu v11.5 smc header for vangogh Add new PMFW message to notify RLC engine status. Signed-off-by: Xiaomeng Hou Reviewed-by: Huang Rui Reviewed-by: Lazar Lijo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/inc/smu_types.h | 2 +- drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h index 1787ae8a9fd9..720d15612fe1 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h @@ -178,7 +178,7 @@ __SMU_DUMMY_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW), \ __SMU_DUMMY_MAP(GET_UMC_FW_WA), \ __SMU_DUMMY_MAP(Mode1Reset), \ - __SMU_DUMMY_MAP(Spare), \ + __SMU_DUMMY_MAP(RlcPowerNotify), \ __SMU_DUMMY_MAP(SetHardMinIspiclkByFreq), \ __SMU_DUMMY_MAP(SetHardMinIspxclkByFreq), \ __SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \ diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h index 7e69b3bd311b..55d7892e4e0e 100644 --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h @@ -41,7 +41,7 @@ #define PPSMC_MSG_PowerUpIspByTile 0x7 #define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default #define PPSMC_MSG_PowerUpVcn 0x9 -#define PPSMC_MSG_spare 0xA +#define PPSMC_MSG_RlcPowerNotify 0xA #define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display #define PPSMC_MSG_SetSoftMinGfxclk 0xC //Sets SoftMin for GFXCLK. Arg is in MHz #define PPSMC_MSG_ActiveProcessNotify 0xD -- cgit v1.2.3 From a0f55287b50c3e4d2fae6e3a09d2c8ea81140897 Mon Sep 17 00:00:00 2001 From: Xiaomeng Hou Date: Tue, 1 Dec 2020 18:33:33 +0800 Subject: drm/amd/pm: inform SMU RLC status thus enable/disable DPM feature for vangogh RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFW is unaware of RLC being halted and will continue sending messages, which would eventually cause an ACPI hang. Use the system_feature_control interface to notify SMU the status of RLC (Normal/OFF) thus enable/disable DPM feature. Signed-off-by: Xiaomeng Hou Reviewed-by: Huang Rui Reviewed-by: Lazar Lijo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 9 ++++++++- drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h | 4 ++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index a81e5c823211..9bccf2ad038c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -64,7 +64,7 @@ static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = { MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0), MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0), MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0), - MSG_MAP(Spare, PPSMC_MSG_spare, 0), + MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0), MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0), MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0), MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0), @@ -722,6 +722,12 @@ static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu) return 0; } +static int vangogh_system_features_control(struct smu_context *smu, bool en) +{ + return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify, + en ? RLC_STATUS_NORMAL : RLC_STATUS_OFF, NULL); +} + static const struct pptable_funcs vangogh_ppt_funcs = { .check_fw_status = smu_v11_0_check_fw_status, @@ -749,6 +755,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = { .print_clk_levels = vangogh_print_fine_grain_clk, .set_default_dpm_table = vangogh_set_default_dpm_tables, .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters, + .system_features_control = vangogh_system_features_control, }; void vangogh_set_ppt_funcs(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h index 8756766296cd..eab455493076 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h @@ -32,4 +32,8 @@ extern void vangogh_set_ppt_funcs(struct smu_context *smu); #define VANGOGH_UMD_PSTATE_SOCCLK 678 #define VANGOGH_UMD_PSTATE_FCLK 800 +/* RLC Power Status */ +#define RLC_STATUS_OFF 0 +#define RLC_STATUS_NORMAL 1 + #endif -- cgit v1.2.3 From 0dc994fb61a9b859bf4bde936a4c6de652116a23 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 9 Dec 2020 14:30:29 +0800 Subject: drm/amd/pm: fulfill the sienna cichlid UMD PSTATE profiling clocks Fulfill the UMD PSTATE profiling clocks of sienna cichlid. Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 6 ++++++ drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h | 4 ++++ 2 files changed, 10 insertions(+) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index b8127be43320..0fbc9cfd76ff 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -1070,12 +1070,18 @@ static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu) pstate_table->gfxclk_pstate.min = gfx_table->min; pstate_table->gfxclk_pstate.peak = gfx_table->max; + if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK) + pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK; pstate_table->uclk_pstate.min = mem_table->min; pstate_table->uclk_pstate.peak = mem_table->max; + if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK) + pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK; pstate_table->socclk_pstate.min = soc_table->min; pstate_table->socclk_pstate.peak = soc_table->max; + if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK) + pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK; return 0; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h index 57e120c440ea..38cd0ece24f6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.h @@ -29,6 +29,10 @@ typedef enum { POWER_SOURCE_COUNT, } POWER_SOURCE_e; +#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK 1825 +#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK 960 +#define SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK 1000 + extern void sienna_cichlid_set_ppt_funcs(struct smu_context *smu); #endif -- cgit v1.2.3 From f9e3fe46202a18dea8c54af392be2b361b0194e7 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 10 Dec 2020 12:03:50 +0800 Subject: drm/amd/pm: correct the data structure for activity monitor coeff exchange This is needed for Sienna Cichlid. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 125 +++++++++++---------- 1 file changed, 65 insertions(+), 60 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 0fbc9cfd76ff..148fa3af33fc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -391,7 +391,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, - sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE, + sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); @@ -1167,7 +1167,9 @@ static int sienna_cichlid_get_fan_parameters(struct smu_context *smu) static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf) { - DpmActivityMonitorCoeffInt_t activity_monitor; + DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; + DpmActivityMonitorCoeffInt_t *activity_monitor = + &(activity_monitor_external.DpmActivityMonitorCoeffInt); uint32_t i, size = 0; int16_t workload_type = 0; static const char *profile_name[] = { @@ -1209,7 +1211,7 @@ static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char * result = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type, - (void *)(&activity_monitor), false); + (void *)(&activity_monitor_external), false); if (result) { dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); return result; @@ -1222,43 +1224,43 @@ static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char * " ", 0, "GFXCLK", - activity_monitor.Gfx_FPS, - activity_monitor.Gfx_MinFreqStep, - activity_monitor.Gfx_MinActiveFreqType, - activity_monitor.Gfx_MinActiveFreq, - activity_monitor.Gfx_BoosterFreqType, - activity_monitor.Gfx_BoosterFreq, - activity_monitor.Gfx_PD_Data_limit_c, - activity_monitor.Gfx_PD_Data_error_coeff, - activity_monitor.Gfx_PD_Data_error_rate_coeff); + activity_monitor->Gfx_FPS, + activity_monitor->Gfx_MinFreqStep, + activity_monitor->Gfx_MinActiveFreqType, + activity_monitor->Gfx_MinActiveFreq, + activity_monitor->Gfx_BoosterFreqType, + activity_monitor->Gfx_BoosterFreq, + activity_monitor->Gfx_PD_Data_limit_c, + activity_monitor->Gfx_PD_Data_error_coeff, + activity_monitor->Gfx_PD_Data_error_rate_coeff); size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", " ", 1, "SOCCLK", - activity_monitor.Fclk_FPS, - activity_monitor.Fclk_MinFreqStep, - activity_monitor.Fclk_MinActiveFreqType, - activity_monitor.Fclk_MinActiveFreq, - activity_monitor.Fclk_BoosterFreqType, - activity_monitor.Fclk_BoosterFreq, - activity_monitor.Fclk_PD_Data_limit_c, - activity_monitor.Fclk_PD_Data_error_coeff, - activity_monitor.Fclk_PD_Data_error_rate_coeff); + activity_monitor->Fclk_FPS, + activity_monitor->Fclk_MinFreqStep, + activity_monitor->Fclk_MinActiveFreqType, + activity_monitor->Fclk_MinActiveFreq, + activity_monitor->Fclk_BoosterFreqType, + activity_monitor->Fclk_BoosterFreq, + activity_monitor->Fclk_PD_Data_limit_c, + activity_monitor->Fclk_PD_Data_error_coeff, + activity_monitor->Fclk_PD_Data_error_rate_coeff); size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n", " ", 2, "MEMLK", - activity_monitor.Mem_FPS, - activity_monitor.Mem_MinFreqStep, - activity_monitor.Mem_MinActiveFreqType, - activity_monitor.Mem_MinActiveFreq, - activity_monitor.Mem_BoosterFreqType, - activity_monitor.Mem_BoosterFreq, - activity_monitor.Mem_PD_Data_limit_c, - activity_monitor.Mem_PD_Data_error_coeff, - activity_monitor.Mem_PD_Data_error_rate_coeff); + activity_monitor->Mem_FPS, + activity_monitor->Mem_MinFreqStep, + activity_monitor->Mem_MinActiveFreqType, + activity_monitor->Mem_MinActiveFreq, + activity_monitor->Mem_BoosterFreqType, + activity_monitor->Mem_BoosterFreq, + activity_monitor->Mem_PD_Data_limit_c, + activity_monitor->Mem_PD_Data_error_coeff, + activity_monitor->Mem_PD_Data_error_rate_coeff); } return size; @@ -1266,7 +1268,10 @@ static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char * static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size) { - DpmActivityMonitorCoeffInt_t activity_monitor; + + DpmActivityMonitorCoeffIntExternal_t activity_monitor_external; + DpmActivityMonitorCoeffInt_t *activity_monitor = + &(activity_monitor_external.DpmActivityMonitorCoeffInt); int workload_type, ret = 0; smu->power_profile_mode = input[size]; @@ -1280,7 +1285,7 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long * ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, - (void *)(&activity_monitor), false); + (void *)(&activity_monitor_external), false); if (ret) { dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__); return ret; @@ -1288,43 +1293,43 @@ static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long * switch (input[0]) { case 0: /* Gfxclk */ - activity_monitor.Gfx_FPS = input[1]; - activity_monitor.Gfx_MinFreqStep = input[2]; - activity_monitor.Gfx_MinActiveFreqType = input[3]; - activity_monitor.Gfx_MinActiveFreq = input[4]; - activity_monitor.Gfx_BoosterFreqType = input[5]; - activity_monitor.Gfx_BoosterFreq = input[6]; - activity_monitor.Gfx_PD_Data_limit_c = input[7]; - activity_monitor.Gfx_PD_Data_error_coeff = input[8]; - activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9]; + activity_monitor->Gfx_FPS = input[1]; + activity_monitor->Gfx_MinFreqStep = input[2]; + activity_monitor->Gfx_MinActiveFreqType = input[3]; + activity_monitor->Gfx_MinActiveFreq = input[4]; + activity_monitor->Gfx_BoosterFreqType = input[5]; + activity_monitor->Gfx_BoosterFreq = input[6]; + activity_monitor->Gfx_PD_Data_limit_c = input[7]; + activity_monitor->Gfx_PD_Data_error_coeff = input[8]; + activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9]; break; case 1: /* Socclk */ - activity_monitor.Fclk_FPS = input[1]; - activity_monitor.Fclk_MinFreqStep = input[2]; - activity_monitor.Fclk_MinActiveFreqType = input[3]; - activity_monitor.Fclk_MinActiveFreq = input[4]; - activity_monitor.Fclk_BoosterFreqType = input[5]; - activity_monitor.Fclk_BoosterFreq = input[6]; - activity_monitor.Fclk_PD_Data_limit_c = input[7]; - activity_monitor.Fclk_PD_Data_error_coeff = input[8]; - activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9]; + activity_monitor->Fclk_FPS = input[1]; + activity_monitor->Fclk_MinFreqStep = input[2]; + activity_monitor->Fclk_MinActiveFreqType = input[3]; + activity_monitor->Fclk_MinActiveFreq = input[4]; + activity_monitor->Fclk_BoosterFreqType = input[5]; + activity_monitor->Fclk_BoosterFreq = input[6]; + activity_monitor->Fclk_PD_Data_limit_c = input[7]; + activity_monitor->Fclk_PD_Data_error_coeff = input[8]; + activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9]; break; case 2: /* Memlk */ - activity_monitor.Mem_FPS = input[1]; - activity_monitor.Mem_MinFreqStep = input[2]; - activity_monitor.Mem_MinActiveFreqType = input[3]; - activity_monitor.Mem_MinActiveFreq = input[4]; - activity_monitor.Mem_BoosterFreqType = input[5]; - activity_monitor.Mem_BoosterFreq = input[6]; - activity_monitor.Mem_PD_Data_limit_c = input[7]; - activity_monitor.Mem_PD_Data_error_coeff = input[8]; - activity_monitor.Mem_PD_Data_error_rate_coeff = input[9]; + activity_monitor->Mem_FPS = input[1]; + activity_monitor->Mem_MinFreqStep = input[2]; + activity_monitor->Mem_MinActiveFreqType = input[3]; + activity_monitor->Mem_MinActiveFreq = input[4]; + activity_monitor->Mem_BoosterFreqType = input[5]; + activity_monitor->Mem_BoosterFreq = input[6]; + activity_monitor->Mem_PD_Data_limit_c = input[7]; + activity_monitor->Mem_PD_Data_error_coeff = input[8]; + activity_monitor->Mem_PD_Data_error_rate_coeff = input[9]; break; } ret = smu_cmn_update_table(smu, SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT, - (void *)(&activity_monitor), true); + (void *)(&activity_monitor_external), true); if (ret) { dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__); return ret; -- cgit v1.2.3 From b4b0b79d8a376d3d830a93f8fafc815d01525fc9 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 10 Dec 2020 12:42:24 +0800 Subject: drm/amd/pm: update the data strucutre for SMU metrics exchange This is needed for Sienna Cichlid. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 75 +++++++++++----------- 1 file changed, 39 insertions(+), 36 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 148fa3af33fc..9608745d732f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -382,7 +382,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); - SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t), + SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); @@ -394,7 +394,7 @@ static int sienna_cichlid_tables_init(struct smu_context *smu) sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM); - smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL); + smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL); if (!smu_table->metrics_table) goto err0_out; smu_table->metrics_time = 0; @@ -423,7 +423,8 @@ static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu, uint32_t *value) { struct smu_table_context *smu_table= &smu->smu_table; - SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table; + SmuMetrics_t *metrics = + &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics); int ret = 0; mutex_lock(&smu->metrics_lock); @@ -2598,52 +2599,54 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu, struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_0 *gpu_metrics = (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table; - SmuMetrics_t metrics; + SmuMetricsExternal_t metrics_external; + SmuMetrics_t *metrics = + &(metrics_external.SmuMetrics); int ret = 0; ret = smu_cmn_get_metrics_table(smu, - &metrics, + &metrics_external, true); if (ret) return ret; smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics); - gpu_metrics->temperature_edge = metrics.TemperatureEdge; - gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot; - gpu_metrics->temperature_mem = metrics.TemperatureMem; - gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx; - gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc; - gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0; + gpu_metrics->temperature_edge = metrics->TemperatureEdge; + gpu_metrics->temperature_hotspot = metrics->TemperatureHotspot; + gpu_metrics->temperature_mem = metrics->TemperatureMem; + gpu_metrics->temperature_vrgfx = metrics->TemperatureVrGfx; + gpu_metrics->temperature_vrsoc = metrics->TemperatureVrSoc; + gpu_metrics->temperature_vrmem = metrics->TemperatureVrMem0; - gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity; - gpu_metrics->average_umc_activity = metrics.AverageUclkActivity; - gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage; + gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; + gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; + gpu_metrics->average_mm_activity = metrics->VcnActivityPercentage; - gpu_metrics->average_socket_power = metrics.AverageSocketPower; - gpu_metrics->energy_accumulator = metrics.EnergyAccumulator; + gpu_metrics->average_socket_power = metrics->AverageSocketPower; + gpu_metrics->energy_accumulator = metrics->EnergyAccumulator; - if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) - gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs; + if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD) + gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs; else - gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs; - gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs; - gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency; - gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency; - gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency; - gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency; - - gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK]; - gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK]; - gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; - gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0]; - gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0]; - gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1]; - gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1]; - - gpu_metrics->throttle_status = metrics.ThrottlerStatus; - - gpu_metrics->current_fan_speed = metrics.CurrFanSpeed; + gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs; + gpu_metrics->average_uclk_frequency = metrics->AverageUclkFrequencyPostDs; + gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency; + gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency; + gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency; + gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency; + + gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK]; + gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK]; + gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; + gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0]; + gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0]; + gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1]; + gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1]; + + gpu_metrics->throttle_status = metrics->ThrottlerStatus; + + gpu_metrics->current_fan_speed = metrics->CurrFanSpeed; gpu_metrics->pcie_link_width = smu_v11_0_get_current_pcie_link_width(smu); -- cgit v1.2.3 From 78d907e2b8ba89c936b7f0c3344261c653668a62 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 10 Dec 2020 16:36:28 +0800 Subject: drm/amd/pm: add deep sleep control for uclk and fclk These are supported by Sienna Cichlid and should be taken into consideration during DS control. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index 45ecd0386e9f..0372cb83cdd9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -2087,6 +2087,22 @@ int smu_v11_0_deep_sleep_control(struct smu_context *smu, } } + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) { + ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement); + if (ret) { + dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable"); + return ret; + } + } + if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); if (ret) { -- cgit v1.2.3 From a9c210c1e5fefd621954fca50c72780bf0198327 Mon Sep 17 00:00:00 2001 From: Xiaomeng Hou Date: Thu, 10 Dec 2020 20:18:23 +0800 Subject: drm/amdgpu/sdma5.2: soft reset sdma blocks before setup and start sdma Without doing the soft reset, register mmSDMA0_GFX_RB_WPTR's value could not be reset to 0 when sdma block resumes. That would cause the ring buffer's read and write pointers not equal and ring test fail. So add the soft reset step. Signed-off-by: Xiaomeng Hou Reviewed-by: Huang Rui Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 39 ++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 39e17aae655f..5c4ac176b7e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -807,6 +807,37 @@ static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) return 0; } +static int sdma_v5_2_soft_reset(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 grbm_soft_reset; + u32 tmp; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) { + grbm_soft_reset = REG_SET_FIELD(0, + GRBM_SOFT_RESET, SOFT_RESET_SDMA0, + 1); + grbm_soft_reset <<= i; + + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + tmp |= grbm_soft_reset; + DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp); + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + + udelay(50); + + tmp &= ~grbm_soft_reset; + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); + tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + + udelay(50); + } + + return 0; +} + /** * sdma_v5_2_start - setup and start the async dma engines * @@ -838,6 +869,7 @@ static int sdma_v5_2_start(struct amdgpu_device *adev) msleep(1000); } + sdma_v5_2_soft_reset(adev); /* unhalt the MEs */ sdma_v5_2_enable(adev, true); /* enable sdma ring preemption */ @@ -1366,13 +1398,6 @@ static int sdma_v5_2_wait_for_idle(void *handle) return -ETIMEDOUT; } -static int sdma_v5_2_soft_reset(void *handle) -{ - /* todo */ - - return 0; -} - static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) { int i, r = 0; -- cgit v1.2.3 From 9ca5b8a170d180889bec0424c27fdd2ee84d2d99 Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Tue, 15 Dec 2020 11:32:20 -0500 Subject: drm/amdgpu: add judgement for suspend/resume sequence S0ix only makes sense on APUs since they are part of the platform, so only when the ASIC is APU should set amdgpu_acpi_is_s0ix_supported flag to deal with the related situation. Signed-off-by: Likun Gao Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 +++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++--- 3 files changed, 10 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6e2953233231..b24de64f4490 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1311,11 +1311,11 @@ int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, struct amdgpu_dm_backlight_caps *caps); -bool amdgpu_acpi_is_s0ix_supported(void); +bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev); #else static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } -static inline bool amdgpu_acpi_is_s0ix_supported(void) { return false; } +static inline bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { return false; } #endif int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 4f4fda53c08a..8155c54392c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -901,10 +901,12 @@ void amdgpu_acpi_fini(struct amdgpu_device *adev) * * returns true if supported, false if not. */ -bool amdgpu_acpi_is_s0ix_supported(void) +bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) { - if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) - return true; + if (acpi_gbl_FADT.flags & ACPI_FADT_LOW_POWER_S0) { + if (adev->flags & AMD_IS_APU) + return true; + } return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 79dd85f71fab..0ec7c28c4d5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2650,7 +2650,7 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) { int i, r; - if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev)) { + if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) { amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE); amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE); } @@ -3710,7 +3710,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) amdgpu_fence_driver_suspend(adev); - if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev)) + if (!amdgpu_acpi_is_s0ix_supported(adev) || amdgpu_in_reset(adev)) r = amdgpu_device_ip_suspend_phase2(adev); else amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); @@ -3744,7 +3744,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) return 0; - if (amdgpu_acpi_is_s0ix_supported()) + if (amdgpu_acpi_is_s0ix_supported(adev)) amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry); /* post card */ -- cgit v1.2.3 From 79cc42697dbd17f19d8ad1d87945a47d2f73573e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 14 Dec 2020 10:23:13 +0800 Subject: drm/amd/display: drop retired CONFIG_DRM_AMD_DC_DCN3_0 CONFIG_DRM_AMD_DC_DCN3_0 is retired. drop it Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index a901baf2aaef..9e1071b2181f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -3267,9 +3267,6 @@ void core_link_enable_stream( } } -#if defined(CONFIG_DRM_AMD_DC_DCN3_0) -#endif - /* turn off otg test pattern if enable */ if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, -- cgit v1.2.3 From 86b6037f7608f9b726281252aa1b2a55dd696486 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 11 Dec 2020 20:59:47 +0800 Subject: drm/amdgpu: skip load smu and sdma microcode on sriov for SIENNA_CICHLID skip load smu and sdma fw on sriov due to sos, ta and asd fw have been skipped for SIENNA_CICHLID. V2: move asic check into smu11 Signed-off-by: Stanley.Yang Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 3 +++ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 ++++------ drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 5 +++++ 3 files changed, 12 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 5c4ac176b7e4..f1ba36a094da 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -153,6 +153,9 @@ static int sdma_v5_2_init_microcode(struct amdgpu_device *adev) struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; + if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_SIENNA_CICHLID)) + return 0; + DRM_DEBUG("\n"); switch (adev->asic_type) { diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index cf999b7a2164..8b867a6d52b5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -847,12 +847,10 @@ static int smu_sw_init(void *handle) smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO; - if (!amdgpu_sriov_vf(adev) || (adev->asic_type != CHIP_NAVI12)) { - ret = smu_init_microcode(smu); - if (ret) { - dev_err(adev->dev, "Failed to load smu firmware!\n"); - return ret; - } + ret = smu_init_microcode(smu); + if (ret) { + dev_err(adev->dev, "Failed to load smu firmware!\n"); + return ret; } ret = smu_smc_table_sw_init(smu); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index 0372cb83cdd9..b279dbbbce6b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -91,6 +91,11 @@ int smu_v11_0_init_microcode(struct smu_context *smu) const struct common_firmware_header *header; struct amdgpu_firmware_info *ucode = NULL; + if (amdgpu_sriov_vf(adev) && + ((adev->asic_type == CHIP_NAVI12) || + (adev->asic_type == CHIP_SIENNA_CICHLID))) + return 0; + switch (adev->asic_type) { case CHIP_ARCTURUS: chip_name = "arcturus"; -- cgit v1.2.3 From 20172ff3f0b4eddcdd1cf4ca31a7d922e9b4c662 Mon Sep 17 00:00:00 2001 From: Victor Lu Date: Tue, 24 Nov 2020 10:06:04 -0500 Subject: drm/amd/display: Change pstate expected timeout warning to 180us on linux [Why] There is a warning that triggers when pstate takes too long. Pstate can take up to ~200us on Linux without hanging but it is currently set to 40us. [How] Change the timeout for the warning to be 180us on Linux. Signed-off-by: Victor Lu Reviewed-by: Roman Li Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c index 75637c291e75..6f42d10dd772 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -124,11 +124,11 @@ bool hubbub1_verify_allow_pstate_change_high( * still not asserted, we are probably stuck and going to hang * * TODO: Figure out why it takes ~100us on linux - * pstate takes around ~100us on linux. Unknown currently as to - * why it takes that long on linux + * pstate takes around ~100us (up to 200us) on linux. Unknown currently + * as to why it takes that long on linux */ const unsigned int pstate_wait_timeout_us = 200; - const unsigned int pstate_wait_expected_timeout_us = 40; + const unsigned int pstate_wait_expected_timeout_us = 180; static unsigned int max_sampled_pstate_wait_us; /* data collection */ static bool forced_pstate_allow; /* help with revert wa */ -- cgit v1.2.3 From 41aa4d3ded5cd7fa19cdc5f15fb60b85ed64f083 Mon Sep 17 00:00:00 2001 From: Max Tseng Date: Sat, 21 Nov 2020 20:11:38 +0800 Subject: drm/amd/display: Add missing DP_SEC register definitions and masks [Why] some DP_SEC register defs and masks are missing. [How] add the missing defs and masks. Signed-off-by: Max Tseng Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h | 6 ++++++ drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h | 2 ++ 2 files changed, 8 insertions(+) (limited to 'drivers/gpu/drm/amd') diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h index 9e38c37c1d73..76b334644f9e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h @@ -81,7 +81,9 @@ SRI(DP_MSE_RATE_UPDATE, DP, id), \ SRI(DP_PIXEL_FORMAT, DP, id), \ SRI(DP_SEC_CNTL, DP, id), \ + SRI(DP_SEC_CNTL1, DP, id), \ SRI(DP_SEC_CNTL2, DP, id), \ + SRI(DP_SEC_CNTL5, DP, id), \ SRI(DP_SEC_CNTL6, DP, id), \ SRI(DP_STEER_FIFO, DP, id), \ SRI(DP_VID_M, DP, id), \ @@ -126,7 +128,9 @@ struct dcn10_stream_enc_registers { uint32_t DP_MSE_RATE_UPDATE; uint32_t DP_PIXEL_FORMAT; uint32_t DP_SEC_CNTL; + uint32_t DP_SEC_CNTL1; uint32_t DP_SEC_CNTL2; + uint32_t DP_SEC_CNTL5; uint32_t DP_SEC_CNTL6; uint32_t DP_STEER_FIFO; uint32_t DP_VID_M; @@ -411,6 +415,8 @@ struct dcn10_stream_enc_registers { type DP_SEC_GSP3_ENABLE;\ type DP_SEC_GSP4_ENABLE;\ type DP_SEC_GSP5_ENABLE;\ + type DP_SEC_GSP5_LINE_NUM;\ + type DP_SEC_GSP5_LINE_REFERENCE;\ type DP_SEC_GSP6_ENABLE;\ type DP_SEC_GSP7_ENABLE;\ type DP_SEC_GSP7_PPS;\ diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h index d2a805bd4573..9a881e639709 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h @@ -83,6 +83,8 @@ SE_SF(DIG0_HDMI_METADATA_PACKET_CONTROL, HDMI_METADATA_PACKET_LINE, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, DOLBY_VISION_EN, mask_sh),\ SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, mask_sh)