From 899788efa45bb619787ee692048ae3f1e8c64754 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 19 Jan 2023 09:54:20 +0100 Subject: clk: imx6sll: add proper spdx license identifier This fixes the following error: include/dt-bindings/clock/imx6sll-clock.h:1: warning: Improper SPDX comment style for 'include/dt-bindings/clock/imx6sll-clock.h', please use '/*' instead include/dt-bindings/clock/imx6sll-clock.h:1: warning: Missing or malformed SPDX-License-Identifier tag in line 1 Signed-off-by: Marcel Ziswiler Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230119085421.102804-2-marcel@ziswiler.com --- include/dt-bindings/clock/imx6sll-clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h index f446710fe63d..494fd0c37fb5 100644 --- a/include/dt-bindings/clock/imx6sll-clock.h +++ b/include/dt-bindings/clock/imx6sll-clock.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP. -- cgit v1.2.3 From 8864eac5511b061753133213c8e4dcbb85933892 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 19 Jan 2023 09:54:21 +0100 Subject: dt-bindings: imx8ulp: clock: no spaces before tabs This fixes the following warnings: include/dt-bindings/clock/imx8ulp-clock.h:204: warning: please, no space before tabs include/dt-bindings/clock/imx8ulp-clock.h:215: warning: please, no space before tabs Signed-off-by: Marcel Ziswiler Acked-by: Krzysztof Kozlowski Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230119085421.102804-3-marcel@ziswiler.com --- include/dt-bindings/clock/imx8ulp-clock.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h index 953ecfe8ebcc..827404fadf5c 100644 --- a/include/dt-bindings/clock/imx8ulp-clock.h +++ b/include/dt-bindings/clock/imx8ulp-clock.h @@ -201,7 +201,7 @@ #define IMX8ULP_CLK_SAI7 2 #define IMX8ULP_CLK_SPDIF 3 #define IMX8ULP_CLK_ISI 4 -#define IMX8ULP_CLK_CSI_REGS 5 +#define IMX8ULP_CLK_CSI_REGS 5 #define IMX8ULP_CLK_PCTLD 6 #define IMX8ULP_CLK_CSI 7 #define IMX8ULP_CLK_DSI 8 @@ -212,7 +212,7 @@ #define IMX8ULP_CLK_GPU2D 13 #define IMX8ULP_CLK_GPU3D 14 #define IMX8ULP_CLK_DC_NANO 15 -#define IMX8ULP_CLK_CSI_CLK_UI 16 +#define IMX8ULP_CLK_CSI_CLK_UI 16 #define IMX8ULP_CLK_CSI_CLK_ESC 17 #define IMX8ULP_CLK_RGPIOD 18 #define IMX8ULP_CLK_DMA2_MP 19 -- cgit v1.2.3 From 8bb289bb48b3e2966e8e165a4b9dcbba09573aa9 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:25 +0100 Subject: clk: imx6q: add ethernet refclock mux support Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards since machine code currently overwrites this default. The machine code will be fixed in a separate patch. Signed-off-by: Oleksij Rempel Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230131084642.709385-3-o.rempel@pengutronix.de --- include/dt-bindings/clock/imx6qdl-clock.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index e20c43cc36f6..e5b2a1ba02bc 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -273,6 +273,8 @@ #define IMX6QDL_CLK_MMDC_P0_IPG 263 #define IMX6QDL_CLK_DCIC1 264 #define IMX6QDL_CLK_DCIC2 265 -#define IMX6QDL_CLK_END 266 +#define IMX6QDL_CLK_ENET_REF_SEL 266 +#define IMX6QDL_CLK_ENET_REF_PAD 267 +#define IMX6QDL_CLK_END 268 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ -- cgit v1.2.3 From 5f82bfced6118450cb9ea3f12316568f6fac10ab Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:38 +0100 Subject: clk: imx6ul: fix enet1 gate configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the "i.MX 6UltraLite Applications Processor Reference Manual, Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root of PLL6. It is controlling ENET1 separately. So, instead of this picture (implementation before this patch): fec1 <- enet_ref (divider) <---------------------------, |- pll6_enet (gate) fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ we should have this one (after this patch): fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ With this fix, the RMII reference clock will be turned off, after setting network interface down on each separate interface (ip l s dev eth0 down). Which was not working before, on system with both FECs enabled. Signed-off-by: Oleksij Rempel Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de --- include/dt-bindings/clock/imx6ul-clock.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index 79094338e6f1..b44920f1edb0 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -256,7 +256,8 @@ #define IMX6UL_CLK_GPIO4 247 #define IMX6UL_CLK_GPIO5 248 #define IMX6UL_CLK_MMDC_P1_IPG 249 +#define IMX6UL_CLK_ENET1_REF_125M 250 -#define IMX6UL_CLK_END 250 +#define IMX6UL_CLK_END 251 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ -- cgit v1.2.3 From 4e197ee880c24ecb63f7fe17449b3653bc64b03c Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Tue, 31 Jan 2023 09:46:39 +0100 Subject: clk: imx6ul: add ethernet refclock mux support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add ethernet refclock mux support and set it to internal clock by default. This configuration will not affect existing boards. clock tree before this patch: fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, |- pll6_enet fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ after this patch: fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... `--<> enet1_ref_pad |- pll6_enet fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... `--<> enet2_ref_pad Signed-off-by: Oleksij Rempel Acked-by: Lee Jones Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de --- include/dt-bindings/clock/imx6ul-clock.h | 6 +++++- include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 6 ++++-- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index b44920f1edb0..66239ebc0e23 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -257,7 +257,11 @@ #define IMX6UL_CLK_GPIO5 248 #define IMX6UL_CLK_MMDC_P1_IPG 249 #define IMX6UL_CLK_ENET1_REF_125M 250 +#define IMX6UL_CLK_ENET1_REF_SEL 251 +#define IMX6UL_CLK_ENET1_REF_PAD 252 +#define IMX6UL_CLK_ENET2_REF_SEL 253 +#define IMX6UL_CLK_ENET2_REF_PAD 254 -#define IMX6UL_CLK_END 251 +#define IMX6UL_CLK_END 255 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index d4b5e527a7a3..09c6b3184bb0 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h @@ -451,8 +451,10 @@ #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) /* For imx6ul iomux gpr register field define */ -#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) -#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) +#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) +#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) +#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) +#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) -- cgit v1.2.3