From 7bbb3cc5c816fc167601ce9519adae5eced3ea6d Mon Sep 17 00:00:00 2001 From: Kyungmin Park Date: Wed, 6 Dec 2006 17:13:54 -0800 Subject: ARM: OMAP: 24xx pinmux updates Add some OMAP 24xx pin mux declarations to support: - TUSB 6010 EVM (on H4) - All three full speed USB ports - GPIOs used with USB0 on Apollon and H4 For OMAP2, issue MUX_WARNINGS and debug messages correctly; and make the message look more like the OMAP1 message. Signed-off-by: Kyungmin Park Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- include/asm-arm/arch-omap/mux.h | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index 828cc5c114e1..f1ec2edd4040 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -421,7 +421,9 @@ enum omap24xx_index { /* 24xx clock */ W14_24XX_SYS_CLKOUT, - /* 24xx GPMC wait pin monitoring */ + /* 24xx GPMC chipselects, wait pin monitoring */ + E2_GPMC_NCS2, + L2_GPMC_NCS7, L3_GPMC_WAIT0, N7_GPMC_WAIT1, M1_GPMC_WAIT2, @@ -435,6 +437,7 @@ enum omap24xx_index { /* 24xx GPIO */ M21_242X_GPIO11, + P21_242X_GPIO12, AA10_242X_GPIO13, AA6_242X_GPIO14, AA4_242X_GPIO15, @@ -444,7 +447,9 @@ enum omap24xx_index { Y20_24XX_GPIO60, W4__24XX_GPIO74, M15_24XX_GPIO92, + J15_24XX_GPIO99, V14_24XX_GPIO117, + P14_24XX_GPIO125, /* 242x DBG GPIO */ V4_242X_GPIO49, @@ -486,6 +491,30 @@ enum omap24xx_index { G18_24XX_MMC_CMD_DIR, H15_24XX_MMC_CLKI, + /* Full speed USB */ + J20_24XX_USB0_PUEN, + J19_24XX_USB0_VP, + K20_24XX_USB0_VM, + J18_24XX_USB0_RCV, + K19_24XX_USB0_TXEN, + J14_24XX_USB0_SE0, + K18_24XX_USB0_DAT, + + N14_24XX_USB1_SE0, + W12_24XX_USB1_SE0, + P15_24XX_USB1_DAT, + R13_24XX_USB1_DAT, + W20_24XX_USB1_TXEN, + P13_24XX_USB1_TXEN, + V19_24XX_USB1_RCV, + V12_24XX_USB1_RCV, + + AA10_24XX_USB2_SE0, + Y11_24XX_USB2_DAT, + AA12_24XX_USB2_TXEN, + AA6_24XX_USB2_RCV, + AA4_24XX_USB2_TLLSE0, + /* Keypad GPIO*/ T19_24XX_KBR0, R19_24XX_KBR1, -- cgit v1.2.3 From c7b87f3d5037a35b5c7bb916ffc826be3fcb208d Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 10 May 2007 16:46:13 +0100 Subject: [ARM] ecard: add helper function for setting ecard irq ops Rather than having every driver fiddle about setting its private IRQ operations and data, provide a helper function to contain this functionality in one place. Arrange to remove the driver-private IRQ operations and data when the device is removed from the driver, and remove the driver private code to do this. This fixes potential problems caused by drivers forgetting to remove these hooks. Signed-off-by: Russell King --- include/asm-arm/ecard.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 3a6d3eb27622..8f1000eac91f 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -121,7 +121,7 @@ struct in_ecid { /* Packed card ID information */ typedef struct expansion_card ecard_t; typedef unsigned long *loader_t; -typedef struct { /* Card handler routines */ +typedef struct expansion_card_ops { /* Card handler routines */ void (*irqenable)(ecard_t *ec, int irqnr); void (*irqdisable)(ecard_t *ec, int irqnr); int (*irqpending)(ecard_t *ec); @@ -179,6 +179,8 @@ struct expansion_card { u64 dma_mask; }; +void ecard_setirq(struct expansion_card *ec, const struct expansion_card_ops *ops, void *irq_data); + struct in_chunk_dir { unsigned int start_offset; union { -- cgit v1.2.3 From 10bdaaa0fad620145cf10e2b573266b2d80b44de Mon Sep 17 00:00:00 2001 From: Russell King Date: Thu, 10 May 2007 18:40:51 +0100 Subject: [ARM] ecard: add ecardm_iomap() / ecardm_iounmap() Add devres ecardm_iomap() and ecardm_iounmap() for Acorn expansion cards. Convert all expansion card drivers to use them. Signed-off-by: Russell King --- include/asm-arm/ecard.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h index 8f1000eac91f..684fe0645239 100644 --- a/include/asm-arm/ecard.h +++ b/include/asm-arm/ecard.h @@ -226,6 +226,10 @@ ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed) extern int ecard_request_resources(struct expansion_card *ec); extern void ecard_release_resources(struct expansion_card *ec); +void __iomem *ecardm_iomap(struct expansion_card *ec, unsigned int res, + unsigned long offset, unsigned long maxsize); +#define ecardm_iounmap(__ec, __addr) devm_iounmap(&(__ec)->dev, __addr) + extern struct bus_type ecard_bus_type; #define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) -- cgit v1.2.3 From b8b6970b4fe08397554295b0c5169bec7575f7c9 Mon Sep 17 00:00:00 2001 From: Graeme Gregory Date: Wed, 9 May 2007 15:55:24 +0100 Subject: [ARM] 4365/1: Add AC97 clock to s3c2443 machine This adds the ac97 clock to the s3c2443 machine files. It seems to have been simply missed out previously. Signed-off-by: Graeme Gregory Signed-off-by: Ben Dooks Signed-off-by: Russell King --- include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h index cd9e26568f85..c1414658d1c5 100644 --- a/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h +++ b/include/asm-arm/arch-s3c2410/regs-s3c2443-clock.h @@ -129,6 +129,7 @@ #define S3C2443_PCLKCON_IIC (1<<4) #define S3C2443_PCLKCON_SDI (1<<5) #define S3C2443_PCLKCON_ADC (1<<7) +#define S3C2443_PCLKCON_AC97 (1<<8) #define S3C2443_PCLKCON_IIS (1<<9) #define S3C2443_PCLKCON_PWMT (1<<10) #define S3C2443_PCLKCON_WDT (1<<11) -- cgit v1.2.3 From f75fd965d500d33720948f30d409c6c7729a80af Mon Sep 17 00:00:00 2001 From: Russell King Date: Wed, 9 May 2007 20:21:11 +0100 Subject: [ARM] Fix iop32x/iop33x build arch/arm/plat-iop/io.c:26: error: conflicting types for '__iop3xx_ioremap' Signed-off-by: Russell King --- include/asm-arm/arch-iop13xx/io.h | 2 +- include/asm-arm/arch-iop32x/io.h | 2 +- include/asm-arm/arch-iop33x/io.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h index 7dfff4ad82b3..a6e0f9e6ddcf 100644 --- a/include/asm-arm/arch-iop13xx/io.h +++ b/include/asm-arm/arch-iop13xx/io.h @@ -27,7 +27,7 @@ extern void __iomem * __iop13xx_io(unsigned long io_addr); extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop13xx_iounmap(void __iomem *addr); extern u32 iop13xx_atue_mem_base; diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h index 994f16af5057..958af751a484 100644 --- a/include/asm-arm/arch-iop32x/io.h +++ b/include/asm-arm/arch-iop32x/io.h @@ -14,7 +14,7 @@ #include extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h index 993f7589b29f..fec9c53e2b10 100644 --- a/include/asm-arm/arch-iop33x/io.h +++ b/include/asm-arm/arch-iop33x/io.h @@ -14,7 +14,7 @@ #include extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff -- cgit v1.2.3 From 030f4810e782e541468d36c27e721b582b7820a4 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 13:21:27 +0100 Subject: [ARM] 4369/1: AT91: Fix circular dependency in header files Resolve the circular dependency in the AT91 header files (io.h and hardware.h) by moving the at91_sys_read() and at91_sys_write() functions to io.h Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/hardware.h | 17 ----------------- include/asm-arm/arch-at91/io.h | 18 ++++++++++++++++++ include/asm-arm/arch-at91/irqs.h | 1 + include/asm-arm/arch-at91/uncompress.h | 2 +- 4 files changed, 20 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 28133e0154dd..1c14382dc3f5 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -69,22 +69,5 @@ /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ -#ifndef __ASSEMBLY__ -#include - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif #endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index 401f327ec047..80073fd36b8e 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h @@ -29,4 +29,22 @@ #define __mem_pci(a) (a) +#ifndef __ASSEMBLY__ + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + return __raw_readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + __raw_writel(value, addr + reg_offset); +} + +#endif + #endif diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h index 1ffa3bb9a9c1..1127a3b5e928 100644 --- a/include/asm-arm/arch-at91/irqs.h +++ b/include/asm-arm/arch-at91/irqs.h @@ -21,6 +21,7 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H +#include #include #define NR_AIC_IRQS 32 diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index a193d28304b6..30ac587b3b41 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -21,7 +21,7 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -#include +#include #include /* -- cgit v1.2.3 From 7c6337e225364870e9bf02a3ae277d9fdea483f8 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 30 Apr 2007 19:37:19 +0100 Subject: [ARM] 4303/3: base kernel support for TI DaVinci Add base kernel support for the TI DaVinci platform. This patch only includes interrupts, timers, CPU identification, serial support and basic power and sleep controller init. More drivers to come. Signed-off-by: Kevin Hilman Signed-off-by: Russell King --- include/asm-arm/arch-davinci/common.h | 19 ++++++ include/asm-arm/arch-davinci/debug-macro.S | 21 ++++++ include/asm-arm/arch-davinci/dma.h | 16 +++++ include/asm-arm/arch-davinci/entry-macro.S | 32 +++++++++ include/asm-arm/arch-davinci/hardware.h | 14 ++++ include/asm-arm/arch-davinci/io.h | 79 ++++++++++++++++++++++ include/asm-arm/arch-davinci/irqs.h | 105 +++++++++++++++++++++++++++++ include/asm-arm/arch-davinci/memory.h | 64 ++++++++++++++++++ include/asm-arm/arch-davinci/psc.h | 76 +++++++++++++++++++++ include/asm-arm/arch-davinci/serial.h | 20 ++++++ include/asm-arm/arch-davinci/system.h | 29 ++++++++ include/asm-arm/arch-davinci/timex.h | 17 +++++ include/asm-arm/arch-davinci/uncompress.h | 35 ++++++++++ include/asm-arm/arch-davinci/vmalloc.h | 15 +++++ 14 files changed, 542 insertions(+) create mode 100644 include/asm-arm/arch-davinci/common.h create mode 100644 include/asm-arm/arch-davinci/debug-macro.S create mode 100644 include/asm-arm/arch-davinci/dma.h create mode 100644 include/asm-arm/arch-davinci/entry-macro.S create mode 100644 include/asm-arm/arch-davinci/hardware.h create mode 100644 include/asm-arm/arch-davinci/io.h create mode 100644 include/asm-arm/arch-davinci/irqs.h create mode 100644 include/asm-arm/arch-davinci/memory.h create mode 100644 include/asm-arm/arch-davinci/psc.h create mode 100644 include/asm-arm/arch-davinci/serial.h create mode 100644 include/asm-arm/arch-davinci/system.h create mode 100644 include/asm-arm/arch-davinci/timex.h create mode 100644 include/asm-arm/arch-davinci/uncompress.h create mode 100644 include/asm-arm/arch-davinci/vmalloc.h (limited to 'include') diff --git a/include/asm-arm/arch-davinci/common.h b/include/asm-arm/arch-davinci/common.h new file mode 100644 index 000000000000..a97dfbb15e57 --- /dev/null +++ b/include/asm-arm/arch-davinci/common.h @@ -0,0 +1,19 @@ +/* + * Header for code common to all DaVinci machines. + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef __ARCH_ARM_MACH_DAVINCI_COMMON_H +#define __ARCH_ARM_MACH_DAVINCI_COMMON_H + +struct sys_timer; + +extern struct sys_timer davinci_timer; + +#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */ diff --git a/include/asm-arm/arch-davinci/debug-macro.S b/include/asm-arm/arch-davinci/debug-macro.S new file mode 100644 index 000000000000..e6c0f0d5d062 --- /dev/null +++ b/include/asm-arm/arch-davinci/debug-macro.S @@ -0,0 +1,21 @@ +/* + * Debugging macro for DaVinci + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + moveq \rx, #0x01000000 @ physical base address + movne \rx, #0xfe000000 @ virtual base + orr \rx, \rx, #0x00c20000 @ UART 0 + .endm + +#define UART_SHIFT 2 +#include diff --git a/include/asm-arm/arch-davinci/dma.h b/include/asm-arm/arch-davinci/dma.h new file mode 100644 index 000000000000..8e2f2d0ba667 --- /dev/null +++ b/include/asm-arm/arch-davinci/dma.h @@ -0,0 +1,16 @@ +/* + * DaVinci DMA definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_DMA_H +#define __ASM_ARCH_DMA_H + +#define MAX_DMA_ADDRESS 0xffffffff + +#endif /* __ASM_ARCH_DMA_H */ diff --git a/include/asm-arm/arch-davinci/entry-macro.S b/include/asm-arm/arch-davinci/entry-macro.S new file mode 100644 index 000000000000..3ebfcc5cb58e --- /dev/null +++ b/include/asm-arm/arch-davinci/entry-macro.S @@ -0,0 +1,32 @@ +/* + * Low-level IRQ helper macros for TI DaVinci-based platforms + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IO_ADDRESS(DAVINCI_ARM_INTC_BASE) + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \tmp, [\base, #0x14] + mov \tmp, \tmp, lsr #2 + sub \irqnr, \tmp, #1 + cmp \tmp, #0 + .endm + + .macro irq_prio_table + .endm diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h new file mode 100644 index 000000000000..60362d80229e --- /dev/null +++ b/include/asm-arm/arch-davinci/hardware.h @@ -0,0 +1,14 @@ +/* + * Common hardware definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-davinci/io.h b/include/asm-arm/arch-davinci/io.h new file mode 100644 index 000000000000..e7accb910864 --- /dev/null +++ b/include/asm-arm/arch-davinci/io.h @@ -0,0 +1,79 @@ +/* + * DaVinci IO address definitions + * + * Copied from include/asm/arm/arch-omap/io.h + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * ---------------------------------------------------------------------------- + * I/O mapping + * ---------------------------------------------------------------------------- + */ +#define IO_PHYS 0x01c00000 +#define IO_OFFSET 0xfd000000 /* Virtual IO = 0xfec00000 */ +#define IO_SIZE 0x00400000 +#define IO_VIRT (IO_PHYS + IO_OFFSET) +#define io_p2v(pa) ((pa) + IO_OFFSET) +#define io_v2p(va) ((va) - IO_OFFSET) +#define IO_ADDRESS(x) io_p2v(x) + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define PCIO_BASE 0 +#define __io(a) ((void __iomem *)(PCIO_BASE + (a))) +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#ifndef __ASSEMBLER__ + +/* + * Functions to access the DaVinci IO region + * + * NOTE: - Use davinci_read/write[bwl] for physical register addresses + * - Use __raw_read/write[bwl]() for virtual register addresses + * - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses + * - DO NOT use hardcoded virtual addresses to allow changing the + * IO address space again if needed + */ +#define davinci_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) +#define davinci_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) +#define davinci_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) + +#define davinci_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) +#define davinci_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) +#define davinci_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) + +/* 16 bit uses LDRH/STRH, base +/- offset_8 */ +typedef struct { volatile u16 offset[256]; } __regbase16; +#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \ + ->offset[((vaddr)&0xff)>>1] +#define __REG16(paddr) __REGV16(io_p2v(paddr)) + +/* 8/32 bit uses LDR/STR, base +/- offset_12 */ +typedef struct { volatile u8 offset[4096]; } __regbase8; +#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>0] +#define __REG8(paddr) __REGV8(io_p2v(paddr)) + +typedef struct { volatile u32 offset[4096]; } __regbase32; +#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \ + ->offset[((vaddr)&4095)>>2] + +#define __REG(paddr) __REGV32(io_p2v(paddr)) +#else + +#define __REG(x) (*((volatile unsigned long *)io_p2v(x))) + +#endif /* __ASSEMBLER__ */ +#endif /* __ASM_ARCH_IO_H */ diff --git a/include/asm-arm/arch-davinci/irqs.h b/include/asm-arm/arch-davinci/irqs.h new file mode 100644 index 000000000000..f4c5ca6da9f4 --- /dev/null +++ b/include/asm-arm/arch-davinci/irqs.h @@ -0,0 +1,105 @@ +/* + * DaVinci interrupt controller definitions + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + +/* Base address */ +#define DAVINCI_ARM_INTC_BASE 0x01C48000 + +/* Interrupt lines */ +#define IRQ_VDINT0 0 +#define IRQ_VDINT1 1 +#define IRQ_VDINT2 2 +#define IRQ_HISTINT 3 +#define IRQ_H3AINT 4 +#define IRQ_PRVUINT 5 +#define IRQ_RSZINT 6 +#define IRQ_VFOCINT 7 +#define IRQ_VENCINT 8 +#define IRQ_ASQINT 9 +#define IRQ_IMXINT 10 +#define IRQ_VLCDINT 11 +#define IRQ_USBINT 12 +#define IRQ_EMACINT 13 + +#define IRQ_CCINT0 16 +#define IRQ_CCERRINT 17 +#define IRQ_TCERRINT0 18 +#define IRQ_TCERRINT 19 +#define IRQ_PSCIN 20 + +#define IRQ_IDE 22 +#define IRQ_HPIINT 23 +#define IRQ_MBXINT 24 +#define IRQ_MBRINT 25 +#define IRQ_MMCINT 26 +#define IRQ_SDIOINT 27 +#define IRQ_MSINT 28 +#define IRQ_DDRINT 29 +#define IRQ_AEMIFINT 30 +#define IRQ_VLQINT 31 +#define IRQ_TINT0_TINT12 32 +#define IRQ_TINT0_TINT34 33 +#define IRQ_TINT1_TINT12 34 +#define IRQ_TINT1_TINT34 35 +#define IRQ_PWMINT0 36 +#define IRQ_PWMINT1 37 +#define IRQ_PWMINT2 38 +#define IRQ_I2C 39 +#define IRQ_UARTINT0 40 +#define IRQ_UARTINT1 41 +#define IRQ_UARTINT2 42 +#define IRQ_SPINT0 43 +#define IRQ_SPINT1 44 + +#define IRQ_DSP2ARM0 46 +#define IRQ_DSP2ARM1 47 +#define IRQ_GPIO0 48 +#define IRQ_GPIO1 49 +#define IRQ_GPIO2 50 +#define IRQ_GPIO3 51 +#define IRQ_GPIO4 52 +#define IRQ_GPIO5 53 +#define IRQ_GPIO6 54 +#define IRQ_GPIO7 55 +#define IRQ_GPIOBNK0 56 +#define IRQ_GPIOBNK1 57 +#define IRQ_GPIOBNK2 58 +#define IRQ_GPIOBNK3 59 +#define IRQ_GPIOBNK4 60 +#define IRQ_COMMTX 61 +#define IRQ_COMMRX 62 +#define IRQ_EMUINT 63 + +#define DAVINCI_N_AINTC_IRQ 64 +#define DAVINCI_N_GPIO 71 + +#define NR_IRQS (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO) + +#define ARCH_TIMER_IRQ IRQ_TINT1_TINT34 + +#endif /* __ASM_ARCH_IRQS_H */ diff --git a/include/asm-arm/arch-davinci/memory.h b/include/asm-arm/arch-davinci/memory.h new file mode 100644 index 000000000000..dd1625c23cf4 --- /dev/null +++ b/include/asm-arm/arch-davinci/memory.h @@ -0,0 +1,64 @@ +/* + * DaVinci memory space definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +/************************************************************************** + * Included Files + **************************************************************************/ +#include +#include + +/************************************************************************** + * Definitions + **************************************************************************/ +#define DAVINCI_DDR_BASE 0x80000000 +#define DAVINCI_IRAM_BASE 0x00008000 /* ARM Internal RAM */ + +#define PHYS_OFFSET DAVINCI_DDR_BASE + +/* + * Increase size of DMA-consistent memory region + */ +#define CONSISTENT_DMA_SIZE (14<<20) + +#ifndef __ASSEMBLY__ +/* + * Restrict DMA-able region to workaround silicon bug. The bug + * restricts buffers available for DMA to video hardware to be + * below 128M + */ +static inline void +__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes) +{ + unsigned int sz = (128<<20) >> PAGE_SHIFT; + + if (node != 0) + sz = 0; + + size[1] = size[0] - sz; + size[0] = sz; +} + +#define arch_adjust_zones(node, zone_size, holes) \ + if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes) + +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1) + +#endif + +/* + * Bus address is physical address + */ +#define __virt_to_bus(x) __virt_to_phys(x) +#define __bus_to_virt(x) __phys_to_virt(x) + +#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/include/asm-arm/arch-davinci/psc.h b/include/asm-arm/arch-davinci/psc.h new file mode 100644 index 000000000000..4977aa071e1e --- /dev/null +++ b/include/asm-arm/arch-davinci/psc.h @@ -0,0 +1,76 @@ +/* + * DaVinci Power & Sleep Controller (PSC) defines + * + * Copyright (C) 2006 Texas Instruments. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ +#ifndef __ASM_ARCH_PSC_H +#define __ASM_ARCH_PSC_H + +/* Power and Sleep Controller (PSC) Domains */ +#define DAVINCI_GPSC_ARMDOMAIN 0 +#define DAVINCI_GPSC_DSPDOMAIN 1 + +#define DAVINCI_LPSC_VPSSMSTR 0 +#define DAVINCI_LPSC_VPSSSLV 1 +#define DAVINCI_LPSC_TPCC 2 +#define DAVINCI_LPSC_TPTC0 3 +#define DAVINCI_LPSC_TPTC1 4 +#define DAVINCI_LPSC_EMAC 5 +#define DAVINCI_LPSC_EMAC_WRAPPER 6 +#define DAVINCI_LPSC_MDIO 7 +#define DAVINCI_LPSC_IEEE1394 8 +#define DAVINCI_LPSC_USB 9 +#define DAVINCI_LPSC_ATA 10 +#define DAVINCI_LPSC_VLYNQ 11 +#define DAVINCI_LPSC_UHPI 12 +#define DAVINCI_LPSC_DDR_EMIF 13 +#define DAVINCI_LPSC_AEMIF 14 +#define DAVINCI_LPSC_MMC_SD 15 +#define DAVINCI_LPSC_MEMSTICK 16 +#define DAVINCI_LPSC_McBSP 17 +#define DAVINCI_LPSC_I2C 18 +#define DAVINCI_LPSC_UART0 19 +#define DAVINCI_LPSC_UART1 20 +#define DAVINCI_LPSC_UART2 21 +#define DAVINCI_LPSC_SPI 22 +#define DAVINCI_LPSC_PWM0 23 +#define DAVINCI_LPSC_PWM1 24 +#define DAVINCI_LPSC_PWM2 25 +#define DAVINCI_LPSC_GPIO 26 +#define DAVINCI_LPSC_TIMER0 27 +#define DAVINCI_LPSC_TIMER1 28 +#define DAVINCI_LPSC_TIMER2 29 +#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 +#define DAVINCI_LPSC_ARM 31 +#define DAVINCI_LPSC_SCR2 32 +#define DAVINCI_LPSC_SCR3 33 +#define DAVINCI_LPSC_SCR4 34 +#define DAVINCI_LPSC_CROSSBAR 35 +#define DAVINCI_LPSC_CFG27 36 +#define DAVINCI_LPSC_CFG3 37 +#define DAVINCI_LPSC_CFG5 38 +#define DAVINCI_LPSC_GEM 39 +#define DAVINCI_LPSC_IMCOP 40 + +#endif /* __ASM_ARCH_PSC_H */ diff --git a/include/asm-arm/arch-davinci/serial.h b/include/asm-arm/arch-davinci/serial.h new file mode 100644 index 000000000000..ed418ef76805 --- /dev/null +++ b/include/asm-arm/arch-davinci/serial.h @@ -0,0 +1,20 @@ +/* + * DaVinci serial device definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SERIAL_H +#define __ASM_ARCH_SERIAL_H + +#include + +#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) +#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) +#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) + +#endif /* __ASM_ARCH_SERIAL_H */ diff --git a/include/asm-arm/arch-davinci/system.h b/include/asm-arm/arch-davinci/system.h new file mode 100644 index 000000000000..440ac515804b --- /dev/null +++ b/include/asm-arm/arch-davinci/system.h @@ -0,0 +1,29 @@ +/* + * DaVinci system defines + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_SYSTEM_H +#define __ASM_ARCH_SYSTEM_H + +#include +#include + +extern void davinci_watchdog_reset(void); + +static void arch_idle(void) +{ + cpu_do_idle(); +} + +static void arch_reset(char mode) +{ + davinci_watchdog_reset(); +} + +#endif /* __ASM_ARCH_SYSTEM_H */ diff --git a/include/asm-arm/arch-davinci/timex.h b/include/asm-arm/arch-davinci/timex.h new file mode 100644 index 000000000000..52827567841d --- /dev/null +++ b/include/asm-arm/arch-davinci/timex.h @@ -0,0 +1,17 @@ +/* + * DaVinci timer defines + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#ifndef __ASM_ARCH_TIMEX_H +#define __ASM_ARCH_TIMEX_H + +/* The source frequency for the timers is the 27MHz clock */ +#define CLOCK_TICK_RATE 27000000 + +#endif /* __ASM_ARCH_TIMEX_H__ */ diff --git a/include/asm-arm/arch-davinci/uncompress.h b/include/asm-arm/arch-davinci/uncompress.h new file mode 100644 index 000000000000..f6d1570f7206 --- /dev/null +++ b/include/asm-arm/arch-davinci/uncompress.h @@ -0,0 +1,35 @@ +/* + * Serial port stubs for kernel decompress status messages + * + * Author: Anant Gole + * (C) Copyright (C) 2006, Texas Instruments, Inc + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include +#include +#include + +/* PORT_16C550A, in polled non-fifo mode */ + +static void putc(char c) +{ + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); + uart[UART_TX] = c; +} + +static inline void flush(void) +{ + volatile u32 *uart = (volatile void *) DAVINCI_UART0_BASE; + while (!(uart[UART_LSR] & UART_LSR_THRE)) + barrier(); +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/include/asm-arm/arch-davinci/vmalloc.h b/include/asm-arm/arch-davinci/vmalloc.h new file mode 100644 index 000000000000..9b47fa89b333 --- /dev/null +++ b/include/asm-arm/arch-davinci/vmalloc.h @@ -0,0 +1,15 @@ +/* + * DaVinci vmalloc definitions + * + * Author: Kevin Hilman, MontaVista Software, Inc. + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ +#include +#include + +/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */ +#define VMALLOC_END (IO_VIRT - (2<<20)) -- cgit v1.2.3 From 2fd0237538480c8d704c385b6f9abc3f6c46b760 Mon Sep 17 00:00:00 2001 From: Daniel Wolstenholme Date: Thu, 10 May 2007 22:33:02 -0700 Subject: [ARM] iop13xx: msi support Enable devices to signal interrupts via PCI memory cycles. rev6: * fix enable/disable typo, Michael Ellerman rev5: * fix up ack, enable, and disable for iop13xx_msi_chip rev4: * move smp compile fix to separate patch * use dynamic_irq_init in create_irq() * hookup mask/unmask routines in iop13xx_msi_chip rev3: * change msi.c to use linux/smp.h instead of asm/smp.h * call dynamic_irq_cleanup at destroy_irq time rev2: * destroy_irq did not take the full 128 bits of msi_irq_in_use into account * added missing '&' for calls to test_and_set_bit and clear_bit [ebiederm@xmission.com: review comments/suggestions] [dan.j.williams@intel.com: cleanups/forward port to 2.6-git] Signed-off-by: Daniel Wolstenholme Signed-off-by: Dan Williams Acked-by: Eric W. Biederman Signed-off-by: Andrew Morton Signed-off-by: Russell King --- include/asm-arm/arch-iop13xx/iop13xx.h | 29 +++++++++++++++++++++++++++++ include/asm-arm/arch-iop13xx/irqs.h | 8 +++++++- include/asm-arm/arch-iop13xx/msi.h | 11 +++++++++++ 3 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 include/asm-arm/arch-iop13xx/msi.h (limited to 'include') diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h index 85707e9c3325..e6736c3d1f7f 100644 --- a/include/asm-arm/arch-iop13xx/iop13xx.h +++ b/include/asm-arm/arch-iop13xx/iop13xx.h @@ -181,6 +181,7 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200 #define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400 #define IOP13XX_PBI_PMMR_OFFSET 0x00001580 +#define IOP13XX_MU_PMMR_OFFSET 0x00004000 #define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188 #define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188) @@ -412,6 +413,34 @@ static inline int iop13xx_cpu_id(void) #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7) /*=======================================================================*/ +/*============================MESSAGING UNIT=============================*/ +#define IOP13XX_MU_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\ + (ofs)) + +#define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10) +#define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14) +#define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18) +#define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C) +#define IOP13XX_MU_IDR IOP13XX_MU_OFFSET(0x20) +#define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24) +#define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28) +#define IOP13XX_MU_ODR IOP13XX_MU_OFFSET(0x2C) +#define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30) +#define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34) +#define IOP13XX_MU_IRCSR IOP13XX_MU_OFFSET(0x38) +#define IOP13XX_MU_ORCSR IOP13XX_MU_OFFSET(0x3C) +#define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48) +#define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50) +#define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54) +#define IOP13XX_MU_MUBAR IOP13XX_MU_OFFSET(0x84) + +#define IOP13XX_MU_WINDOW_SIZE (8 * 1024) +#define IOP13XX_MU_BASE_PHYS (0xff000000) +#define IOP13XX_MU_BASE_PCI (0xff000000) +#define IOP13XX_MU_MIMR_PCI (IOP13XX_MU_BASE_PCI + 0x48) +#define IOP13XX_MU_MIMR_CORE_SELECT (15) +/*=======================================================================*/ + /*==============================ADMA UNITS===============================*/ #define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9)) #define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0) diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h index 5c6fac2a4004..054e7acb5bfa 100644 --- a/include/asm-arm/arch-iop13xx/irqs.h +++ b/include/asm-arm/arch-iop13xx/irqs.h @@ -168,7 +168,7 @@ static inline u32 read_intpnd_3(void) #define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */ #define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */ #define IRQ_IOP13XX_RSVD_112 (112) /* 16 */ -#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */ +#define IRQ_IOP13XX_INBD_MSI (113) /* 17 */ #define IRQ_IOP13XX_RSVD_114 (114) /* 18 */ #define IRQ_IOP13XX_RSVD_115 (115) /* 19 */ #define IRQ_IOP13XX_RSVD_116 (116) /* 20 */ @@ -184,7 +184,13 @@ static inline u32 read_intpnd_3(void) #define IRQ_IOP13XX_RSVD_126 (126) /* 30 */ #define IRQ_IOP13XX_HPI (127) /* 31 */ +#ifdef CONFIG_PCI_MSI +#define IRQ_IOP13XX_MSI_0 (IRQ_IOP13XX_HPI + 1) +#define NR_IOP13XX_IRQS (IRQ_IOP13XX_MSI_0 + 128) +#else #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1) +#endif + #define NR_IRQS NR_IOP13XX_IRQS #endif /* _IOP13XX_IRQ_H_ */ diff --git a/include/asm-arm/arch-iop13xx/msi.h b/include/asm-arm/arch-iop13xx/msi.h new file mode 100644 index 000000000000..b80c5ae17e99 --- /dev/null +++ b/include/asm-arm/arch-iop13xx/msi.h @@ -0,0 +1,11 @@ +#ifndef _IOP13XX_MSI_H_ +#define _IOP13XX_MSI_H_ +#ifdef CONFIG_PCI_MSI +void iop13xx_msi_init(void); +#else +static inline void iop13xx_msi_init(void) +{ + return; +} +#endif +#endif -- cgit v1.2.3 From 877d7720f5f67793b9b6027840d2c88ea25dc4c8 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 20:49:56 +0100 Subject: [ARM] 4370/3: AT91: Support for Atmel AT91SAM9RL processors. Add support for Atmel's new AT91SAM9RL range of processors. Includes similar peripherals as other AT91SAM9 processors, but with a High-speed USB controller and various sizes of internal SRAM. Signed-off-by: Nicolas Ferre Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-at91/at91sam9rl.h | 110 ++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91sam9rl_matrix.h | 96 ++++++++++++++++++++++ include/asm-arm/arch-at91/cpu.h | 9 +++ include/asm-arm/arch-at91/hardware.h | 2 + include/asm-arm/arch-at91/timex.h | 5 ++ include/asm-avr32/arch-at32ap/cpu.h | 1 + 6 files changed, 223 insertions(+) create mode 100644 include/asm-arm/arch-at91/at91sam9rl.h create mode 100644 include/asm-arm/arch-at91/at91sam9rl_matrix.h (limited to 'include') diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h new file mode 100644 index 000000000000..8a9708a370c6 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -0,0 +1,110 @@ +/* + * include/asm-arm/arch-at91/at91sam9260.h + * + * Copyright (C) 2007 Atmel Corporation + * + * Common definitions. + * Based on AT91SAM9RL datasheet revision A. (Preliminary) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef AT91SAM9RL_H +#define AT91SAM9RL_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Controller */ +#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ +#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ +#define AT91SAM9RL_ID_US0 6 /* USART 0 */ +#define AT91SAM9RL_ID_US1 7 /* USART 1 */ +#define AT91SAM9RL_ID_US2 8 /* USART 2 */ +#define AT91SAM9RL_ID_US3 9 /* USART 3 */ +#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ +#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ +#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ +#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ +#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ +#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ +#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ +#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ +#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ +#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ +#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ +#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ +#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ + + +/* + * User Peripheral physical base addresses. + */ +#define AT91SAM9RL_BASE_TCB0 0xfffa0000 +#define AT91SAM9RL_BASE_TC0 0xfffa0000 +#define AT91SAM9RL_BASE_TC1 0xfffa0040 +#define AT91SAM9RL_BASE_TC2 0xfffa0080 +#define AT91SAM9RL_BASE_MCI 0xfffa4000 +#define AT91SAM9RL_BASE_TWI0 0xfffa8000 +#define AT91SAM9RL_BASE_TWI1 0xfffac000 +#define AT91SAM9RL_BASE_US0 0xfffb0000 +#define AT91SAM9RL_BASE_US1 0xfffb4000 +#define AT91SAM9RL_BASE_US2 0xfffb8000 +#define AT91SAM9RL_BASE_US3 0xfffbc000 +#define AT91SAM9RL_BASE_SSC0 0xfffc0000 +#define AT91SAM9RL_BASE_SSC1 0xfffc4000 +#define AT91SAM9RL_BASE_PWMC 0xfffc8000 +#define AT91SAM9RL_BASE_SPI 0xfffcc000 +#define AT91SAM9RL_BASE_TSC 0xfffd0000 +#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 +#define AT91SAM9RL_BASE_AC97C 0xfffd8000 +#define AT91_BASE_SYS 0xffffc000 + + +/* + * System Peripherals (offset from AT91_BASE_SYS) + */ +#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) +#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) +#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) +#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) +#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) +#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) +#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) +#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) +#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) +#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) +#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) +#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) +#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) +#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) +#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) +#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) +#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) +#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) +#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) + + +/* + * Internal Memory. + */ +#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ + +#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ +#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ + +#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ +#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ + +#endif diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h new file mode 100644 index 000000000000..b15f11b7c08d --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h @@ -0,0 +1,96 @@ +/* + * include/asm-arm/arch-at91/at91sam9rl_matrix.h + * + * Copyright (C) 2007 Atmel Corporation + * + * Memory Controllers (MATRIX, EBI) - System peripherals registers. + * Based on AT91SAM9RL datasheet revision A. (Preliminary) + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive for + * more details. + */ + +#ifndef AT91SAM9RL_MATRIX_H +#define AT91SAM9RL_MATRIX_H + +#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ +#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ +#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ +#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ +#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ +#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ +#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ +#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ +#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ +#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ +#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ +#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ +#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ +#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ +#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ +#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ +#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ +#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ +#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ +#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ +#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ +#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ +#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ +#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ +#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ + +#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ +#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ +#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#define AT91_MATRIX_RCB2 (1 << 2) +#define AT91_MATRIX_RCB3 (1 << 3) +#define AT91_MATRIX_RCB4 (1 << 4) +#define AT91_MATRIX_RCB5 (1 << 5) + +#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ +#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ +#define AT91_MATRIX_ITCM_0 (0 << 0) +#define AT91_MATRIX_ITCM_16 (5 << 0) +#define AT91_MATRIX_ITCM_32 (6 << 0) +#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ +#define AT91_MATRIX_DTCM_0 (0 << 4) +#define AT91_MATRIX_DTCM_16 (5 << 4) +#define AT91_MATRIX_DTCM_32 (6 << 4) + +#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ +#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ +#define AT91_MATRIX_CS1A_SMC (0 << 1) +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ +#define AT91_MATRIX_CS3A_SMC (0 << 3) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ +#define AT91_MATRIX_CS4A_SMC (0 << 4) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ +#define AT91_MATRIX_CS5A_SMC (0 << 5) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) + + +#endif diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h index 7ef4eebe9f8e..ef93c30a9c5f 100644 --- a/include/asm-arm/arch-at91/cpu.h +++ b/include/asm-arm/arch-at91/cpu.h @@ -26,6 +26,8 @@ #define ARCH_ID_AT91SAM9XE256 0x329a93a0 #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 +#define ARCH_ID_AT91SAM9RL64 0x019b03a0 + static inline unsigned long at91_cpu_identify(void) { return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); @@ -68,6 +70,13 @@ static inline unsigned long at91_arch_identify(void) #define cpu_is_at91sam9263() (0) #endif +#ifdef CONFIG_ARCH_AT91SAM9RL +#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) +#else +#define cpu_is_at91sam9rl() (0) +#endif + + /* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers. diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 28133e0154dd..0e51ad224eaa 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -24,6 +24,8 @@ #include #elif defined(CONFIG_ARCH_AT91SAM9263) #include +#elif defined(CONFIG_ARCH_AT91SAM9RL) +#include #else #error "Unsupported AT91 processor" #endif diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h index f41636d607a2..2df1ee12dfb7 100644 --- a/include/asm-arm/arch-at91/timex.h +++ b/include/asm-arm/arch-at91/timex.h @@ -37,6 +37,11 @@ #define AT91SAM9_MASTER_CLOCK 99959500 #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) +#elif defined(CONFIG_ARCH_AT91SAM9RL) + +#define AT91SAM9_MASTER_CLOCK 100000000 +#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) + #endif #endif diff --git a/include/asm-avr32/arch-at32ap/cpu.h b/include/asm-avr32/arch-at32ap/cpu.h index 2bdc5bd6f793..a762f42cbb71 100644 --- a/include/asm-avr32/arch-at32ap/cpu.h +++ b/include/asm-avr32/arch-at32ap/cpu.h @@ -29,5 +29,6 @@ #define cpu_is_at91sam9260() (0) #define cpu_is_at91sam9261() (0) #define cpu_is_at91sam9263() (0) +#define cpu_is_at91sam9rl() (0) #endif /* __ASM_ARCH_CPU_H */ -- cgit v1.2.3 From 54cb128037de499ea81626b0f37f9bb90e8db3d3 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 20:09:41 +0100 Subject: [ARM] 4372/1: Define byte sizes in asm-arm/sizes.h Define SZ_512, SZ_256 and SZ_16 in asm-arm/sizes.h. Remove the definitions from the at91*_devices.c files. (Dependent on ARM patch #4370/2) Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/sizes.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/asm-arm/sizes.h b/include/asm-arm/sizes.h index 7f50ae0edf1b..503843db1565 100644 --- a/include/asm-arm/sizes.h +++ b/include/asm-arm/sizes.h @@ -24,6 +24,10 @@ #define __sizes_h 1 /* handy sizes */ +#define SZ_16 0x00000010 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + #define SZ_1K 0x00000400 #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 -- cgit v1.2.3 From c53c9cf60e49119e97d38390849cac5b2f0a0981 Mon Sep 17 00:00:00 2001 From: Andrew Victor Date: Fri, 11 May 2007 21:01:28 +0100 Subject: [ARM] 4331/3: Support for Micrel/Kendin KS8695 processor Add core support for the Kendin/Micrel KS8695 processor family. It is an ARM922-T based SoC with integrated USART, 4-port Ethernet Switch, WAN Ethernet port, and optional PCI Host bridge, etc. http://www.micrel.com/page.do?page=product-info/sys_on_chip.jsp This patch is based on earlier patches from Lennert Buytenhek, Ben Dooks and Greg Ungerer posted to the arm-linux-kernel mailing list in March 2006; and Micrel's 2.6.9 port. Signed-off-by: Andrew Victor Signed-off-by: Russell King --- include/asm-arm/arch-ks8695/debug-macro.S | 38 ++++++++++++ include/asm-arm/arch-ks8695/devices.h | 32 ++++++++++ include/asm-arm/arch-ks8695/dma.h | 17 ++++++ include/asm-arm/arch-ks8695/entry-macro.S | 53 +++++++++++++++++ include/asm-arm/arch-ks8695/hardware.h | 49 ++++++++++++++++ include/asm-arm/arch-ks8695/io.h | 19 ++++++ include/asm-arm/arch-ks8695/irqs.h | 54 +++++++++++++++++ include/asm-arm/arch-ks8695/memory.h | 49 ++++++++++++++++ include/asm-arm/arch-ks8695/regs-gpio.h | 53 +++++++++++++++++ include/asm-arm/arch-ks8695/regs-hpna.h | 25 ++++++++ include/asm-arm/arch-ks8695/regs-irq.h | 41 +++++++++++++ include/asm-arm/arch-ks8695/regs-lan.h | 65 +++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-mem.h | 89 ++++++++++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-misc.h | 97 +++++++++++++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-pci.h | 53 +++++++++++++++++ include/asm-arm/arch-ks8695/regs-switch.h | 66 +++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-sys.h | 34 +++++++++++ include/asm-arm/arch-ks8695/regs-timer.h | 40 +++++++++++++ include/asm-arm/arch-ks8695/regs-uart.h | 92 +++++++++++++++++++++++++++++ include/asm-arm/arch-ks8695/regs-wan.h | 65 +++++++++++++++++++++ include/asm-arm/arch-ks8695/system.h | 48 +++++++++++++++ include/asm-arm/arch-ks8695/timex.h | 20 +++++++ include/asm-arm/arch-ks8695/uncompress.h | 37 ++++++++++++ include/asm-arm/arch-ks8695/vmalloc.h | 19 ++++++ 24 files changed, 1155 insertions(+) create mode 100644 include/asm-arm/arch-ks8695/debug-macro.S create mode 100644 include/asm-arm/arch-ks8695/devices.h create mode 100644 include/asm-arm/arch-ks8695/dma.h create mode 100644 include/asm-arm/arch-ks8695/entry-macro.S create mode 100644 include/asm-arm/arch-ks8695/hardware.h create mode 100644 include/asm-arm/arch-ks8695/io.h create mode 100644 include/asm-arm/arch-ks8695/irqs.h create mode 100644 include/asm-arm/arch-ks8695/memory.h create mode 100644 include/asm-arm/arch-ks8695/regs-gpio.h create mode 100644 include/asm-arm/arch-ks8695/regs-hpna.h create mode 100644 include/asm-arm/arch-ks8695/regs-irq.h create mode 100644 include/asm-arm/arch-ks8695/regs-lan.h create mode 100644 include/asm-arm/arch-ks8695/regs-mem.h create mode 100644 include/asm-arm/arch-ks8695/regs-misc.h create mode 100644 include/asm-arm/arch-ks8695/regs-pci.h create mode 100644 include/asm-arm/arch-ks8695/regs-switch.h create mode 100644 include/asm-arm/arch-ks8695/regs-sys.h create mode 100644 include/asm-arm/arch-ks8695/regs-timer.h create mode 100644 include/asm-arm/arch-ks8695/regs-uart.h create mode 100644 include/asm-arm/arch-ks8695/regs-wan.h create mode 100644 include/asm-arm/arch-ks8695/system.h create mode 100644 include/asm-arm/arch-ks8695/timex.h create mode 100644 include/asm-arm/arch-ks8695/uncompress.h create mode 100644 include/asm-arm/arch-ks8695/vmalloc.h (limited to 'include') diff --git a/include/asm-arm/arch-ks8695/debug-macro.S b/include/asm-arm/arch-ks8695/debug-macro.S new file mode 100644 index 000000000000..cd5f2fb1f06e --- /dev/null +++ b/include/asm-arm/arch-ks8695/debug-macro.S @@ -0,0 +1,38 @@ +/* + * include/asm-arm/arch-ks8695/debug-macro.S + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Debug macros + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + + .macro addruart, rx + mrc p15, 0, \rx, c1, c0 + tst \rx, #1 @ MMU enabled? + ldreq \rx, =KS8695_UART_PA @ physical base address + ldrne \rx, =KS8695_UART_VA @ virtual base address + .endm + + .macro senduart, rd, rx + str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register + .endm + + .macro busyuart, rd, rx +1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register + tst \rd, #URLS_URTE @ Holding & Shift registers empty? + beq 1001b + .endm + + .macro waituart, rd, rx +1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register + tst \rd, #URLS_URTHRE @ Holding Register empty? + beq 1001b + .endm diff --git a/include/asm-arm/arch-ks8695/devices.h b/include/asm-arm/arch-ks8695/devices.h new file mode 100644 index 000000000000..b0364dce463f --- /dev/null +++ b/include/asm-arm/arch-ks8695/devices.h @@ -0,0 +1,32 @@ +/* + * include/asm-arm/arch-ks8695/devices.h + * + * Copyright (C) 2006 Andrew Victor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_DEVICES_H +#define __ASM_ARCH_DEVICES_H + +#include + + /* Ethernet */ +extern void __init ks8695_add_device_wan(void); +extern void __init ks8695_add_device_lan(void); +extern void __init ks8695_add_device_hpna(void); + + /* PCI */ +#define KS8695_MODE_PCI 0 +#define KS8695_MODE_MINIPCI 1 +#define KS8695_MODE_CARDBUS 2 + +struct ks8695_pci_cfg { + short mode; + int (*map_irq)(struct pci_dev *, u8, u8); +}; +extern __init void ks8695_init_pci(struct ks8695_pci_cfg *); + +#endif diff --git a/include/asm-arm/arch-ks8695/dma.h b/include/asm-arm/arch-ks8695/dma.h new file mode 100644 index 000000000000..e5159ed42a4b --- /dev/null +++ b/include/asm-arm/arch-ks8695/dma.h @@ -0,0 +1,17 @@ +/* + * include/asm-arm/arch-ks8695/dma.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ diff --git a/include/asm-arm/arch-ks8695/entry-macro.S b/include/asm-arm/arch-ks8695/entry-macro.S new file mode 100644 index 000000000000..e34bdf85920e --- /dev/null +++ b/include/asm-arm/arch-ks8695/entry-macro.S @@ -0,0 +1,53 @@ +/* + * include/asm-arm/arch-ks8695/entry-macro.S + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * Low-level IRQ helper macros for KS8695 + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. +*/ + +#include +#include + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =KS8695_IRQ_VA @ Base address of interrupt controller + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + ldr \irqstat, [\base, #KS8695_INTMS] @ Mask Status register + + teq \irqstat, #0 + beq 1001f + + mov \irqnr, #0 + + tst \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tsteq \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tsteq \irqstat, #0xff + moveq \irqstat, \irqstat, lsr #8 + addeq \irqnr, \irqnr, #8 + tst \irqstat, #0x0f + moveq \irqstat, \irqstat, lsr #4 + addeq \irqnr, \irqnr, #4 + tst \irqstat, #0x03 + moveq \irqstat, \irqstat, lsr #2 + addeq \irqnr, \irqnr, #2 + tst \irqstat, #0x01 + addeqs \irqnr, \irqnr, #1 +1001: + .endm diff --git a/include/asm-arm/arch-ks8695/hardware.h b/include/asm-arm/arch-ks8695/hardware.h new file mode 100644 index 000000000000..cb732bff3288 --- /dev/null +++ b/include/asm-arm/arch-ks8695/hardware.h @@ -0,0 +1,49 @@ +/* + * include/asm-arm/arch-ks8695/hardware.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Memory Map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +/* + * Physical RAM address. + */ +#define KS8695_SDRAM_PA 0x00000000 + + +/* + * We map an entire MiB with the System Configuration Registers in even + * though only 64KiB is needed. This makes it easier for use with the + * head debug code as the initial MMU setup only deals in L1 sections. + */ +#define KS8695_IO_PA 0x03F00000 +#define KS8695_IO_VA 0xF0000000 +#define KS8695_IO_SIZE SZ_1M + +#define KS8695_PCIMEM_PA 0x60000000 +#define KS8695_PCIMEM_SIZE SZ_512M + +#define KS8695_PCIIO_PA 0x80000000 +#define KS8695_PCIIO_SIZE SZ_64K + + +/* + * PCI support + */ +#define pcibios_assign_all_busses() 1 + +#define PCIBIOS_MIN_IO 0 +#define PCIBIOS_MIN_MEM 0 + +#endif diff --git a/include/asm-arm/arch-ks8695/io.h b/include/asm-arm/arch-ks8695/io.h new file mode 100644 index 000000000000..8edc4bd6aadf --- /dev/null +++ b/include/asm-arm/arch-ks8695/io.h @@ -0,0 +1,19 @@ +/* + * include/asm-arm/arch-ks8695/io.h + * + * Copyright (C) 2006 Andrew Victor + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(a)) +#define __mem_pci(a) (a) + +#endif diff --git a/include/asm-arm/arch-ks8695/irqs.h b/include/asm-arm/arch-ks8695/irqs.h new file mode 100644 index 000000000000..8b1c4fe96a81 --- /dev/null +++ b/include/asm-arm/arch-ks8695/irqs.h @@ -0,0 +1,54 @@ +/* + * linux/include/asm-arm/arch-ks8695/irqs.h + * + * Copyright (C) 2006 Simtec Electronics + * Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_IRQS_H +#define __ASM_ARCH_IRQS_H + + +#define NR_IRQS 32 + +/* + * IRQ definitions + */ +#define KS8695_IRQ_COMM_RX 0 +#define KS8695_IRQ_COMM_TX 1 +#define KS8695_IRQ_EXTERN0 2 +#define KS8695_IRQ_EXTERN1 3 +#define KS8695_IRQ_EXTERN2 4 +#define KS8695_IRQ_EXTERN3 5 +#define KS8695_IRQ_TIMER0 6 +#define KS8695_IRQ_TIMER1 7 +#define KS8695_IRQ_UART_TX