path: root/arch/arm/boot/dts/st/stm32mp131.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
 */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp13-clks.h>
#include <dt-bindings/reset/stm32mp13-resets.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>;
		interrupt-parent = <&intc>;
	};

	firmware {
		optee {
			method = "smc";
			compatible = "linaro,optee-tz";
			interrupt-parent = <&intc>;
			interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
		};

		scmi: scmi {
			compatible = "linaro,scmi-optee";
			#address-cells = <1>;
			#size-cells = <0>;
			linaro,optee-channel-id = <0>;

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};

			scmi_reset: protocol@16 {
				reg = <0x16>;
				#reset-cells = <1>;
			};

			scmi_voltd: protocol@17 {
				reg = <0x17>;

				scmi_regu: regulators {
					#address-cells = <1>;
					#size-cells = <0>;

					scmi_reg11: regulator@0 {
						reg = <VOLTD_SCMI_REG11>;
						regulator-name = "reg11";
					};
					scmi_reg18: regulator@1 {
						reg = <VOLTD_SCMI_REG18>;
						regulator-name = "reg18";
					};
					scmi_usb33: regulator@2 {
						reg = <VOLTD_SCMI_USB33>;
						regulator-name = "usb33";
					};
				};
			};
		};
	};

	intc: interrupt-controller@a0021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xa0021000 0x1000>,
		      <0xa0022000 0x2000>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-parent = <&intc>;
		always-on;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		timers2: timer@40000000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global";
			clocks = <&rcc TIM2_K>;
			clock-names = "int";
			dmas = <&dmamux1 18 0x400 0x1>,
			       <&dmamux1 19 0x400 0x1>,
			       <&dmamux1 20 0x400 0x1>,
			       <&dmamux1 21 0x400 0x1>,
			       <&dmamux1 22 0x400 0x1>;
			dma-names = "ch1", "ch2", "ch3", "ch4", "up";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@1 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <1>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-timer-counter";
				status = "disabled";
			};
		};

		timers3: timer@40001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40001000 0x400>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global";
			clocks = <&rcc TIM3_K>;
			clock-names = "int";
			dmas = <&dmamux1 23 0x400 0x1>,
			       <&dmamux1 24 0x400 0x1>,
			       <&dmamux1 25 0x400 0x1>,
			       <&dmamux1 26 0x400 0x1>,
			       <&dmamux1 27 0x400 0x1>,
			       <&dmamux1 28 0x400 0x1>;
			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@2 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <2>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-timer-counter";
				status = "disabled";
			};
		};

		timers4: timer@40002000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40002000 0x400>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global";
			clocks = <&rcc TIM4_K>;
			clock-names = "int";
			dmas = <&dmamux1 29 0x400 0x1>,
			       <&dmamux1 30 0x400 0x1>,
			       <&dmamux1 31 0x400 0x1>,
			       <&dmamux1 32 0x400 0x1>;
			dma-names = "ch1", "ch2", "ch3", "up";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@3 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <3>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-timer-counter";
				status = "disabled";
			};
		};

		timers5: timer@40003000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40003000 0x400>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global";
			clocks = <&rcc TIM5_K>;
			clock-names = "int";
			dmas = <&dmamux1 55 0x400 0x1>,
			       <&dmamux1 56 0x400 0x1>,
			       <&dmamux1 57 0x400 0x1>,
			       <&dmamux1 58 0x400 0x1>,
			       <&dmamux1 59 0x400 0x1>,
			       <&dmamux1 60 0x400 0x1>;
			dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				#pwm-cells = <3>;
				status = "disabled";
			};

			timer@4 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <4>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-timer-counter";
				status = "disabled";
			};
		};

		timers6: timer@40004000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40004000 0x400>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global";
			clocks = <&rcc TIM6_K>;
			clock-names = "int";
			dmas = <&dmamux1 69 0x400 0x1>;
			dma-names = "up";
			status = "disabled";

			timer@5 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <5>;
				status = "disabled";
			};
		};

		timers7: timer@40005000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40005000 0x400>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "global";
			clocks = <&rcc TIM7_K>;
			clock-names = "int";
			dmas = <&dmamux1 70 0x400 0x1>;
			dma-names = "up";
			status = "disabled";

			timer@6 {
				compatible = "st,stm32h7-timer-trigger";
				reg = <6>;
				status = "disabled";
			};
		};

		lptimer1: timer@40009000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-lptimer";
			reg = <0x40009000 0x400>;
			interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc LPTIM1_K>;
			clock-names = "mux";
			wakeup-source;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm-lp";
				#pwm-cells = <3>;
				status = "disabled";
			};

			trigger@0 {
				compatible = "st,stm32-lptimer-trigger";
				reg = <0>;
				status = "disabled";
			};

			counter {
				compatible = "st,stm32-lptimer-counter";
				status = "disabled";
			};

			timer {
				compatible = "st,stm32-lptimer-timer";
				status = "disabled";
			};
		};

		i2s2: audio-controller@4000b000 {
			compatible = "st,stm32h7-i2s";
			reg = <0x4000b000 0x400>;
			#sound-dai-cells = <0>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmamux1 39 0x400 0x01>,
			       <&dmamux1 40 0x400 0x01>;
			dma-na