path: root/drivers/accel/ivpu/ivpu_hw_40xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2020-2023 Intel Corporation
 */

#include "ivpu_drv.h"
#include "ivpu_fw.h"
#include "ivpu_hw.h"
#include "ivpu_hw_40xx_reg.h"
#include "ivpu_hw_reg_io.h"
#include "ivpu_ipc.h"
#include "ivpu_mmu.h"
#include "ivpu_pm.h"

#include <linux/dmi.h>

#define TILE_MAX_NUM                 6
#define TILE_MAX_MASK                0x3f

#define LNL_HW_ID                    0x4040

#define SKU_TILE_SHIFT               0u
#define SKU_TILE_MASK                0x0000ffffu
#define SKU_HW_ID_SHIFT              16u
#define SKU_HW_ID_MASK               0xffff0000u

#define PLL_CONFIG_DEFAULT           0x1
#define PLL_CDYN_DEFAULT             0x80
#define PLL_EPP_DEFAULT              0x80
#define PLL_REF_CLK_FREQ	     (50 * 1000000)
#define PLL_RATIO_TO_FREQ(x)	     ((x) * PLL_REF_CLK_FREQ)

#define PLL_PROFILING_FREQ_DEFAULT   38400000
#define PLL_PROFILING_FREQ_HIGH      400000000

#define TIM_SAFE_ENABLE		     0xf1d0dead
#define TIM_WATCHDOG_RESET_VALUE     0xffffffff

#define TIMEOUT_US		     (150 * USEC_PER_MSEC)
#define PWR_ISLAND_STATUS_TIMEOUT_US (5 * USEC_PER_MSEC)
#define PLL_TIMEOUT_US		     (1500 * USEC_PER_MSEC)

#define WEIGHTS_DEFAULT              0xf711f711u
#define WEIGHTS_ATS_DEFAULT          0x0000f711u

#define ICB_0_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT)) | \
			(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
			(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
			(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
			(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
			(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
			(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))

#define ICB_1_IRQ_MASK ((REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_2_INT)) | \
			(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_3_INT)) | \
			(REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_1, CPU_INT_REDIRECT_4_INT)))

#define ICB_0_1_IRQ_MASK ((((u64)ICB_1_IRQ_MASK) << 32) | ICB_0_IRQ_MASK)

#define BUTTRESS_IRQ_MASK ((REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, FREQ_CHANGE)) | \
			   (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, ATS_ERR)) | \
			   (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI0_ERR)) | \
			   (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, CFI1_ERR)) | \
			   (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR0_ERR)) | \
			   (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, IMR1_ERR)) | \
			   (REG_FLD(VPU_40XX_BUTTRESS_INTERRUPT_STAT, SURV_ERR)))

#define BUTTRESS_IRQ_ENABLE_MASK ((u32)~BUTTRESS_IRQ_MASK)
#define BUTTRESS_IRQ_DISABLE_MASK ((u32)-1)

#define ITF_FIREWALL_VIOLATION_MASK ((REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_ROM_CMX)) | \
				     (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_DBG)) | \
				     (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, CSS_CTRL)) | \
				     (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, DEC400)) | \
				     (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_NCE)) | \
				     (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI)) | \
				     (REG_FLD(VPU_40XX_HOST_SS_FW_SOC_IRQ_EN, MSS_MBI_CMX)))

static char *ivpu_platform_to_str(u32 platform)
{
	switch (platform) {
	case IVPU_PLATFORM_SILICON:
		return "IVPU_PLATFORM_SILICON";
	case IVPU_PLATFORM_SIMICS:
		return "IVPU_PLATFORM_SIMICS";
	case IVPU_PLATFORM_FPGA:
		return "IVPU_PLATFORM_FPGA";
	default:
		return "Invalid platform";
	}
}

static const struct dmi_system_id ivpu_dmi_platform_simulation[] = {
	{
		.ident = "Intel Simics",
		.matches = {
			DMI_MATCH(DMI_BOARD_NAME, "lnlrvp"),
			DMI_MATCH(DMI_BOARD_VERSION, "1.0"),
			DMI_MATCH(DMI_BOARD_SERIAL, "123456789"),
		},
	},
	{
		.ident = "Intel Simics",
		.matches = {
			DMI_MATCH(DMI_BOARD_NAME, "Simics"),
		},
	},
	{ }
};

static void ivpu_hw_read_platform(struct ivpu_device *vdev)
{
	if (dmi_check_system(ivpu_dmi_platform_simulation))
		vdev->platform = IVPU_PLATFORM_SIMICS;
	else
		vdev->platform = IVPU_PLATFORM_SILICON;

	ivpu_dbg(vdev, MISC, "Platform type: %s (%d)\n",
		 ivpu_platform_to_str(vdev->platform), vdev->platform);
}

static void ivpu_hw_wa_init(struct ivpu_device *vdev)
{
	vdev->wa.punit_disabled = ivpu_is_fpga(vdev);
	vdev->wa.clear_runtime_mem = false;

	if (ivpu_hw_gen(vdev) == IVPU_HW_40XX)
		vdev->wa.disable_clock_relinquish = true;
}

static void ivpu_hw_timeouts_init(struct ivpu_device *vdev)
{
	if (ivpu_is_fpga(vdev)) {
		vdev->timeout.boot = 100000;
		vdev->timeout.jsm = 50000;
		vdev->timeout.tdr = 2000000;
		vdev->timeout.reschedule_suspend = 1000;
	} else if (ivpu_is_simics(vdev)) {
		vdev->timeout.boot = 50;
		vdev->timeout.jsm = 500;
		vdev->timeout.tdr = 10000;
		vdev->timeout.reschedule_suspend = 10;
	} else {
		vdev->timeout.boot = 1000;
		vdev->timeout.jsm = 500;
		vdev->timeout.tdr = 2000;
		vdev->timeout.reschedule_suspend = 10;
	}
}

static int ivpu_pll_wait_for_cmd_send(struct ivpu_device *vdev)
{
	return REGB_POLL_FLD(VPU_40XX_BUTTRESS_WP_REQ_CMD, SEND, 0, PLL_TIMEOUT_US);
}

static int ivpu_pll_cmd_send(struct ivpu_device *vdev, u16