path: root/drivers/gpio/gpio-mvebu.c

/*
 * GPIO driver for Marvell SoCs
 *
 * Copyright (C) 2012 Marvell
 *
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Andrew Lunn <andrew@lunn.ch>
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * This driver is a fairly straightforward GPIO driver for the
 * complete family of Marvell EBU SoC platforms (Orion, Dove,
 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
 * driver is the different register layout that exists between the
 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
 * platforms (MV78200 from the Discovery family and the Armada
 * XP). Therefore, this driver handles three variants of the GPIO
 * block:
 * - the basic variant, called "orion-gpio", with the simplest
 *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
 *   non-SMP Discovery systems
 * - the mv78200 variant for MV78200 Discovery systems. This variant
 *   turns the edge mask and level mask registers into CPU0 edge
 *   mask/level mask registers, and adds CPU1 edge mask/level mask
 *   registers.
 * - the armadaxp variant for Armada XP systems. This variant keeps
 *   the normal cause/edge mask/level mask registers when the global
 *   interrupts are used, but adds per-CPU cause/edge mask/level mask
 *   registers n a separate memory area for the per-CPU GPIO
 *   interrupts.
 */

#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/gpio/consumer.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/mfd/syscon.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pwm.h>
#include <linux/regmap.h>
#include <linux/slab.h>

/*
 * GPIO unit register offsets.
 */
#define GPIO_OUT_OFF			0x0000
#define GPIO_IO_CONF_OFF		0x0004
#define GPIO_BLINK_EN_OFF		0x0008
#define GPIO_IN_POL_OFF			0x000c
#define GPIO_DATA_IN_OFF		0x0010
#define GPIO_EDGE_CAUSE_OFF		0x0014
#define GPIO_EDGE_MASK_OFF		0x0018
#define GPIO_LEVEL_MASK_OFF		0x001c
#define GPIO_BLINK_CNT_SELECT_OFF	0x0020

/*
 * PWM register offsets.
 */
#define PWM_BLINK_ON_DURATION_OFF	0x0
#define PWM_BLINK_OFF_DURATION_OFF	0x4


/* The MV78200 has per-CPU registers for edge mask and level mask */
#define GPIO_EDGE_MASK_MV78200_OFF(cpu)	  ((cpu) ? 0x30 : 0x18)
#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)

/*
 * The Armada XP has per-CPU registers for interrupt cause, interrupt
 * mask and interrupt level mask. Those are relative to the
 * percpu_membase.
 */
#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)

#define MVEBU_GPIO_SOC_VARIANT_ORION	0x1
#define MVEBU_GPIO_SOC_VARIANT_MV78200	0x2
#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
#define MVEBU_GPIO_SOC_VARIANT_A8K	0x4

#define MVEBU_MAX_GPIO_PER_BANK		32

struct mvebu_pwm {
	void __iomem		*membase;
	unsigned long		 clk_rate;
	struct gpio_desc	*gpiod;
	struct pwm_chip		 chip;
	spinlock_t		 lock;
	struct mvebu_gpio_chip	*mvchip;

	/* Used to preserve GPIO/PWM registers across suspend/resume */
	u32			 blink_select;
	u32			 blink_on_duration;
	u32			 blink_off_duration;
};

struct mvebu_gpio_chip {
	struct gpio_chip   chip;
	struct regmap     *regs;
	u32		   offset;
	struct regmap     *percpu_regs;
	int		   irqbase;
	struct irq_domain *domain;
	int		   soc_variant;

	/* Used for PWM support */
	struct clk	  *clk;
	struct mvebu_pwm  *mvpwm;

	/* Used to preserve GPIO registers across suspend/resume */
	u32		   out_reg;
	u32		   io_conf_reg;
	u32		   blink_en_reg;
	u32		   in_pol_reg;
	u32		   edge_mask_regs[4];
	u32		   level_mask_regs[4];
};

/*
 * Functions returning addresses of individual registers for a given
 * GPIO controller.
 */

static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip,
			 struct regmap **map, unsigned int *offset)
{
	int cpu;

	switch (mvchip->soc_variant) {
	case MVEBU_GPIO_SOC_VARIANT_ORION:
	case MVEBU_GPIO_SOC_VARIANT_MV78200:
	case MVEBU_GPIO_SOC_VARIANT_A8K:
		*map = mvchip->regs;
		*offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset;
		break;
	case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
		cpu = smp_processor_id();
		*map = mvchip->percpu_regs;
		*offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
		break;
	default:
		BUG();
	}
}

static u32
mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip)