path: root/drivers/iio/adc/max11410.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * MAX11410 SPI ADC driver
 *
 * Copyright 2022 Analog Devices Inc.
 */
#include <linux/bitfield.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>

#include <asm/unaligned.h>

#include <linux/iio/buffer.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>

#define MAX11410_REG_CONV_START	0x01
#define		MAX11410_CONV_TYPE_SINGLE	0x00
#define		MAX11410_CONV_TYPE_CONTINUOUS	0x01
#define MAX11410_REG_CAL_START	0x03
#define		MAX11410_CAL_START_SELF		0x00
#define		MAX11410_CAL_START_PGA		0x01
#define MAX11410_REG_GPIO_CTRL(ch)		((ch) ? 0x05 : 0x04)
#define		MAX11410_GPIO_INTRB		0xC1
#define MAX11410_REG_FILTER	0x08
#define		MAX11410_FILTER_RATE_MASK	GENMASK(3, 0)
#define		MAX11410_FILTER_RATE_MAX	0x0F
#define		MAX11410_FILTER_LINEF_MASK	GENMASK(5, 4)
#define		MAX11410_FILTER_50HZ		BIT(5)
#define		MAX11410_FILTER_60HZ		BIT(4)
#define MAX11410_REG_CTRL	0x09
#define		MAX11410_CTRL_REFSEL_MASK	GENMASK(2, 0)
#define		MAX11410_CTRL_VREFN_BUF_BIT	BIT(3)
#define		MAX11410_CTRL_VREFP_BUF_BIT	BIT(4)
#define		MAX11410_CTRL_FORMAT_BIT	BIT(5)
#define		MAX11410_CTRL_UNIPOLAR_BIT	BIT(6)
#define MAX11410_REG_MUX_CTRL0	0x0B
#define MAX11410_REG_PGA	0x0E
#define		MAX11410_PGA_GAIN_MASK		GENMASK(2, 0)
#define		MAX11410_PGA_SIG_PATH_MASK	GENMASK(5, 4)
#define		MAX11410_PGA_SIG_PATH_BUFFERED	0x00
#define		MAX11410_PGA_SIG_PATH_BYPASS	0x01
#define		MAX11410_PGA_SIG_PATH_PGA	0x02
#define MAX11410_REG_DATA0	0x30
#define MAX11410_REG_STATUS	0x38
#define		MAX11410_STATUS_CONV_READY_BIT	BIT(0)
#define		MAX11410_STATUS_CAL_READY_BIT	BIT(2)

#define MAX11410_REFSEL_AVDD_AGND	0x03
#define MAX11410_REFSEL_MAX		0x06
#define MAX11410_SIG_PATH_MAX		0x02
#define MAX11410_CHANNEL_INDEX_MAX	0x0A
#define MAX11410_AINP_AVDD	0x0A
#define MAX11410_AINN_GND	0x0A

#define MAX11410_CONVERSION_TIMEOUT_MS	2000
#define MAX11410_CALIB_TIMEOUT_MS	2000

#define MAX11410_SCALE_AVAIL_SIZE	8

enum max11410_filter {
	MAX11410_FILTER_FIR5060,
	MAX11410_FILTER_FIR50,
	MAX11410_FILTER_FIR60,
	MAX11410_FILTER_SINC4,
};

static const u8 max11410_sampling_len[] = {
	[MAX11410_FILTER_FIR5060] = 5,
	[MAX11410_FILTER_FIR50] = 6,
	[MAX11410_FILTER_FIR60] = 6,
	[MAX11410_FILTER_SINC4] = 10,
};

static const int max11410_sampling_rates[4][10][2] = {
	[MAX11410_FILTER_FIR5060] = {
		{ 1, 100000 },
		{ 2, 100000 },
		{ 4, 200000 },
		{ 8, 400000 },
		{ 16, 800000 }
	},
	[MAX11410_FILTER_FIR50] = {
		{ 1, 300000 },
		{ 2, 700000 },
		{ 5, 300000 },
		{ 10, 700000 },
		{ 21, 300000 },
		{ 40 }
	},
	[MAX11410_FILTER_FIR60] = {
		{ 1, 300000 },
		{ 2, 700000 },
		{ 5, 300000 },
		{ 10, 700000 },
		{ 21, 300000 },
		{ 40 }
	},
	[MAX11410_FILTER_SINC4] = {
		{ 4 },
		{ 10 },
		{ 20 },
		{ 40 },
		{ 60 },
		{ 120 },
		{ 240 },
		{ 480 },
		{ 960 },
		{ 1920 }
	}
};

struct max11410_channel_config {
	u32 settling_time_us;
	u32 *scale_avail;
	u8 refsel;
	u8 sig_path;
	u8 gain;
	bool bipolar;
	bool buffered_vrefp;
	bool buffered_vrefn;
};

struct max11410_state {
	struct spi_device *spi_dev;
	struct iio_trigger *trig;
	struct completion completion;
	struct mutex lock; /* Prevent changing channel config during sampling */
	struct regmap *regmap;
	struct regulator *avdd;
	struct regulator *vrefp[3];
	struct regulator *vrefn[3];
	struct max11410_channel_config *channels;
	int irq;
	struct {
		u32 data __aligned(IIO_DMA_MINALIGN);
		s64 ts __aligned(8);
	} scan;
};

static const struct iio_chan_spec chanspec_template = {
	.type = IIO_VOLTAGE,
	.indexed = 1,
	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
			      BIT(IIO_CHAN_INFO_SCALE) |
			      BIT(IIO_CHAN_INFO_OFFSET),
	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
	.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
	.scan_type = {
		.sign = 's',
		.realbits = 24,
		.storagebits = 32,
		.endianness = IIO_LE,
	},
};

static unsigned int max11410_reg_size(unsigned int reg)
{
	/* Registers from 0x00 to 0x10 are 1 byte, the rest are 3 bytes long. */
	return reg <= 0x10 ? 1 : 3;
}

static int max11410_write_reg(struct max11410_state *st, unsigned int reg,
			      unsigned int val)
{
	/* This driver only needs to write 8-bit registers */
	if (max11410_reg_size(reg) != 1)
		return -EINVAL;

	return regmap_write(st->regmap, reg, val);
}

static int max11410_read_reg(struct max11410_state *st, unsigned int reg,
			     int *val)
{
	int ret;

	if (max11410_reg_size(reg) == 3) {
		ret = regmap_bulk_read(st->regmap, reg, &st->scan.data, 3);
		if (ret)
			return ret;

		*val = get_unaligned_be24(&st->scan.data);
		return 0;
	}

	return regmap_read(st->regmap, reg, val);
}

static struct regulator *max11410_get_vrefp(struct max11410_state *st,
					    u8 refsel)
{
	refsel = refsel % 4;
	if (refsel == 3)
		return st->avdd;

	return st->vrefp[ref