path: root/drivers/media/i2c/lt6911uxe.c

// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2023 - 2025 Intel Corporation.

#include <linux/acpi.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/v4l2-dv-timings.h>

#include <media/v4l2-cci.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-dv-timings.h>
#include <media/v4l2-event.h>
#include <media/v4l2-fwnode.h>

#define LT6911UXE_CHIP_ID		0x2102
#define REG_CHIP_ID			CCI_REG16(0xe100)

#define REG_ENABLE_I2C			CCI_REG8(0xe0ee)
#define REG_HALF_PIX_CLK		CCI_REG24(0xe085)
#define REG_BYTE_CLK			CCI_REG24(0xe092)
#define REG_HALF_H_TOTAL		CCI_REG16(0xe088)
#define REG_V_TOTAL			CCI_REG16(0xe08a)
#define REG_HALF_H_ACTIVE		CCI_REG16(0xe08c)
#define REG_V_ACTIVE			CCI_REG16(0xe08e)
#define REG_MIPI_FORMAT			CCI_REG8(0xe096)
#define REG_MIPI_TX_CTRL		CCI_REG8(0xe0b0)

/* Interrupts */
#define REG_INT_HDMI			CCI_REG8(0xe084)
#define INT_VIDEO_DISAPPEAR		0x0
#define INT_VIDEO_READY			0x1

#define LT6911UXE_DEFAULT_LANES		4
#define LT6911_PAGE_CONTROL		0xff
#define YUV422_8_BIT			0x7

static const struct v4l2_dv_timings_cap lt6911uxe_timings_cap_4kp30 = {
	.type = V4L2_DV_BT_656_1120,
	/* keep this initialization for compatibility with CLANG */
	.reserved = { 0 },
	/* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
	V4L2_INIT_BT_TIMINGS(160, 3840,			/* min/max width */
			     120, 2160,			/* min/max height */
			     50000000, 594000000,	/* min/max pixelclock */
			     V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
			     V4L2_DV_BT_STD_CVT,
			     V4L2_DV_BT_CAP_PROGRESSIVE |
			     V4L2_DV_BT_CAP_CUSTOM |
			     V4L2_DV_BT_CAP_REDUCED_BLANKING)
};

static const struct regmap_range_cfg lt6911uxe_ranges[] = {
	{
		.name = "register_range",
		.range_min =  0,
		.range_max = 0xffff,
		.selector_reg = LT6911_PAGE_CONTROL,
		.selector_mask = 0xff,
		.selector_shift = 0,
		.window_start = 0,
		.window_len = 0x100,
	},
};

static const struct regmap_config lt6911uxe_regmap_config = {
	.reg_bits = 8,
	.val_bits = 8,
	.max_register = 0xffff,
	.ranges = lt6911uxe_ranges,
	.num_ranges = ARRAY_SIZE(lt6911uxe_ranges),
};

struct lt6911uxe_mode {
	u32 width;
	u32 height;
	u32 htotal;
	u32 vtotal;
	u32 code;
	u32 fps;
	u32 lanes;
	s64 link_freq;
	u64 pixel_clk;
};

struct lt6911uxe {
	struct v4l2_subdev sd;
	struct media_pad pad;
	struct v4l2_ctrl_handler ctrl_handler;
	struct v4l2_ctrl *pixel_rate;
	struct v4l2_dv_timings timings;
	struct lt6911uxe_mode cur_mode;
	struct regmap *regmap;
	struct gpio_desc *reset_gpio;
	struct gpio_desc *irq_gpio;
};

static const struct v4l2_event lt6911uxe_ev_source_change = {
	.type = V4L2_EVENT_SOURCE_CHANGE,
	.u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
};

static inline struct lt6911uxe *to_lt6911uxe(struct v4l2_subdev *sd)
{
	return container_of(sd, struct lt6911uxe, sd);
}

static s64 get_pixel_rate(struct lt6911uxe *lt6911uxe)
{
	s64 pixel_rate;

	pixel_rate = (s64)lt6911uxe->cur_mode.width *
		     lt6911uxe->cur_mode.height *
		     lt6911uxe->cur_mode.fps * 16;
	do_div(pixel_rate, lt6911uxe->cur_mode.lanes);

	return pixel_rate;
}

static int lt6911uxe_get_detected_timings(struct v4l2_subdev *sd,
					  struct v4l2_dv_timings *timings)
{
	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
	struct v4l2_bt_timings *bt = &timings->bt;

	memset(timings, 0, sizeof(struct v4l2_dv_timings));

	timings->type = V4L2_DV_BT_656_1120;

	bt->width = lt6911uxe->cur_mode.width;
	bt->height = lt6911uxe->cur_mode.height;
	bt->vsync = lt6911uxe->cur_mode.vtotal - lt6911uxe->cur_mode.height;
	bt->hsync = lt6911uxe->cur_mode.htotal - lt6911uxe->cur_mode.width;
	bt->pixelclock = lt6911uxe->cur_mode.pixel_clk;

	return 0;
}

static int lt6911uxe_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
				  struct v4l2_dv_timings *timings)
{
	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
	struct v4l2_subdev_state *state;

	state = v4l2_subdev_lock_and_get_active_state(sd);
	if (v4l2_match_dv_timings(&lt6911uxe->timings, timings, 0, false)) {
		v4l2_subdev_unlock_state(state);
		return 0;
	}

	if (!v4l2_valid_dv_timings(timings, &lt6911uxe_timings_cap_4kp30,
				   NULL, NULL)) {
		v4l2_subdev_unlock_state(state);
		return -ERANGE;
	}
	lt6911uxe->timings = *timings;
	v4l2_subdev_unlock_state(state);

	return 0;
}

static int lt6911uxe_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
				  struct v4l2_dv_timings *timings)
{
	struct lt6911uxe *lt6911uxe = to_lt6911uxe(sd);
	struct v4l2_subdev_state *state;

	state = v4l2_subdev_lock_and_get_active_state(sd);

	*timings = lt6911uxe->timings;
	v4l2_subdev_unlock_state(state);

	return 0;
}

static int lt6911uxe_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,
				      struct v4l2_dv_timings *timings)
{
	struct v4l2_subdev_state *state;
	int ret;

	state = v4l2_subdev_lock_and_get_active_state(sd);
	ret = lt6911uxe_get_detected_timings(sd, timings);
	if (ret) {
		v4l2_subdev_unlock_state(state);
		return ret;
	}

	if (!v4l2_valid_dv_timings(timings, &lt6911uxe_timings_cap_4kp30,
				   NULL, NULL)) {
		v4l2_subdev_unlock_state(state);
		return -ERANGE;
	}

	v4l2_subdev_unlock_state(state);
	return 0;
}

static int lt6911uxe_enum_dv_timings(struct v4l2_subdev *sd,
				     struct v4l2_enum_dv_timings *timings)
{
	return v4l2_enum_dv_timings_cap(timings,
			&lt6911uxe_timings_cap_4kp30, NULL, NULL);
}

static int lt6911uxe_dv_timings_cap(struct v4l2_subdev *sd,
				    struct v4l2_dv_timings_cap *cap)
{
	*cap = lt6911uxe_timings_cap_4kp30;
	return 0;
}

static int lt6911uxe_status_update(struct lt6911uxe *lt6911uxe)
{
	struct i2c_client *client = v4l2_get_subdevdata(&lt6911uxe->sd);
	u64 int_event;
	u64 byte_clk, half_pix_clk, fps, format;
	u64 half_htotal, vtotal, half_width, height;
	int ret = 0;

	/* Read interrupt event */
	cci_read(lt6911uxe->regmap, REG_INT_HDMI, &int_event, &ret);
	if (ret) {
		dev_err(&client->dev, "failed to read interrupt event: %d\n",
			ret);
		return ret;
	}

	switch (int_event) {
	case INT_VIDEO_READY:
		cci_read(lt6911uxe->regmap, REG_BYTE_CLK, &byte_clk, &ret);
		byte_clk *= 1000;
		cci_read(lt6911uxe->regmap, REG_HALF_PIX_CLK,
			 &half_pix_clk, &ret);
		half_pix_clk *= 1000;

		if (ret || byte_clk == 0 || half_pix_clk == 0) {
			dev_dbg(&client->dev,
				"invalid ByteClock or PixelClock\n");
			return -EINVAL;
		}

		cci_read(lt6911uxe->regmap, REG_HALF_H_TOTAL,
			 &half_htotal, &ret);
		cci_read(lt6911uxe->regmap, REG_V_TOTAL, &vtotal, &ret);
		if (ret || half_htotal == 0 || vtotal == 0) {
			dev_dbg(&client->dev, "invalid htotal or vtotal\n");
			return -EINVAL;
		}

		fps = div_u64(half_pix_clk, half_htotal * vtotal);
		if (fps > 60) {
			dev_dbg(&client->dev,
				"max fps is 60, current fps: %llu\n", fps);
			return -EINVAL;
		}

		cci_read(lt6911uxe->regmap, REG_HALF_H_ACTIVE,
			 &half_width, &ret);
		cci_read(lt6911uxe->regmap, REG_V_ACTIVE, &height, &ret);
		if (ret || half_width == 0 || half_width * 2 > 3840 ||
		    height == 0 || height > 2160) {
			dev_dbg(&client->dev,