/*
* QLogic qlcnic NIC Driver
* Copyright (c) 2009-2013 QLogic Corporation
*
* See LICENSE.qlcnic for copyright and licensing details.
*/
#include <net/ip.h>
#include "qlcnic.h"
#include "qlcnic_hdr.h"
#include "qlcnic_83xx_hw.h"
#include "qlcnic_hw.h"
#define QLC_83XX_MINIDUMP_FLASH 0x520000
#define QLC_83XX_OCM_INDEX 3
#define QLC_83XX_PCI_INDEX 0
#define QLC_83XX_DMA_ENGINE_INDEX 8
static const u32 qlcnic_ms_read_data[] = {
0x410000A8, 0x410000AC, 0x410000B8, 0x410000BC
};
#define QLCNIC_DUMP_WCRB BIT_0
#define QLCNIC_DUMP_RWCRB BIT_1
#define QLCNIC_DUMP_ANDCRB BIT_2
#define QLCNIC_DUMP_ORCRB BIT_3
#define QLCNIC_DUMP_POLLCRB BIT_4
#define QLCNIC_DUMP_RD_SAVE BIT_5
#define QLCNIC_DUMP_WRT_SAVED BIT_6
#define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
#define QLCNIC_DUMP_SKIP BIT_7
#define QLCNIC_DUMP_MASK_MAX 0xff
struct qlcnic_pex_dma_descriptor {
u32 read_data_size;
u32 dma_desc_cmd;
u32 src_addr_low;
u32 src_addr_high;
u32 dma_bus_addr_low;
u32 dma_bus_addr_high;
u32 rsvd[6];
} __packed;
struct qlcnic_common_entry_hdr {
u32 type;
u32 offset;
u32 cap_size;
#if defined(__LITTLE_ENDIAN)
u8 mask;
u8 rsvd[2];
u8 flags;
#else
u8 flags;
u8 rsvd[2];
u8 mask;
#endif
} __packed;
struct __crb {
u32 addr;
#if defined(__LITTLE_ENDIAN)
u8 stride;
u8 rsvd1[3];
#else
u8 rsvd1[3];
u8 stride;
#endif
u32 data_size;
u32 no_ops;
u32 rsvd2[4];
} __packed;
struct __ctrl {
u32