path: root/drivers/pinctrl/pinctrl-starfive.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Pinctrl / GPIO driver for StarFive JH7100 SoC
 *
 * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
 */

#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/spinlock.h>

#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#include <dt-bindings/pinctrl/pinctrl-starfive.h>

#include "core.h"
#include "pinctrl-utils.h"
#include "pinmux.h"
#include "pinconf.h"

#define DRIVER_NAME "pinctrl-starfive"

/*
 * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
 * https://github.com/starfive-tech/JH7100_Docs
 */
#define NR_GPIOS	64

/*
 * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
 * are enabled. If set to 0 the GPIO interrupts are disabled.
 */
#define GPIOEN		0x000

/*
 * The following 32-bit registers come in pairs, but only the offset of the
 * first register is defined. The first controls (interrupts for) GPIO 0-31 and
 * the second GPIO 32-63.
 */

/*
 * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
 * interrupt is level-triggered.
 */
#define GPIOIS		0x010

/*
 * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
 * both positive and negative edges. If set to 0 the interrupt is triggered by a
 * single edge.
 */
#define GPIOIBE		0x018

/*
 * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
 * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
 * interrupt is triggered on a falling edge (edge-triggered) or low level
 * (level-triggered).
 */
#define GPIOIEV		0x020

/*
 * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
 * the interrupt is disabled (masked). Note that the current documentation is
 * wrong and says the exct opposite of this.
 */
#define GPIOIE		0x028

/*
 * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
 * interrupt.
 */
#define GPIOIC		0x030

/*
 * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
 */
#define GPIORIS		0x038

/*
 * Interrupt Status after Masking. A 1 means the configured edge or level was
 * detected and not masked.
 */
#define GPIOMIS		0x040

/*
 * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
 * a digital 1 and if 0 the pin is a digital 0.
 */
#define GPIODIN		0x048

/*
 * From the data sheet section 12.2, there are 64 32-bit output data registers
 * and 64 output enable registers. Output data and output enable registers for
 * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
 * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c.  The stride
 * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
 * and GPOn_DOEN_CFG is 0x54 + 8n.
 */
#define GPON_DOUT_CFG	0x050
#define GPON_DOEN_CFG	0x054

/*
 * From Section 12.3, there are 75 input signal configuration registers which
 * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
 * GPI_USB_OVER_CURRENT_CFG 0x378
 */
#define GPI_CFG_OFFSET	0x250

/*
 * Pad Control Bits. There are 16 pad control bits for each pin located in 103
 * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
 * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
 * bit of each register.
 */
#define PAD_SLEW_RATE_MASK		GENMASK(11, 9)
#define PAD_SLEW_RATE_POS		9
#define PAD_BIAS_STRONG_PULL_UP		BIT(8)
#define PAD_INPUT_ENABLE		BIT(7)
#define PAD_INPUT_SCHMITT_ENABLE	BIT(6)
#define PAD_BIAS_DISABLE		BIT(5)
#define PAD_BIAS_PULL_DOWN		BIT(4)
#define PAD_BIAS_MASK \
	(PAD_BIAS_STRONG_PULL_UP | \
	 PAD_BIAS_DISABLE | \
	 PAD_BIAS_PULL_DOWN)
#define PAD_DRIVE_STRENGTH_MASK		GENMASK(3, 0)
#define PAD_DRIVE_STRENGTH_POS		0

/*
 * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
 * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
 * PAD_GPIO pads. This is a global setting.
 */
#define IO_PADSHARE_SEL			0x1a0

/*
 * This just needs to be some number such that when
 * sfp->gpio.pin_base = PAD_INVALID_GPIO then
 * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
 * That is it should underflow and return something >= NR_GPIOS.
 */
#define PAD_INVALID_GPIO		0x10000

/*
 * The packed pinmux values from the device tree look like this:
 *
 *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
 *  |  dout   |  doen   |  din   | dout rev | doen rev | g