path: root/drivers/pinctrl/pinctrl-thunderbay.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Intel Thunder Bay SOC pinctrl/GPIO driver
 *
 * Copyright (C) 2021 Intel Corporation
 */

#include <linux/device.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_irq.h>

#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>

#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "core.h"
#include "pinconf.h"
#include "pinctrl-utils.h"
#include "pinmux.h"

/* Bit 0:2 and 4:6 should be used for mode selection */
#define THB_GPIO_PINMUX_MODE_0			0x00
#define THB_GPIO_PINMUX_MODE_1			0x11
#define THB_GPIO_PINMUX_MODE_2			0x22
#define THB_GPIO_PINMUX_MODE_3			0x33
#define THB_GPIO_PINMUX_MODE_4			0x44

#define THB_GPIO_PORT_SELECT_MASK		BIT(8)
#define THB_GPIO_PAD_DIRECTION_MASK		BIT(10)
#define THB_GPIO_SPU_MASK			BIT(11)
#define THB_GPIO_PULL_ENABLE_MASK		BIT(12)
#define THB_GPIO_PULL_UP_MASK			BIT(13)
#define THB_GPIO_PULL_DOWN_MASK			BIT(14)
#define THB_GPIO_ENAQ_MASK			BIT(15)
/* bit 16-19: Drive Strength for the Pad */
#define THB_GPIO_DRIVE_STRENGTH_MASK		(0xF0000)
#define THB_GPIO_SLEW_RATE_MASK			BIT(20)
#define THB_GPIO_SCHMITT_TRIGGER_MASK		BIT(21)

#define THB_GPIO_REG_OFFSET(pin_num)			((pin_num) * (0x4))
#define THB_MAX_MODE_SUPPORTED				(5u)
#define THB_MAX_NPINS_SUPPORTED				(67u)

/* store Pin status */
static u32 thb_pinx_status[THB_MAX_NPINS_SUPPORTED];

struct thunderbay_mux_desc {
	u8 mode;
	const char *name;
};

#define THUNDERBAY_PIN_DESC(pin_number, pin_name, ...) {        \
	.number = pin_number,                           \
	.name = pin_name,                               \
	.drv_data = &(struct thunderbay_mux_desc[]) {   \
			__VA_ARGS__, { } },             \
}

#define THUNDERBAY_MUX(pin_mode, pin_function) {                \
	.mode = pin_mode,                               \
	.name = pin_function,                           \
}

struct thunderbay_pin_soc {
	const struct pinctrl_pin_desc           *pins;
	unsigned int                            npins;
};

/**
 * struct thunderbay_pinctrl - Intel Thunderbay pinctrl structure
 * @pctrl: Pointer to the pin controller device
 * @base0: First register base address
 * @dev: Pointer to the device structure
 * @chip: GPIO chip used by this pin controller
 * @soc: Pin control configuration data based on SoC
 * @ngroups: Number of pin groups available
 * @nfuncs: Number of pin functions available
 */
struct thunderbay_pinctrl {
	struct pinctrl_dev              *pctrl;
	void __iomem                    *base0;
	struct device                   *dev;
	struct gpio_chip                chip;
	const struct thunderbay_pin_soc *soc;
	unsigned int                    ngroups;
	unsigned int                    nfuncs;
};

static const struct pinctrl_pin_desc thunderbay_pins[] = {
	THUNDERBAY_PIN_DESC(0, "GPIO0",
			    THUNDERBAY_MUX(0X0, "I2C0_M0"),
			    THUNDERBAY_MUX(0X1, "EMPTY_M1"),
			    THUNDERBAY_MUX(0X2, "EMPTY_M2"),
			    THUNDERBAY_MUX(0X3, "EMPTY_M3"),
			    THUNDERBAY_MUX(0X4, "GPIO_M4")),
	THUNDERBAY_PIN_DESC(1, "GPIO1",
			    THUNDERBAY_MUX(0X0, "I2C0_M0"),
			    THUNDERBAY_MUX(0X1, "EMPTY_M1"),
			    THUNDERBAY_MUX(0X2, "EMPTY_M2"),
			    THUNDERBAY_MUX(0X3, "EMPTY_M3"),
			    THUNDERBAY_MUX(0X4, "GPIO_M4")),
	THUNDERBAY_PIN_DESC(2, "GPIO2",
			    THUNDERBAY_MUX(0X0, "I2C1_M0"),
			    THUNDERBAY_MUX(0X1, "EMPTY_M1"),
			    THUNDERBAY_MUX(0X2, "EMPTY_M2"),
			    THUNDERBAY_MUX(0X3, "EMPTY_M3"),
			    THUNDERBAY_MUX(0X4, "GPIO_M4")),
	THU