path: root/drivers/spi/spi-sirf.c

/*
 * SPI bus driver for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/of_gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/dmaengine.h>
#include <linux/dma-direction.h>
#include <linux/dma-mapping.h>
#include <linux/reset.h>

#define DRIVER_NAME "sirfsoc_spi"
/* SPI CTRL register defines */
#define SIRFSOC_SPI_SLV_MODE		BIT(16)
#define SIRFSOC_SPI_CMD_MODE		BIT(17)
#define SIRFSOC_SPI_CS_IO_OUT		BIT(18)
#define SIRFSOC_SPI_CS_IO_MODE		BIT(19)
#define SIRFSOC_SPI_CLK_IDLE_STAT	BIT(20)
#define SIRFSOC_SPI_CS_IDLE_STAT	BIT(21)
#define SIRFSOC_SPI_TRAN_MSB		BIT(22)
#define SIRFSOC_SPI_DRV_POS_EDGE	BIT(23)
#define SIRFSOC_SPI_CS_HOLD_TIME	BIT(24)
#define SIRFSOC_SPI_CLK_SAMPLE_MODE	BIT(25)
#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8	(0 << 26)
#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12	(1 << 26)
#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16	(2 << 26)
#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32	(3 << 26)
#define SIRFSOC_SPI_CMD_BYTE_NUM(x)	((x & 3) << 28)
#define SIRFSOC_SPI_ENA_AUTO_CLR	BIT(30)
#define SIRFSOC_SPI_MUL_DAT_MODE	BIT(31)

/* Interrupt Enable */
#define SIRFSOC_SPI_RX_DONE_INT_EN	BIT(0)
#define SIRFSOC_SPI_TX_DONE_INT_EN	BIT(1)
#define SIRFSOC_SPI_RX_OFLOW_INT_EN	BIT(2)
#define SIRFSOC_SPI_TX_UFLOW_INT_EN	BIT(3)
#define SIRFSOC_SPI_RX_IO_DMA_INT_EN	BIT(4)
#define SIRFSOC_SPI_TX_IO_DMA_INT_EN	BIT(5)
#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN	BIT(6)
#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN	BIT(7)
#define SIRFSOC_SPI_RXFIFO_THD_INT_EN	BIT(8)
#define SIRFSOC_SPI_TXFIFO_THD_INT_EN	BIT(9)
#define SIRFSOC_SPI_FRM_END_INT_EN	BIT(10)

/* Interrupt status */
#define SIRFSOC_SPI_RX_DONE		BIT(0)
#define SIRFSOC_SPI_TX_DONE		BIT(1)
#define SIRFSOC_SPI_RX_OFLOW		BIT(2)
#define SIRFSOC_SPI_TX_UFLOW		BIT(3)
#define SIRFSOC_SPI_RX_IO_DMA		BIT(4)
#define SIRFSOC_SPI_RX_FIFO_FULL	BIT(6)
#define SIRFSOC_SPI_TXFIFO_EMPTY	BIT(7)
#define SIRFSOC_SPI_RXFIFO_THD_REACH	BIT(8)
#define SIRFSOC_SPI_TXFIFO_THD_REACH	BIT(9)
#define SIRFSOC_SPI_FRM_END		BIT(10)

/* TX RX enable */
#define SIRFSOC_SPI_RX_EN		BIT(0)
#define SIRFSOC_SPI_TX_EN		BIT(1)
#define SIRFSOC_SPI_CMD_TX_EN		BIT(2)

#define SIRFSOC_SPI_IO_MODE_SEL		BIT(0)
#define SIRFSOC_SPI_RX_DMA_FLUSH	BIT(2)

/* FIFO OPs */
#define SIRFSOC_SPI_FIFO_RESET		BIT(0)
#define SIRFSOC_SPI_FIFO_START		BIT(1)

/* FIFO CTRL */
#define SIRFSOC_SPI_FIFO_WIDTH_BYTE	(0 << 0)
#define SIRFSOC_SPI_FIFO_WIDTH_WORD	(1 << 0)
#define SIRFSOC_SPI_FIFO_WIDTH_DWORD	(2 << 0)
/* USP related */
#define SIRFSOC_USP_SYNC_MODE		BIT(0)
#define SIRFSOC_USP_SLV_MODE		BIT(1)
#define SIRFSOC_USP_LSB			BIT(4)
#define SIRFSOC_USP_EN			BIT(5)
#define SIRFSOC_USP_RXD_FALLING_EDGE	BIT(6)
#define SIRFSOC_USP_TXD_FALLING_EDGE	BIT(7)
#define SIRFSOC_USP_CS_HIGH_VALID	BIT(9)
#define SIRFSOC_USP_SCLK_IDLE_STAT	BIT(11)
#define SIRFSOC_USP_TFS_IO_MODE		BIT(14)
#define SIRFSOC_USP_TFS_IO_INPUT	BIT(19)

#define SIRFSOC_USP_RXD_DELAY_LEN_MASK	0xFF
#define SIRFSOC_USP_TXD_DELAY_LEN_MASK	0xFF
#define SIRFSOC_USP_RXD_DELAY_OFFSET	0
#define SIRFSOC_USP_TXD_DELAY_OFFSET	8
#define SIRFSOC_USP_RXD_DELAY_LEN	1
#define SIRFSOC_USP_TXD_DELAY_LEN	1
#define SIRFSOC_USP_CLK_DIVISOR_OFFSET	21
#define SIRFSOC_USP_CLK_DIVISOR_MASK	0x3FF
#define SIRFSOC_USP_CLK_10_11_MASK	0x3
#define SIRFSOC_USP_CLK_10_11_OFFSET	30
#define SIRFSOC_USP_CLK_12_15_MASK	0xF
#define SIRFSOC_USP_CLK_12_15_OFFSET	24

#define SIRFSOC_USP_TX_DATA_OFFSET	0
#define SIRFSOC_USP_TX_SYNC_OFFSET	8
#define SIRFSOC_USP_TX_FRAME_OFFSET	16
#define SIRFSOC_USP_TX_SHIFTER_OFFSET	24

#define SIRFSOC_USP_TX_DATA_MASK	0xFF
#define SIRFSOC_USP_TX_SYNC_MASK	0xFF
#define SIRFSOC_USP_TX_FRAME_MASK	0xFF
#define SIRFSOC_USP_TX_SHIFTER_MASK	0x1F

#define SIRFSOC_USP_RX_DATA_OFFSET	0
#define SIRFSOC_USP_RX_FRAME_OFFSET	8
#define SIRFSOC_USP_RX_SHIFTER_OFFSET	16

#define SIRFSOC_USP_RX_DATA_MASK	0xFF
#define SIRFSOC_USP_RX_FRAME_MASK	0xFF
#define SIRFSOC_USP_RX_SHIFTER_MASK	0x1F
#define SIRFSOC_USP_CS_HIGH_VALUE	BIT(1)

#define SIRFSOC_SPI_FIFO_SC_OFFSET	0
#define SIRFSOC_SPI_FIFO_LC_OFFSET	10
#define SIRFSOC_SPI_FIFO_HC_OFFSET	20

#define SIRFSOC_SPI_FIFO_FULL_MASK(s)	(1 << ((s)->fifo_full_offset))
#define SIRFSOC_SPI_FIFO_EMPTY_MASK(s)	(1 << ((s)->fifo_full_offset + 1))
#define SIRFSOC_SPI_FIFO_THD_MASK(s)	((s)->fifo_size - 1)
#define SIRFSOC_SPI_FIFO_THD_OFFSET	2
#define SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(s, val)	\
	((val) & (s)->fifo_level_chk_mask)

enum sirf_spi_type {
	SIRF_REAL_SPI,
	SIRF_USP_SPI_P2,
	SIRF_USP_SPI_A7,
};

/*
 * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
 * due to the limitation of dma controller
 */

#define ALIGNED(x) (!((u32)x & 0x3))
#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
	ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))

#define SIRFSOC_MAX_CMD_BYTES	4
#define SIRFSOC_SPI_DEFAULT_FRQ 1000000

struct sirf_spi_register {
	/*SPI and USP-SPI common*/
	u32 tx_rx_en;
	u32 int_en;
	u32 int_st;
	u32 tx_dma_io_ctrl;
	u32 tx_dma_io_len;
	u32 txfifo_ctrl;
	u32 txfifo_level_chk;
	u32 txfifo_op;
	u32 txfifo_st;
	u32 txfifo_data;
	u32 rx_dma_io_ctrl;
	u32 rx_dma_io_len;
	u32 rxfifo_ctrl;
	u32 rxfifo_level_chk;
	u32 rxfifo_op;
	u32 rxfifo_st;
	u32 rxfifo_data;
	/*SPI self*/
	u32 spi_ctrl;
	u32 spi_cmd;
	u32 spi_dummy_delay_ctrl;
	/*USP-SPI self*/
	u32 usp_mode1;
	u32 usp_mode2;
	u32 usp_tx_frame_ctrl;
	u32 usp_rx_frame_ctrl;
	u32 usp_pin_io_data;
	u32 usp_risc_dsp_mode;
	u32 usp_async_param_reg;
	u32 usp_irda_x_mode_div;
	u32 usp_sm_cfg;
	u32 usp_int_en_clr;
};

static const struct sirf_spi_register real_spi_register = {
	.tx_rx_en		= 0x8,
	.int_en		= 0xc,
	.int_st		= 0x10,
	.tx_dma_io_ctrl	= 0x100,
	.tx_dma_io_len	= 0x104,
	.txfifo_ctrl	= 0x108,
	.