path: root/include/dt-bindings/clock/tegra186-clock.h

/** @file */

#ifndef _MACH_T186_CLK_T186_H
#define _MACH_T186_CLK_T186_H

/**
 * @defgroup clock_ids Clock Identifiers
 * @{
 *   @defgroup extern_input external input clocks
 *   @{
 *     @def TEGRA186_CLK_OSC
 *     @def TEGRA186_CLK_CLK_32K
 *     @def TEGRA186_CLK_DTV_INPUT
 *     @def TEGRA186_CLK_SOR0_PAD_CLKOUT
 *     @def TEGRA186_CLK_SOR1_PAD_CLKOUT
 *     @def TEGRA186_CLK_I2S1_SYNC_INPUT
 *     @def TEGRA186_CLK_I2S2_SYNC_INPUT
 *     @def TEGRA186_CLK_I2S3_SYNC_INPUT
 *     @def TEGRA186_CLK_I2S4_SYNC_INPUT
 *     @def TEGRA186_CLK_I2S5_SYNC_INPUT
 *     @def TEGRA186_CLK_I2S6_SYNC_INPUT
 *     @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
 *   @}
 *
 *   @defgroup extern_output external output clocks
 *   @{
 *     @def TEGRA186_CLK_EXTPERIPH1
 *     @def TEGRA186_CLK_EXTPERIPH2
 *     @def TEGRA186_CLK_EXTPERIPH3
 *     @def TEGRA186_CLK_EXTPERIPH4
 *   @}
 *
 *   @defgroup display_clks display related clocks
 *   @{
 *     @def TEGRA186_CLK_CEC
 *     @def TEGRA186_CLK_DSIC
 *     @def TEGRA186_CLK_DSIC_LP
 *     @def TEGRA186_CLK_DSID
 *     @def TEGRA186_CLK_DSID_LP
 *     @def TEGRA186_CLK_DPAUX1
 *     @def TEGRA186_CLK_DPAUX
 *     @def TEGRA186_CLK_HDA2HDMICODEC
 *     @def TEGRA186_CLK_NVDISPLAY_DISP
 *     @def TEGRA186_CLK_NVDISPLAY_DSC
 *     @def TEGRA186_CLK_NVDISPLAY_P0
 *     @def TEGRA186_CLK_NVDISPLAY_P1
 *     @def TEGRA186_CLK_NVDISPLAY_P2
 *     @def TEGRA186_CLK_NVDISPLAYHUB
 *     @def TEGRA186_CLK_SOR_SAFE
 *     @def TEGRA186_CLK_SOR0
 *     @def TEGRA186_CLK_SOR0_OUT
 *     @def TEGRA186_CLK_SOR1
 *     @def TEGRA186_CLK_SOR1_OUT
 *     @def TEGRA186_CLK_DSI
 *     @def TEGRA186_CLK_MIPI_CAL
 *     @def TEGRA186_CLK_DSIA_LP
 *     @def TEGRA186_CLK_DSIB
 *     @def TEGRA186_CLK_DSIB_LP
 *   @}
 *
 *   @defgroup camera_clks camera related clocks
 *   @{
 *     @def TEGRA186_CLK_NVCSI
 *     @def TEGRA186_CLK_NVCSILP
 *     @def TEGRA186_CLK_VI
 *   @}
 *
 *   @defgroup audio_clks audio related clocks
 *   @{
 *     @def TEGRA186_CLK_ACLK
 *     @def TEGRA186_CLK_ADSP
 *     @def TEGRA186_CLK_ADSPNEON
 *     @def TEGRA186_CLK_AHUB
 *     @def TEGRA186_CLK_APE
 *     @def TEGRA186_CLK_APB2APE
 *     @def TEGRA186_CLK_AUD_MCLK
 *     @def TEGRA186_CLK_DMIC1
 *     @def TEGRA186_CLK_DMIC2
 *     @def TEGRA186_CLK_DMIC3
 *     @def TEGRA186_CLK_DMIC4
 *     @def TEGRA186_CLK_DSPK1
 *     @def TEGRA186_CLK_DSPK2
 *     @def TEGRA186_CLK_HDA
 *     @def TEGRA186_CLK_HDA2CODEC_2X
 *     @def TEGRA186_CLK_I2S1
 *     @def TEGRA186_CLK_I2S2
 *     @def TEGRA186_CLK_I2S3
 *     @def TEGRA186_CLK_I2S4
 *     @def TEGRA186_CLK_I2S5
 *     @def TEGRA186_CLK_I2S6
 *     @def TEGRA186_CLK_MAUD
 *     @def TEGRA186_CLK_PLL_A_OUT0
 *     @def TEGRA186_CLK_SPDIF_DOUBLER
 *     @def TEGRA186_CLK_SPDIF_IN
 *     @def TEGRA186_CLK_SPDIF_OUT
 *     @def TEGRA186_CLK_SYNC_DMIC1
 *     @def TEGRA186_CLK_SYNC_DMIC2
 *     @def TEGRA186_CLK_SYNC_DMIC3
 *     @def TEGRA186_CLK_SYNC_DMIC4
 *     @def TEGRA186_CLK_SYNC_DMIC5
 *     @def TEGRA186_CLK_SYNC_DSPK1
 *     @def TEGRA186_CLK_SYNC_DSPK2
 *     @def TEGRA186_CLK_SYNC_I2S1
 *     @def TEGRA186_CLK_SYNC_I2S2
 *     @def TEGRA186_CLK_SYNC_I2S3
 *     @def TEGRA186_CLK_SYNC_I2S4
 *     @def TEGRA186_CLK_SYNC_I2S5
 *     @def TEGRA186_CLK_SYNC_I2S6
 *     @def TEGRA186_CLK_SYNC_SPDIF
 *   @}
 *
 *   @defgroup uart_clks UART clocks
 *   @{
 *     @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
 *     @def TEGRA186_CLK_UARTA
 *     @def TEGRA186_CLK_UARTB
 *     @def TEGRA186_CLK_UARTC
 *     @def TEGRA186_CLK_UARTD
 *     @def TEGRA186_CLK_UARTE
 *     @def TEGRA186_CLK_UARTF
 *     @def TEGRA186_CLK_UARTG
 *     @def TEGRA186_CLK_UART_FST_MIPI_CAL
 *   @}
 *
 *   @defgroup i2c_clks I2C clocks
 *   @{
 *     @def TEGRA186_CLK_AON_I2C_SLOW
 *     @def TEGRA186_CLK_I2C1
 *     @def TEGRA186_CLK_I2C2
 *     @def TEGRA186_CLK_I2C3
 *     @def TEGRA186_CLK_I2C4
 *     @def TEGRA186_CLK_I2C5
 *     @def TEGRA186_CLK_I2C6
 *     @def TEGRA186_CLK_I2C8
 *     @def TEGRA186_CLK_I2C9
 *     @def TEGRA186_CLK_I2C1
 *     @def TEGRA186_CLK_I2C12
 *     @def TEGRA186_CLK_I2C13
 *     @def TEGRA186_CLK_I2C14
 *     @def TEGRA186_CLK_I2C_SLOW
 *     @def TEGRA186_CLK_VI_I2C
 *   @}
 *
 *   @defgroup spi_clks SPI clocks
 *   @{
 *     @def TEGRA186_CLK_SPI1
 *     @def TEGRA186_CLK_SPI2
 *     @def TEGRA186_CLK_SPI3
 *     @def TEGRA186_CLK_SPI4
 *   @}
 *
 *   @defgroup storage storage related clocks
 *   @{
 *     @def TEGRA186_CLK_SATA
 *     @def TEGRA186_CLK_SATA_OOB
 *     @def TEGRA186_CLK_SATA_IOBIST
 *     @def TEGRA186_CLK_SDMMC_LEGACY_TM
 *     @def TEGRA186_CLK_SDMMC1
 *     @def TEGRA186_CLK_SDMMC2
 *     @def TEGRA186_CLK_SDMMC3
 *     @def TEGRA186_CLK_SDMMC4
 *     @def TEGRA186_CLK_QSPI
 *     @def TEGRA186_CLK_QSPI_OUT
 *     @def TEGRA186_CLK_UFSDEV_REF
 *     @def TEGRA186_CLK_UFSHC
 *   @}
 *
 *   @defgroup pwm_clks PWM clocks
 *   @{
 *     @def TEGRA186_CLK_PWM1
 *     @def TEGRA186_CLK_PWM2
 *     @def TEGRA186_CLK_PWM3
 *     @def TEGRA186_CLK_PWM4
 *     @def TEGRA186_CLK_PWM5
 *     @def TEGRA186_CLK_PWM6
 *     @def TEGRA186_CLK_PWM7
 *     @def TEGRA186_CLK_PWM8
 *   @}
 *
 *   @defgroup plls PLLs and related clocks
 *   @{
 *     @def TEGRA186_CLK_PLLREFE_OUT_GATED
 *     @def TEGRA186_CLK_PLLREFE_OUT1
 *     @def TEGRA186_CLK_PLLD_OUT1
 *     @def TEGRA186_CLK_PLLP_OUT0
 *     @def TEGRA186_CLK_PLLP_OUT5
 *     @def TEGRA186_CLK_PLLA
 *     @def TEGRA186_CLK_PLLE_PWRSEQ
 *     @def TEGRA186_CLK_PLLA_OUT1
 *     @def TEGRA186_CLK_PLLREFE_REF
 *     @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
 *     @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
 *     @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
 *     @def TEGRA186_CLK_PLLREFE_PEX
 *     @def TEGRA186_CLK_PLLREFE_IDDQ
 *     @def TEGRA186_CLK_PLLC_OUT_AON
 *     @def TEGRA186_CLK_PLLC_OUT_ISP
 *     @def TEGRA186_CLK_PLLC_OUT_VE
 *     @def TEGRA186_CLK_PLLC4_OUT
 *     @def TEGRA186_CLK_PLLREFE_OUT
 *     @def TEGRA186_CLK_PLLREFE_PLL_REF
 *     @def TEGRA186_CLK_PLLE
 *     @def TEGRA186_CLK_PLLC
 *     @def TEGRA186_CLK_PLLP
 *     @def TEGRA186_CLK_PLLD
 *     @def TEGRA186_CLK_PLLD2
 *     @def TEGRA186_CLK_PLLREFE_VCO
 *     @def TEGRA186_CLK_PLLC2
 *     @def TEGRA186_CLK_PLLC3
 *     @def TEGRA186_CLK_PLLDP
 *     @def TEGRA186_CLK_PLLC4_VCO
 *     @def TEGRA186_CLK_PLLA1
 *     @def TEGRA186_CLK_PLLNVCSI
 *     @def TEGRA186_CLK_PLLDISPHUB
 *     @def TEGRA186_CLK_PLLD3
 *     @def TEGRA186_CLK_PLLBPMPCAM
 *     @def TEGRA186_CLK_PLLAON
 *     @def TEGRA186_CLK_PLLU
 *     @def TEGRA186_CLK_PLLC4_VCO_DIV2
 *     @def TEGRA186_CLK_PLL_REF
 *     @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
 *     @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
 *     @def TEGRA186_CLK_PLL_U_48M
 *     @def TEGRA186_CLK_PLL_U_480M
 *     @def TEGRA186_CLK_PLLC4_OUT0
 *     @def TEGRA186_CLK_PLLC4_OUT1
 *     @def TEGRA186_CLK_PLLC4_OUT2
 *     @def TEGRA186_CLK_PLLC4_OUT_MUX
 *     @def TEGRA186_CLK_DFLLDISP_DIV
 *     @def TEGRA186_CLK_PLLDISPHUB_DIV
 *     @def TEGRA186_CLK_PLLP_DIV8
 *   @}
 *
 *   @defgroup nafll_clks NAFLL clock sources
 *   @{
 *     @def TEGRA186_CLK_NAFLL_AXI_CBB
 *     @def TEGRA186_CLK_NAFLL_BCPU
 *     @def TEGRA186_CLK_NAFLL_BPMP
 *     @def TEGRA186_CLK_NAFLL_DISP
 *     @def TEGRA186_CLK_NAFLL_GPU
 *     @def TEGRA186_CLK_NAFLL_ISP
 *     @def TEGRA186_CLK_NAFLL_MCPU
 *     @def TEGRA186_CLK_NAFLL_NVDEC
 *     @def TEGRA186_CLK_NAFLL_NVENC
 *     @def TEGRA186_CLK_NAFLL_NVJPG
 *     @def TEGRA186_CLK_NAFLL_SCE
 *     @def TEGRA186_CLK_NAFLL_SE
 *     @def TEGRA186_CLK_NAFLL_TSEC
 *     @def TEGRA186_CLK_NAFLL_TSECB
 *     @def TEGRA186_CLK_NAFLL_VI
 *     @def TEGRA186_CLK_NAFLL_VIC
 *   @}
 *
 *   @defgroup mphy MPHY related clocks
 *   @{
 *     @def TEGRA186_CLK_MPHY_L0_RX_SYMB
 *     @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
 *     @def TEGRA186_CLK_MPHY_L0_TX_SYMB
 *     @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
 *     @def TEGRA186_CLK_MPHY_L0_RX_ANA
 *     @def TEGRA186_CLK_MPHY_L1_RX_ANA
 *     @def TEGRA186_CLK_MPHY_IOBIST
 *     @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
 *     @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
 *   @}
 *
 *   @defgroup eavb EAVB related clocks
 *   @{
 *     @def TEGRA186_CLK_EQOS_AXI
 *     @def TEGRA186_CLK_EQOS_PTP_REF
 *     @def TEGRA186_CLK_EQOS_RX
 *     @def TEGRA186_CLK_EQOS_RX_INPUT
 *     @def TEGRA186_CLK_EQOS_TX
 *   @}
 *
 *   @defgroup usb USB related clocks
 *   @{
 *     @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
 *     @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
 *     @def TEGRA186_CLK_HSIC_TRK
 *     @def TEGRA186_CLK_USB2_TRK
 *     @def TEGRA186_CLK_USB2_HSIC_TRK
 *     @def TEGRA186_CLK_XUSB_CORE_SS
 *     @def TEGRA186_CLK_XUSB_CORE_DEV
 *     @def TEGRA186_CLK_XUSB_FALCON
 *     @def TEGRA186_CLK_XUSB_FS
 *     @def TEGRA186_CLK_XUSB
 *     @def TEGRA186_CLK_XUSB_DEV
 *     @def TEGRA186_CLK_XUSB_HOST
 *     @def TEGRA186_CLK_XUSB_SS
 *   @}
 *
 *   @defgroup bigblock compute block related clocks
 *   @{
 *     @def TEGRA186_CLK_GPCCLK
 *     @def TEGRA186_CLK_GPC2CLK
 *     @def TEGRA186_CLK_GPU
 *     @def TEGRA186_CLK_HOST1X
 *     @def TEGRA186_CLK_ISP
 *     @def TEGRA186_CLK_NVDEC
 *     @def TEGRA186_CLK_NVENC
 *     @def TEGRA186_CLK_NVJPG
 *     @def TEGRA186_CLK_SE
 *     @def TEGRA186_CLK_TSEC
 *     @def TEGRA186_CLK_TSECB
 *     @def TEGRA186_CLK_VIC
 *   @}
 *
 *   @defgroup can CAN bus related clocks
 *   @{
 *     @def TEGRA186_CLK_CAN1
 *     @def TEGRA186_CLK_CAN1_HOST
 *     @def TEGRA186_CLK_CAN2
 *     @def TEGRA186_CLK_CAN2_HOST
 *   @}
 *
 *   @defgroup system basic system clocks
 *   @{
 *     @def TEGRA186_CLK_ACTMON
 *     @def TEGRA186_CLK_AON_APB
 *     @def TEGRA186_CLK_AON_CPU_NIC
 *     @def TEGRA186_CLK_AON_NIC
 *     @def TEGRA186_CLK_AXI_CBB
 *     @def TEGRA186_CLK_BPMP_APB
 *     @def TEGRA186_CLK_BPMP_CPU_NIC
 *     @def TEGRA186_CLK_BPMP_NIC_RATE
 *     @def TEGRA186_CLK_CLK_M
 *     @def TEGRA186_CLK_EMC
 *     @def TEGRA186_CLK_MSS_ENCRYPT
 *     @def TEGRA186_CLK_SCE_APB
 *     @def TEGRA186_CLK_SCE_CPU_NIC
 *     @def TEGRA186_CLK_SCE_NIC
 *     @def TEGRA186_CLK_TSC
 *   @}
 *
 *   @defgroup pcie_clks PCIe related clocks
 *   @{
 *     @def TEGRA186_CLK_AFI
 *     @def TEGRA186_CLK_PCIE
 *     @def TEGRA186_CLK_PCIE2_IOBIST
 *     @def TEGRA186_CLK_PCIERX0
 *     @def TEGRA186_CLK_PCIERX1
 *     @def TEGRA186_CLK_PCIERX2
 *     @def TEGRA186_CLK_PCIERX3
 *     @def TEGRA186_CLK_PCIERX4
 *   @}
 */

/** @brief output of gate CLK_ENB_FUSE */
#define TEGRA186_CLK_FUSE 0
/**
 * @brief It's not what you think
 * @details output of gate CLK_ENB_GPU. This output connects to the GPU
 * pwrclk. @warning: This is almost certainly not the clock you think
 * it is. If you're looking for the clock of the graphics engine, see
 * TEGRA186_GPCCLK
 */
#define TEGRA186_CLK_GPU 1
/** @brief output of gate CLK_ENB_PCIE */
#define TEGRA186_CLK_PCIE 3
/** @brief output of the divider IPFS_CLK_DIVISOR */
#define TEGRA186_CLK_AFI 4
/** @brief output of gate CLK_ENB_PCIE2_IOBIST */
#define TEGRA186_CLK_PCIE2_IOBIST 5
/** @brief output of gate CLK_ENB_PCIERX0*/
#define TEGRA186_CLK_PCIERX0 6
/** @brief output of gate CLK_ENB_PCIERX1*/
#define TEGRA186_CLK_PCIERX1 7
/** @brief output of gate CLK_ENB_PCIERX2*/
#define TEGRA186_CLK_PCIERX2 8
/** @brief output of gate CLK_ENB_PCIERX3*/
#define TEGRA186_CLK_PCIERX3 9
/** @brief output of gate CLK_ENB_PCIERX4*/
#define TEGRA186_CLK_PCIERX4 10
/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
#define TEGRA186_CLK_PLLC_OUT_ISP 11
/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
#define TEGRA186_CLK_PLLC_OUT_VE 12
/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
#define TEGRA186_CLK_PLLC_OUT_AON 13
/** @brief output of gate CLK_ENB_SOR_SAFE */
#define TEGRA186_CLK_SOR_SAFE 39
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
#define TEGRA186_CLK_I2S2 42
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
#define TEGRA186_CLK_I2S3 43
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
#define TEGRA186_CLK_SPDIF_IN 44
/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
#define TEGRA186_CLK_SPDIF_DOUBLER 45
/**  @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
#define TEGRA186_CLK_SPI3 46
/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
#define TEGRA186_CLK_I2C1 47
/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
#define TEGRA186_CLK_I2C5 48
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
#define TEGRA186_CLK_SPI1 49
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
#define TEGRA186_CLK_ISP 50
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
#define TEGRA186_CLK_VI 51
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
#define TEGRA186_CLK_SDMMC1 52
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
#define TEGRA186_CLK_SDMMC2 53
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
#define TEGRA186_CLK_SDMMC4 54
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
#define TEGRA186_CLK_UARTA 55
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
#define TEGRA186_CLK_UARTB 56
/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
#define TEGRA186_CLK_HOST1X 57
/**
 * @brief controls the EMC clock frequency.
 * @details Doing a clk_set_rate on this clock will select the
 * appropriate clock source, program the source rate and execute a
 * specific sequence to switch to the new clock source for both memory
 * controllers. This can be used to control the balance between memory
 * throughput and memory controller power.
 */