path: root/include/linux/mfd/rtsx_pci.h

/* Driver for Realtek PCI-Express card reader
 *
 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2, or (at your option) any
 * later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * Author:
 *   Wei WANG <wei_wang@realsil.com.cn>
 */

#ifndef __RTSX_PCI_H
#define __RTSX_PCI_H

#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/mfd/rtsx_common.h>

#define MAX_RW_REG_CNT			1024

#define RTSX_HCBAR			0x00
#define RTSX_HCBCTLR			0x04
#define   STOP_CMD			(0x01 << 28)
#define   READ_REG_CMD			0
#define   WRITE_REG_CMD			1
#define   CHECK_REG_CMD			2

#define RTSX_HDBAR			0x08
#define   SG_INT			0x04
#define   SG_END			0x02
#define   SG_VALID			0x01
#define   SG_NO_OP			0x00
#define   SG_TRANS_DATA			(0x02 << 4)
#define   SG_LINK_DESC			(0x03 << 4)
#define RTSX_HDBCTLR			0x0C
#define   SDMA_MODE			0x00
#define   ADMA_MODE			(0x02 << 26)
#define   STOP_DMA			(0x01 << 28)
#define   TRIG_DMA			(0x01 << 31)

#define RTSX_HAIMR			0x10
#define   HAIMR_TRANS_START		(0x01 << 31)
#define   HAIMR_READ			0x00
#define   HAIMR_WRITE			(0x01 << 30)
#define   HAIMR_READ_START		(HAIMR_TRANS_START | HAIMR_READ)
#define   HAIMR_WRITE_START		(HAIMR_TRANS_START | HAIMR_WRITE)
#define   HAIMR_TRANS_END			(HAIMR_TRANS_START)

#define RTSX_BIPR			0x14
#define   CMD_DONE_INT			(1 << 31)
#define   DATA_DONE_INT			(1 << 30)
#define   TRANS_OK_INT			(1 << 29)
#define   TRANS_FAIL_INT		(1 << 28)
#define   XD_INT			(1 << 27)
#define   MS_INT			(1 << 26)
#define   SD_INT			(1 << 25)
#define   GPIO0_INT			(1 << 24)
#define   OC_INT			(1 << 23)
#define   SD_WRITE_PROTECT		(1 << 19)
#define   XD_EXIST			(1 << 18)
#define   MS_EXIST			(1 << 17)
#define   SD_EXIST			(1 << 16)
#define   DELINK_INT			GPIO0_INT
#define   MS_OC_INT			(1 << 23)
#define   SD_OC_INT			(1 << 22)

#define CARD_INT		(XD_INT | MS_INT | SD_INT)
#define NEED_COMPLETE_INT	(DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
#define RTSX_INT		(CMD_DONE_INT | NEED_COMPLETE_INT | \
					CARD_INT | GPIO0_INT | OC_INT)
#define CARD_EXIST		(XD_EXIST | MS_EXIST | SD_EXIST)

#define RTSX_BIER			0x18
#define   CMD_DONE_INT_EN		(1 << 31)
#define   DATA_DONE_INT_EN		(1 << 30)
#define   TRANS_OK_INT_EN		(1 << 29)
#define   TRANS_FAIL_INT_EN		(1 << 28)
#define   XD_INT_EN			(1 << 27)
#define   MS_INT_EN			(1 << 26)
#define   SD_INT_EN			(1 << 25)
#define   GPIO0_INT_EN			(1 << 24)
#define   OC_INT_EN			(1 << 23)
#define   DELINK_INT_EN			GPIO0_INT_EN
#define   MS_OC_INT_EN			(1 << 23)
#define   SD_OC_INT_EN			(1 << 22)


/*
 * macros for easy use
 */
#define rtsx_pci_writel(pcr, reg, value) \
	iowrite32(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readl(pcr, reg) \
	ioread32((pcr)->remap_addr + reg)
#define rtsx_pci_writew(pcr, reg, value) \
	iowrite16(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readw(pcr, reg) \
	ioread16((pcr)->remap_addr + reg)
#define rtsx_pci_writeb(pcr, reg, value) \
	iowrite8(value, (pcr)->remap_addr + reg)
#define rtsx_pci_readb(pcr, reg) \
	ioread8((pcr)->remap_addr + reg)

#define rtsx_pci_read_config_byte(pcr, where, val) \
	pci_read_config_byte((pcr)->pci, where, val)

#define rtsx_pci_write_config_byte(pcr, where, val) \
	pci_write_config_byte((pcr)->pci, where, val)

#define rtsx_pci_read_config_dword(pcr, where, val) \
	pci_read_config_dword((pcr)->pci, where, val)

#define rtsx_pci_write_config_dword(pcr, where, val) \
	pci_write_config_dword((pcr)->pci, where, val)

#define STATE_TRANS_NONE		0
#define STATE_TRANS_CMD			1
#define STATE_TRANS_BUF			2
#define STATE_TRANS_SG			3

#define TRANS_NOT_READY			0
#define TRANS_RESULT_OK			1
#define TRANS_RESULT_FAIL		2
#define TRANS_NO_DEVICE			3

#define RTSX_RESV_BUF_LEN		4096
#define HOST_CMDS_BUF_LEN		1024
#define HOST_SG_TBL_BUF_LEN		(RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
#define HOST_SG_TBL_ITEMS		(HOST_SG_TBL_BUF_LEN / 8)
#define MAX_SG_ITEM_LEN			0x80000
#define HOST_TO_DEVICE			0
#define DEVICE_TO_HOST			1

#define OUTPUT_3V3			0
#define OUTPUT_1V8			1

#define RTSX_PHASE_MAX			32
#define RX_TUNING_CNT			3

#define MS_CFG				0xFD40
#define   SAMPLE_TIME_RISING		0x00
#define   SAMPLE_TIME_FALLING		0x80
#define   PUSH_TIME_DEFAULT		0x00
#define   PUSH_TIME_ODD			0x40
#define   NO_EXTEND_TOGGLE		0x00
#define   EXTEND_TOGGLE_CHK		0x20
#define   MS_BUS_WIDTH_1		0x00
#define   MS_BUS_WIDTH_4		0x10
#define   MS_BUS_WIDTH_8		0x18
#define   MS_2K_SECTOR_MODE		0x04
#define   MS_512_SECTOR_MODE		0x00
#define   MS_TOGGLE_TIMEOUT_EN		0x00
#define   MS_TOGGLE_TIMEOUT_DISEN	0x01
#define MS_NO_CHECK_INT			0x02
#define MS_TPC				0xFD41
#define MS_TRANS_CFG			0xFD42
#define   WAIT_INT			0x80
#define   NO_WAIT_INT			0x00
#define   NO_AUTO_READ_INT_REG		0x00
#define   AUTO_READ_INT_REG		0x40
#define   MS_CRC16_ERR			0x20
#define   MS_RDY_TIMEOUT		0x10
#define   MS_INT_CMDNK			0x08
#define   MS_INT_BREQ			0x04
#define   MS_INT_ERR			0x02
#define   MS_INT_CED			0x01
#define MS_TRANSFER			0xFD43
#define   MS_TRANSFER_START		0x80
#define   MS_TRANSFER_END		0x40
#define   MS_TRANSFER_ERR		0x20
#define   MS_BS_STATE			0x10
#define   MS_TM_READ_BYTES		0x00
#define   MS_TM_NORMAL_READ		0x01
#define   MS_TM_WRITE_BYTES		0x04
#define   MS_TM_NORMAL_WRITE		0x05
#define   MS_TM_AUTO_READ		0x08
#define   MS_TM_AUTO_WRITE		0x0C
#define MS_INT_REG			0xFD44
#define MS_BYTE_CNT			0xFD45
#define MS_SECTOR_CNT_L			0xFD46
#define MS_SECTOR_CNT_H			0xFD47
#define MS_DBUS_H			0xFD48

#define SD_CFG1				0xFDA0
#define   SD_CLK_DIVIDE_0		0x00
#define   SD_CLK_DIVIDE_256		0xC0
#define   SD_CLK_DIVIDE_128		0x80
#define   SD_BUS_WIDTH_1BIT		0x00
#define   SD_BUS_WIDTH_4BIT		0x01
#define   SD_BUS_WIDTH_8BIT		0x02
#define   SD_ASYNC_FIFO_NOT_RST		0x10
#define   SD_20_MODE			0x00
#define   SD_DDR_MODE			0x04
#define   SD_30_MODE			0x08
#define   SD_CLK_DIVIDE_MASK		0xC0
#define SD_CFG2				0xFDA1
#define   SD_CALCULATE_CRC7		0x00
#define   SD_NO_CALCULATE_CRC7		0x80
#define   SD_CHECK_CRC16		0x00
#define   SD_NO_CHECK_CRC16		0x40
#define   SD_NO_CHECK_WAIT_CRC_TO	0x20
#define   SD_WAIT_BUSY_END		0x08
#define   SD_NO_WAIT_BUSY_END		0x00
#define   SD_CHECK_CRC7			0x00
#define   SD_NO_CHECK_CRC7		0x04
#define   SD_RSP_LEN_0			0x00
#define   SD_RSP_LEN_6			0x01
#define   SD_RSP_LEN_17			0x02
#define   SD_RSP_TYPE_R0		0x04
#define   SD_RSP_TYPE_R1		0x01
#define   SD_RSP_TYPE_R1b		0x09
#define   SD_RSP_TYPE_R2		0x02
#define   SD_RSP_TYPE_R3		0x05
#define   SD_RSP_TYPE_R4		0x05
#define   SD_RSP_TYPE_R5		0x01
#define   SD_RSP_TYPE_R6		0x01
#define   SD_RSP_TYPE_R7		0x01
#define SD_CFG3				0xFDA2
#define   SD_RSP_80CLK_TIMEOUT_EN	0x01

#define SD_STAT1			0xFDA3
#define   SD_CRC7_ERR			0x80
#define   SD_CRC16_ERR			0x40
#define   SD_CRC_WRITE_ERR		0x20
#define   SD_CRC_WRITE_ERR_MASK		0x1C
#define   GET_CRC_TIME_OUT		0x02
#define   SD_TUNING_COMPARE_ERR		0x01
#define SD_STAT2			0xFDA4
#define   SD_RSP_80CLK_TIMEOUT		0x01

#define SD_BUS_STAT			0xFDA5
#define   SD_CLK_TOGGLE_EN		0x80
#define   SD_CLK_FORCE_STOP		0x40
#define   SD_DAT3_STATUS		0x10
#define   SD_DAT2_STATUS		0x08
#define   SD_DAT1_STATUS		0x04
#define   SD_DAT0_STATUS		0x02
#define   SD_CMD_STATUS			0x01
#define SD_PAD_CTL			0xFDA6
#define   SD_IO_USING_1V8		0x80
#define   SD_IO_USING_3V3		0x7F
#define   TYPE_A_DRIVING		0x00
#define   TYPE_B_DRIVING		0x01
#define   TYPE_C_DRIVING		0x02
#define   TYPE_D_DRIVING		0x03
#define SD_SAMPLE_POINT_CTL		0xFDA7
#define   DDR_FIX_RX_DAT		0x00
#define   DDR_VAR_RX_DAT		0x80
#define   DDR_FIX_RX_DAT_EDGE		0x00
#define   DDR_FIX_RX_DAT_14_DELAY	0x40
#define   DDR_FIX_RX_CMD		0x00
#define   DDR_VAR_RX_CMD		0x20
#define   DDR_FIX_RX_CMD_POS_EDGE	0x00
#define   DDR_FIX_RX_CMD_14_DELAY	0x10
#define   SD20_RX_POS_EDGE		0x00
#define   SD20_RX_14_DELAY		0x08
#define SD20_RX_SEL_MASK		0x08
#define SD_PUSH_POINT_CTL		0xFDA8
#define   DDR_FIX_TX_CMD_DAT		0x00
#define   DDR_VAR_TX_CMD_DAT		0x80
#define   DDR_FIX_TX_DAT_14_TSU		0x00
#define   DDR_FIX_TX_DAT_12_TSU		0x40
#define   DDR_FIX_TX_CMD_NEG_EDGE	0x00
#define   DDR_FIX_TX_CMD_14_AHEAD	0x20
#define   SD20_TX_NEG_EDGE		0x00
#define   SD20_TX_14_AHEAD		0x10
#define   SD20_TX_SEL_MASK		0x10
#define   DDR_VAR_SDCLK_POL_SWAP	0x01
#define SD_CMD0				0xFDA9
#define   SD_CMD_START			0x40
#define SD_CMD1				0xFDAA
#define SD_CMD2				0xFDAB
#define SD_CMD3				0xFDAC
#define SD_CMD4				0xFDAD
#define SD_CMD5				0xFDAE
#define SD_BYTE_CNT_L			0xFDAF
#define SD_BYTE_CNT_H			0xFDB0
#define SD_BLOCK_CNT_L			0xFDB1
#define SD_BLOCK_CNT_H			0xFDB2
#define SD_TRANSFER			0xFDB3
#define   SD_TRANSFER_START		0x80
#define   SD_TRANSFER_END		0x40
#define   SD_STAT_IDLE			0x20
#define   SD_TRANSFER_ERR		0x10
#define   SD_TM_NORMAL_WRITE		0x00
#define   SD_TM_AUTO_WRITE_3		0x01
#define   SD_TM_AUTO_WRITE_4		0x02
#define   SD_TM_AUTO_READ_3		0x05
#define   SD_TM_AUTO_READ_4		0x06
#define   SD_TM_CMD_RSP			0x08
#define   SD_TM_AUTO_WRITE_1		0x09
#define   SD_TM_AUTO_WRITE_2		0x0A
#define   SD_TM_NORMAL_READ		0x0C
#define   SD_TM_AUTO_READ_1		0x0D
#define   SD_TM_AUTO_READ_2		0x0E
#define   SD_TM_AUTO_TUNING		0x0F
#define SD_CMD_STATE			0xFDB5
#define   SD_CM